Changeable registers:

name         | Addr           | (a)sync  |  r/w(*) | Interface          | init
--------------------------------------------------------------------------------------------------
freq_dev     | 0[0], 1[0-7]   |  ?       |  r/w    | XE1205PhyConf      |
bitrate      | 2[0-6]         |  ?       |  r/w    | XE1205PhyConf      |
freq_lo      | 3[0-7],4[0-7]  |  ?       |  r/w    | XE1205PhyConf      |
rx_irq_0     | 5[6-7]         | async    |  w	   | XE1205IrqConf      |
rx_irq_1     | 5[4-5]         | async    |  w      | XE1205IrqConf      |
tx_irq_1     | 5[3]           | async    |  w      | XE1205IrqConf      |
fifooverun   | 5[0]           | async    |  w      | XE1205IrqConf      |
start_detect | 6[6]           | async    |  w      | XE1205IrqConf      |
power        | 7[6-7]         |  ?       |  r/w    | XE1205PhyConf      |
bw           | 8[4-6]         | same as  |  w      | XE1205PhyConf      |
                              | bitrate  |         |                    |
rssi         | 9[7]           | async    |  w      | XE1205RssiConf     |
rssi_range   | 9[6]           | async    |  r/w    | XE1205RssiConf     |
rssi_out     | 9[4-5]         | async    |  r      | XE1205RssiConf     |
pattern      | 10[4]          | ?        |  w      | XE1205PatternConf  | *
pat_size     | 10[2-3]        | async    |  w      | XE1205PatternConf  | 
pat_tol      | 10[0-1]        | ?        |  w      | XE1205PatternConf  |
reg_pattern  | 13-16          | async    |  w      | XE1205PatternConf  |


(*) (at higher levels, reads my be cached)