-/* Reset all target-selection flags. */
-#define TARGET_NONE -(SH1_BIT | SH2_BIT | SH3_BIT | SH3E_BIT | SH4_BIT \
- | HARD_SH4_BIT | FPU_SINGLE_BIT | SH5_BIT)
-
-#define TARGET_SWITCHES \
-{ {"1", TARGET_NONE, "" }, \
- {"1", SH1_BIT, "" }, \
- {"2", TARGET_NONE, "" }, \
- {"2", SH2_BIT|SH1_BIT, "" }, \
- {"3", TARGET_NONE, "" }, \
- {"3", SH3_BIT|SH2_BIT|SH1_BIT, "" }, \
- {"3e", TARGET_NONE, "" }, \
- {"3e", SH3E_BIT|SH3_BIT|SH2_BIT|SH1_BIT|FPU_SINGLE_BIT, "" }, \
- {"4-single-only", TARGET_NONE, "" }, \
- {"4-single-only", SH3E_BIT|SH3_BIT|SH2_BIT|SH1_BIT|HARD_SH4_BIT|FPU_SINGLE_BIT, "" }, \
- {"4-single", TARGET_NONE, "" }, \
- {"4-single", SH4_BIT|SH3E_BIT|SH3_BIT|SH2_BIT|SH1_BIT|HARD_SH4_BIT|FPU_SINGLE_BIT, "" },\
- {"4-nofpu", TARGET_NONE, "" }, \
- {"4-nofpu", SH3_BIT|SH2_BIT|SH1_BIT|HARD_SH4_BIT, "" },\
- {"4", TARGET_NONE, "" }, \
- {"4", SH4_BIT|SH3E_BIT|SH3_BIT|SH2_BIT|SH1_BIT|HARD_SH4_BIT, "" }, \
- {"5-64media", TARGET_NONE, "" }, \
- {"5-64media", SH5_BIT|SH4_BIT, "Generate 64-bit SHmedia code" }, \
- {"5-64media-nofpu", TARGET_NONE, "" }, \
- {"5-64media-nofpu", SH5_BIT, "Generate 64-bit FPU-less SHmedia code" }, \
- {"5-32media", TARGET_NONE, "" }, \
- {"5-32media", SH5_BIT|SH4_BIT|SH3E_BIT, "Generate 32-bit SHmedia code" }, \
- {"5-32media-nofpu", TARGET_NONE, "" }, \
- {"5-32media-nofpu", SH5_BIT|SH3E_BIT, "Generate 32-bit FPU-less SHmedia code" }, \
- {"5-compact", TARGET_NONE, "" }, \
- {"5-compact", SH5_BIT|SH4_BIT|SH3E_BIT|SH3_BIT|SH2_BIT|SH1_BIT|FPU_SINGLE_BIT, "Generate SHcompact code" }, \
- {"5-compact-nofpu", TARGET_NONE, "" }, \
- {"5-compact-nofpu", SH5_BIT|SH3_BIT|SH2_BIT|SH1_BIT, "Generate FPU-less SHcompact code" }, \
- {"b", -LITTLE_ENDIAN_BIT, "" }, \
- {"bigtable", BIGTABLE_BIT, "" }, \
- {"dalign", DALIGN_BIT, "" }, \
- {"fmovd", FMOVD_BIT, "" }, \
- {"hitachi", HITACHI_BIT, "" }, \
- {"nomacsave", NOMACSAVE_BIT, "" }, \
- {"ieee", IEEE_BIT, "" }, \
- {"isize", ISIZE_BIT, "" }, \
- {"l", LITTLE_ENDIAN_BIT, "" }, \
- {"no-ieee", -IEEE_BIT, "" }, \
- {"padstruct", PADSTRUCT_BIT, "" }, \
- {"prefergot", PREFERGOT_BIT, "" }, \
- {"relax", RELAX_BIT, "" }, \
- {"space", SPACE_BIT, "" }, \
- {"usermode", USERMODE_BIT, "" }, \
- SUBTARGET_SWITCHES \
- {"", TARGET_DEFAULT, "" } \
-}
+#ifndef SUBTARGET_CPP_SPEC
+#define SUBTARGET_CPP_SPEC ""
+#endif
+
+#ifndef SUBTARGET_EXTRA_SPECS
+#define SUBTARGET_EXTRA_SPECS
+#endif
+
+#define EXTRA_SPECS \
+ { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
+ { "link_emul_prefix", LINK_EMUL_PREFIX }, \
+ { "link_default_cpu_emul", LINK_DEFAULT_CPU_EMUL }, \
+ { "subtarget_link_emul_suffix", SUBTARGET_LINK_EMUL_SUFFIX }, \
+ { "subtarget_link_spec", SUBTARGET_LINK_SPEC }, \
+ { "subtarget_asm_endian_spec", SUBTARGET_ASM_ENDIAN_SPEC }, \
+ { "subtarget_asm_relax_spec", SUBTARGET_ASM_RELAX_SPEC }, \
+ { "subtarget_asm_isa_spec", SUBTARGET_ASM_ISA_SPEC }, \
+ { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
+ SUBTARGET_EXTRA_SPECS
+
+#if TARGET_CPU_DEFAULT & MASK_HARD_SH4
+#define SUBTARGET_ASM_RELAX_SPEC "%{!m1:%{!m2:%{!m3*:%{!m5*:-isa=sh4-up}}}}"
+#else
+#define SUBTARGET_ASM_RELAX_SPEC "%{m4*:-isa=sh4-up}"
+#endif
+
+#define SH_ASM_SPEC \
+ "%(subtarget_asm_endian_spec) %{mrelax:-relax %(subtarget_asm_relax_spec)}\
+%(subtarget_asm_isa_spec) %(subtarget_asm_spec)\
+%{m2a:--isa=sh2a} \
+%{m2a-single:--isa=sh2a} \
+%{m2a-single-only:--isa=sh2a} \
+%{m2a-nofpu:--isa=sh2a-nofpu} \
+%{m5-compact*:--isa=SHcompact} \
+%{m5-32media*:--isa=SHmedia --abi=32} \
+%{m5-64media*:--isa=SHmedia --abi=64} \
+%{m4al:-dsp} %{mcut2-workaround:-cut2-workaround}"
+
+#define ASM_SPEC SH_ASM_SPEC
+
+#ifndef SUBTARGET_ASM_ENDIAN_SPEC
+#if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN
+#define SUBTARGET_ASM_ENDIAN_SPEC "%{mb:-big} %{!mb:-little}"
+#else
+#define SUBTARGET_ASM_ENDIAN_SPEC "%{ml:-little} %{!ml:-big}"
+#endif
+#endif
+
+#if STRICT_NOFPU == 1
+/* Strict nofpu means that the compiler should tell the assembler
+ to reject FPU instructions. E.g. from ASM inserts. */
+#if TARGET_CPU_DEFAULT & MASK_HARD_SH4 && !(TARGET_CPU_DEFAULT & MASK_SH_E)
+#define SUBTARGET_ASM_ISA_SPEC "%{!m1:%{!m2:%{!m3*:%{m4-nofpu|!m4*:%{!m5:-isa=sh4-nofpu}}}}}"
+#else
+/* If there were an -isa option for sh5-nofpu then it would also go here. */
+#define SUBTARGET_ASM_ISA_SPEC \
+ "%{m4-nofpu:-isa=sh4-nofpu} " ASM_ISA_DEFAULT_SPEC
+#endif
+#else /* ! STRICT_NOFPU */
+#define SUBTARGET_ASM_ISA_SPEC ASM_ISA_DEFAULT_SPEC
+#endif
+
+#ifndef SUBTARGET_ASM_SPEC
+#define SUBTARGET_ASM_SPEC ""
+#endif