+/******************************************************************************
+ USCI0 on MSP430F54xx
+ ******************************************************************************/
+
+#if defined(__MSP430_USCI5_BASE_0__)
+
+#define UCA0CTL0_ __MSP430_USCI5_BASE_0__ + 0x01 // USCI control 0 (sic)
+sfrb(UCA0CTL0, UCA0CTL0_);
+#define UCA0CTL1_ __MSP430_USCI5_BASE_0__ + 0x00 // USCI control 1 (sic)
+sfrb(UCA0CTL1, UCA0CTL1_);
+#define UCA0BRW_ __MSP430_USCI5_BASE_0__ + 0x06 // USCI baud rate word
+sfrw(UCA0BRW, UCA0BRW_);
+#define UCA0BR0_ __MSP430_USCI5_BASE_0__ + 0x06 // USCI baud rate 0
+sfrb(UCA0BR0, UCA0BR0_);
+#define UCA0BR1_ __MSP430_USCI5_BASE_0__ + 0x07 // USCI baud rate 1
+sfrb(UCA0BR1, UCA0BR1_);
+#define UCA0MCTL_ __MSP430_USCI5_BASE_0__ + 0x08 // USCI modulation control
+sfrb(UCA0MCTL, UCA0MCTL_);
+#define UCA0STAT_ __MSP430_USCI5_BASE_0__ + 0x0A // USCI status
+sfrb(UCA0STAT, UCA0STAT_);
+#define UCA0RXBUF_ __MSP430_USCI5_BASE_0__ + 0x0C // USCI receive buffer
+sfrb(UCA0RXBUF, UCA0RXBUF_);
+#define UCA0TXBUF_ __MSP430_USCI5_BASE_0__ + 0x0E // USCI transmit buffer
+sfrb(UCA0TXBUF, UCA0TXBUF_);
+#define UCA0ABCTL_ __MSP430_USCI5_BASE_0__ + 0x10 // USCI LIN control
+sfrb(UCA0ABCTL, UCA0ABCTL_);
+#define UCA0IRTCTL_ __MSP430_USCI5_BASE_0__ + 0x12 // USCI IrDA transmit control
+sfrb(UCA0IRTCTL, UCA0IRTCTL_);
+#define UCA0IRRCTL_ __MSP430_USCI5_BASE_0__ + 0x13 // USCI IrDA receive control
+sfrb(UCA0IRRCTL, UCA0IRRCTL_);
+#define UCA0IE_ __MSP430_USCI5_BASE_0__ + 0x1C // USCI interrupt enable
+sfrb(UCA0IE, UCA0IE_);
+#define UCA0IFG_ __MSP430_USCI5_BASE_0__ + 0x1D // USCI interrupt flags
+sfrb(UCA0IFG, UCA0IFG_);
+#define UCA0IV_ __MSP430_USCI5_BASE_0__ + 0x1E // USCI interrupt vector word
+sfrw(UCA0IV, UCA0IV_);
+#define UCA0IV_L_ __MSP430_USCI5_BASE_0__ + 0x1E
+sfrb(UCA0IV_L, UCA0IV_L_);
+#define UCA0IV_H_ __MSP430_USCI5_BASE_0__ + 0x1F
+sfrb(UCA0IV_H, UCA0IV_H_);
+
+#define UCB0CTL0_ __MSP430_USCI5_BASE_0__ + 0x20 // USCI synchronous control 0
+sfrb(UCB0CTL0, UCB0CTL0_);
+#define UCB0CTL1_ __MSP430_USCI5_BASE_0__ + 0x21 // USCI synchronous control 1
+sfrb(UCB0CTL1, UCB0CTL1_);
+#define UCB0BR0_ __MSP430_USCI5_BASE_0__ + 0x26 // USCI synchronous bit rate 0
+sfrb(UCB0BR0, UCB0BR0_);
+#define UCB0BR1_ __MSP430_USCI5_BASE_0__ + 0x27 // USCI synchronous bit rate 1
+sfrb(UCB0BR1, UCB0BR1_);
+#define UCB0MCTL_ __MSP430_USCI5_BASE_0__ + 0x28 // USCI I2C interrupt enable
+sfrb(UCB0MCTL, UCB0MCTL_);
+#define UCB0STAT_ __MSP430_USCI5_BASE_0__ + 0x2A // USCI synchronous status
+sfrb(UCB0STAT, UCB0STAT_);
+#define UCB0RXBUF_ __MSP430_USCI5_BASE_0__ + 0x2C // USCI synchronous receive buffer
+sfrb(UCB0RXBUF, UCB0RXBUF_);
+#define UCB0TXBUF_ __MSP430_USCI5_BASE_0__ + 0x2E // USCI synchronous transmit buffer
+sfrb(UCB0TXBUF, UCB0TXBUF_);
+#define UCB0I2COA_ __MSP430_USCI5_BASE_0__ + 0x30 // USCI I2C own address
+sfrb(UCB0I2COA, UCB0I2COA_);
+#define UCB0I2CSA_ __MSP430_USCI5_BASE_0__ + 0x32 // USCI I2C slave address
+sfrb(UCB0I2CSA, UCB0I2CSA_);
+#define UCB0IE_ __MSP430_USCI5_BASE_0__ + 0x3C // USCI interrupt enable
+sfrb(UCB0IE, UCB0IE_);
+#define UCB0IFG_ __MSP430_USCI5_BASE_0__ + 0x3D // USCI interrupt flags
+sfrb(UCB0IFG, UCB0IFG_);
+#define UCB0IV_ __MSP430_USCI5_BASE_0__ + 0x3E // USCI interrupt vector word
+sfrw(UCB0IV, UCB0IV_);
+#define UCB0IV_L_ __MSP430_USCI5_BASE_0__ + 0x3E
+sfrb(UCB0IV_L, UCB0IV_L_);
+#define UCB0IV_H_ __MSP430_USCI5_BASE_0__ + 0x3F
+sfrb(UCB0IV_H, UCB0IV_H_);
+
+#endif /* __MSP430_USCI5_BASE_0__ */
+
+/******************************************************************************
+ USCI1 on MSP430F54xx
+ ******************************************************************************/
+
+#if defined(__MSP430_USCI5_BASE_1__)
+
+#define UCA1CTL0_ __MSP430_USCI5_BASE_1__ + 0x01 // USCI control 0 (sic)
+sfrb(UCA1CTL0, UCA1CTL0_);
+#define UCA1CTL1_ __MSP430_USCI5_BASE_1__ + 0x00 // USCI control 1 (sic)
+sfrb(UCA1CTL1, UCA1CTL1_);
+#define UCA1BRW_ __MSP430_USCI5_BASE_1__ + 0x06 // USCI baud rate word
+sfrw(UCA1BRW, UCA1BRW_);
+#define UCA1BR0_ __MSP430_USCI5_BASE_1__ + 0x06 // USCI baud rate 0
+sfrb(UCA1BR0, UCA1BR0_);
+#define UCA1BR1_ __MSP430_USCI5_BASE_1__ + 0x07 // USCI baud rate 1
+sfrb(UCA1BR1, UCA1BR1_);
+#define UCA1MCTL_ __MSP430_USCI5_BASE_1__ + 0x08 // USCI modulation control
+sfrb(UCA1MCTL, UCA1MCTL_);
+#define UCA1STAT_ __MSP430_USCI5_BASE_1__ + 0x0A // USCI status
+sfrb(UCA1STAT, UCA1STAT_);
+#define UCA1RXBUF_ __MSP430_USCI5_BASE_1__ + 0x0C // USCI receive buffer
+sfrb(UCA1RXBUF, UCA1RXBUF_);
+#define UCA1TXBUF_ __MSP430_USCI5_BASE_1__ + 0x0E // USCI transmit buffer
+sfrb(UCA1TXBUF, UCA1TXBUF_);
+#define UCA1ABCTL_ __MSP430_USCI5_BASE_1__ + 0x10 // USCI LIN control
+sfrb(UCA1ABCTL, UCA1ABCTL_);
+#define UCA1IRTCTL_ __MSP430_USCI5_BASE_1__ + 0x12 // USCI IrDA transmit control
+sfrb(UCA1IRTCTL, UCA1IRTCTL_);
+#define UCA1IRRCTL_ __MSP430_USCI5_BASE_1__ + 0x13 // USCI IrDA receive control
+sfrb(UCA1IRRCTL, UCA1IRRCTL_);
+#define UCA1IE_ __MSP430_USCI5_BASE_1__ + 0x1C // USCI interrupt enable
+sfrb(UCA1IE, UCA1IE_);
+#define UCA1IFG_ __MSP430_USCI5_BASE_1__ + 0x1D // USCI interrupt flags
+sfrb(UCA1IFG, UCA1IFG_);
+#define UCA1IV_ __MSP430_USCI5_BASE_1__ + 0x1E // USCI interrupt vector word
+sfrw(UCA1IV, UCA1IV_);
+#define UCA1IV_L_ __MSP430_USCI5_BASE_1__ + 0x1E
+sfrb(UCA1IV_L, UCA1IV_L_);
+#define UCA1IV_H_ __MSP430_USCI5_BASE_1__ + 0x1F
+sfrb(UCA1IV_H, UCA1IV_H_);
+
+#define UCB1CTL0_ __MSP430_USCI5_BASE_1__ + 0x20 // USCI synchronous control 0
+sfrb(UCB1CTL0, UCB1CTL0_);
+#define UCB1CTL1_ __MSP430_USCI5_BASE_1__ + 0x21 // USCI synchronous control 1
+sfrb(UCB1CTL1, UCB1CTL1_);
+#define UCB1BR0_ __MSP430_USCI5_BASE_1__ + 0x26 // USCI synchronous bit rate 0
+sfrb(UCB1BR0, UCB1BR0_);
+#define UCB1BR1_ __MSP430_USCI5_BASE_1__ + 0x27 // USCI synchronous bit rate 1
+sfrb(UCB1BR1, UCB1BR1_);
+#define UCB1MCTL_ __MSP430_USCI5_BASE_1__ + 0x28 // USCI I2C interrupt enable
+sfrb(UCB1MCTL, UCB1MCTL_);
+#define UCB1STAT_ __MSP430_USCI5_BASE_1__ + 0x2A // USCI synchronous status
+sfrb(UCB1STAT, UCB1STAT_);
+#define UCB1RXBUF_ __MSP430_USCI5_BASE_1__ + 0x2C // USCI synchronous receive buffer
+sfrb(UCB1RXBUF, UCB1RXBUF_);
+#define UCB1TXBUF_ __MSP430_USCI5_BASE_1__ + 0x2E // USCI synchronous transmit buffer
+sfrb(UCB1TXBUF, UCB1TXBUF_);
+#define UCB1I2COA_ __MSP430_USCI5_BASE_1__ + 0x30 // USCI I2C own address
+sfrb(UCB1I2COA, UCB1I2COA_);
+#define UCB1I2CSA_ __MSP430_USCI5_BASE_1__ + 0x32 // USCI I2C slave address
+sfrb(UCB1I2CSA, UCB1I2CSA_);
+#define UCB1IE_ __MSP430_USCI5_BASE_1__ + 0x3C // USCI interrupt enable
+sfrb(UCB1IE, UCB1IE_);
+#define UCB1IFG_ __MSP430_USCI5_BASE_1__ + 0x3D // USCI interrupt flags
+sfrb(UCB1IFG, UCB1IFG_);
+#define UCB1IV_ __MSP430_USCI5_BASE_1__ + 0x3E // USCI interrupt vector word
+sfrw(UCB1IV, UCB1IV_);
+#define UCB1IV_L_ __MSP430_USCI5_BASE_1__ + 0x3E
+sfrb(UCB1IV_L, UCB1IV_L_);
+#define UCB1IV_H_ __MSP430_USCI5_BASE_1__ + 0x3F
+sfrb(UCB1IV_H, UCB1IV_H_);
+
+#endif /* __MSP430_USCI5_BASE_1__ */
+
+/******************************************************************************
+ USCI2 on MSP430F54xx
+ ******************************************************************************/
+
+#if defined(__MSP430_USCI5_BASE_2__)
+
+#define UCA2CTL0_ __MSP430_USCI5_BASE_2__ + 0x01 // USCI control 0 (sic)
+sfrb(UCA2CTL0, UCA2CTL0_);
+#define UCA2CTL1_ __MSP430_USCI5_BASE_2__ + 0x00 // USCI control 1 (sic)
+sfrb(UCA2CTL1, UCA2CTL1_);
+#define UCA2BRW_ __MSP430_USCI5_BASE_2__ + 0x06 // USCI baud rate word
+sfrw(UCA2BRW, UCA2BRW_);
+#define UCA2BR0_ __MSP430_USCI5_BASE_2__ + 0x06 // USCI baud rate 0
+sfrb(UCA2BR0, UCA2BR0_);
+#define UCA2BR1_ __MSP430_USCI5_BASE_2__ + 0x07 // USCI baud rate 1
+sfrb(UCA2BR1, UCA2BR1_);
+#define UCA2MCTL_ __MSP430_USCI5_BASE_2__ + 0x08 // USCI modulation control
+sfrb(UCA2MCTL, UCA2MCTL_);
+#define UCA2STAT_ __MSP430_USCI5_BASE_2__ + 0x0A // USCI status
+sfrb(UCA2STAT, UCA2STAT_);
+#define UCA2RXBUF_ __MSP430_USCI5_BASE_2__ + 0x0C // USCI receive buffer
+sfrb(UCA2RXBUF, UCA2RXBUF_);
+#define UCA2TXBUF_ __MSP430_USCI5_BASE_2__ + 0x0E // USCI transmit buffer
+sfrb(UCA2TXBUF, UCA2TXBUF_);
+#define UCA2ABCTL_ __MSP430_USCI5_BASE_2__ + 0x10 // USCI LIN control
+sfrb(UCA2ABCTL, UCA2ABCTL_);
+#define UCA2IRTCTL_ __MSP430_USCI5_BASE_2__ + 0x12 // USCI IrDA transmit control
+sfrb(UCA2IRTCTL, UCA2IRTCTL_);
+#define UCA2IRRCTL_ __MSP430_USCI5_BASE_2__ + 0x13 // USCI IrDA receive control
+sfrb(UCA2IRRCTL, UCA2IRRCTL_);
+#define UCA2IE_ __MSP430_USCI5_BASE_2__ + 0x1C // USCI interrupt enable
+sfrb(UCA2IE, UCA2IE_);
+#define UCA2IFG_ __MSP430_USCI5_BASE_2__ + 0x1D // USCI interrupt flags
+sfrb(UCA2IFG, UCA2IFG_);
+#define UCA2IV_ __MSP430_USCI5_BASE_2__ + 0x1E // USCI interrupt vector word
+sfrw(UCA2IV, UCA2IV_);
+#define UCA2IV_L_ __MSP430_USCI5_BASE_2__ + 0x1E
+sfrb(UCA2IV_L, UCA2IV_L_);
+#define UCA2IV_H_ __MSP430_USCI5_BASE_2__ + 0x1F
+sfrb(UCA2IV_H, UCA2IV_H_);
+
+#define UCB2CTL0_ __MSP430_USCI5_BASE_2__ + 0x20 // USCI synchronous control 0
+sfrb(UCB2CTL0, UCB2CTL0_);
+#define UCB2CTL1_ __MSP430_USCI5_BASE_2__ + 0x21 // USCI synchronous control 1
+sfrb(UCB2CTL1, UCB2CTL1_);
+#define UCB2BR0_ __MSP430_USCI5_BASE_2__ + 0x26 // USCI synchronous bit rate 0
+sfrb(UCB2BR0, UCB2BR0_);
+#define UCB2BR1_ __MSP430_USCI5_BASE_2__ + 0x27 // USCI synchronous bit rate 1
+sfrb(UCB2BR1, UCB2BR1_);
+#define UCB2MCTL_ __MSP430_USCI5_BASE_2__ + 0x28 // USCI I2C interrupt enable
+sfrb(UCB2MCTL, UCB2MCTL_);
+#define UCB2STAT_ __MSP430_USCI5_BASE_2__ + 0x2A // USCI synchronous status
+sfrb(UCB2STAT, UCB2STAT_);
+#define UCB2RXBUF_ __MSP430_USCI5_BASE_2__ + 0x2C // USCI synchronous receive buffer
+sfrb(UCB2RXBUF, UCB2RXBUF_);
+#define UCB2TXBUF_ __MSP430_USCI5_BASE_2__ + 0x2E // USCI synchronous transmit buffer
+sfrb(UCB2TXBUF, UCB2TXBUF_);
+#define UCB2I2COA_ __MSP430_USCI5_BASE_2__ + 0x30 // USCI I2C own address
+sfrb(UCB2I2COA, UCB2I2COA_);
+#define UCB2I2CSA_ __MSP430_USCI5_BASE_2__ + 0x32 // USCI I2C slave address
+sfrb(UCB2I2CSA, UCB2I2CSA_);
+#define UCB2IE_ __MSP430_USCI5_BASE_2__ + 0x3C // USCI interrupt enable
+sfrb(UCB2IE, UCB2IE_);
+#define UCB2IFG_ __MSP430_USCI5_BASE_2__ + 0x3D // USCI interrupt flags
+sfrb(UCB2IFG, UCB2IFG_);
+#define UCB2IV_ __MSP430_USCI5_BASE_2__ + 0x3E // USCI interrupt vector word
+sfrw(UCB2IV, UCB2IV_);
+#define UCB2IV_L_ __MSP430_USCI5_BASE_2__ + 0x3E
+sfrb(UCB2IV_L, UCB2IV_L_);
+#define UCB2IV_H_ __MSP430_USCI5_BASE_2__ + 0x3F
+sfrb(UCB2IV_H, UCB2IV_H_);
+
+#endif /* __MSP430_USCI5_BASE_2__ */
+
+/******************************************************************************
+ USCI3 on MSP430F54xx
+ ******************************************************************************/
+
+#if defined(__MSP430_USCI5_BASE_3__)
+
+#define UCA3CTL0_ __MSP430_USCI5_BASE_3__ + 0x01 // USCI control 0 (sic)
+sfrb(UCA3CTL0, UCA3CTL0_);
+#define UCA3CTL1_ __MSP430_USCI5_BASE_3__ + 0x00 // USCI control 1 (sic)
+sfrb(UCA3CTL1, UCA3CTL1_);
+#define UCA3BRW_ __MSP430_USCI5_BASE_3__ + 0x06 // USCI baud rate word
+sfrw(UCA3BRW, UCA3BRW_)
+#define UCA3BR0_ __MSP430_USCI5_BASE_3__ + 0x06 // USCI baud rate 0
+sfrb(UCA3BR0, UCA3BR0_);
+#define UCA3BR1_ __MSP430_USCI5_BASE_3__ + 0x07 // USCI baud rate 1
+sfrb(UCA3BR1, UCA3BR1_);
+#define UCA3MCTL_ __MSP430_USCI5_BASE_3__ + 0x08 // USCI modulation control
+sfrb(UCA3MCTL, UCA3MCTL_);
+#define UCA3STAT_ __MSP430_USCI5_BASE_3__ + 0x0A // USCI status
+sfrb(UCA3STAT, UCA3STAT_);
+#define UCA3RXBUF_ __MSP430_USCI5_BASE_3__ + 0x0C // USCI receive buffer
+sfrb(UCA3RXBUF, UCA3RXBUF_);
+#define UCA3TXBUF_ __MSP430_USCI5_BASE_3__ + 0x0E // USCI transmit buffer
+sfrb(UCA3TXBUF, UCA3TXBUF_);
+#define UCA3ABCTL_ __MSP430_USCI5_BASE_3__ + 0x10 // USCI LIN control
+sfrb(UCA3ABCTL, UCA3ABCTL_);
+#define UCA3IRTCTL_ __MSP430_USCI5_BASE_3__ + 0x12 // USCI IrDA transmit control
+sfrb(UCA3IRTCTL, UCA3IRTCTL_);
+#define UCA3IRRCTL_ __MSP430_USCI5_BASE_3__ + 0x13 // USCI IrDA receive control
+sfrb(UCA3IRRCTL, UCA3IRRCTL_);
+#define UCA3IE_ __MSP430_USCI5_BASE_3__ + 0x1C // USCI interrupt enable
+sfrb(UCA3IE, UCA3IE_);
+#define UCA3IFG_ __MSP430_USCI5_BASE_3__ + 0x1D // USCI interrupt flags
+sfrb(UCA3IFG, UCA3IFG_);
+#define UCA3IV_ __MSP430_USCI5_BASE_3__ + 0x1E // USCI interrupt vector word
+sfrw(UCA3IV, UCA3IV_);
+#define UCA3IV_L_ __MSP430_USCI5_BASE_3__ + 0x1E
+sfrb(UCA3IV_L, UCA3IV_L_);
+#define UCA3IV_H_ __MSP430_USCI5_BASE_3__ + 0x1F
+sfrb(UCA3IV_H, UCA3IV_H_);
+
+#define UCB3CTL0_ __MSP430_USCI5_BASE_3__ + 0x20 // USCI synchronous control 0
+sfrb(UCB3CTL0, UCB3CTL0_);
+#define UCB3CTL1_ __MSP430_USCI5_BASE_3__ + 0x21 // USCI synchronous control 1
+sfrb(UCB3CTL1, UCB3CTL1_);
+#define UCB3BR0_ __MSP430_USCI5_BASE_3__ + 0x26 // USCI synchronous bit rate 0
+sfrb(UCB3BR0, UCB3BR0_);
+#define UCB3BR1_ __MSP430_USCI5_BASE_3__ + 0x27 // USCI synchronous bit rate 1
+sfrb(UCB3BR1, UCB3BR1_);
+#define UCB3MCTL_ __MSP430_USCI5_BASE_3__ + 0x28 // USCI I2C interrupt enable
+sfrb(UCB3MCTL, UCB3MCTL_);
+#define UCB3STAT_ __MSP430_USCI5_BASE_3__ + 0x2A // USCI synchronous status
+sfrb(UCB3STAT, UCB3STAT_);
+#define UCB3RXBUF_ __MSP430_USCI5_BASE_3__ + 0x2C // USCI synchronous receive buffer
+sfrb(UCB3RXBUF, UCB3RXBUF_);
+#define UCB3TXBUF_ __MSP430_USCI5_BASE_3__ + 0x2E // USCI synchronous transmit buffer
+sfrb(UCB3TXBUF, UCB3TXBUF_);
+#define UCB3I2COA_ __MSP430_USCI5_BASE_3__ + 0x30 // USCI I2C own address
+sfrb(UCB3I2COA, UCB3I2COA_);
+#define UCB3I2CSA_ __MSP430_USCI5_BASE_3__ + 0x32 // USCI I2C slave address
+sfrb(UCB3I2CSA, UCB3I2CSA_);
+#define UCB3IE_ __MSP430_USCI5_BASE_3__ + 0x3C // USCI interrupt enable
+sfrb(UCB3IE, UCB3IE_);
+#define UCB3IFG_ __MSP430_USCI5_BASE_3__ + 0x3D // USCI interrupt flags
+sfrb(UCB3IFG, UCB3IFG_);
+#define UCB3IV_ __MSP430_USCI5_BASE_3__ + 0x3E // USCI interrupt vector word
+sfrw(UCB3IV, UCB3IV_);
+#define UCB3IV_L_ __MSP430_USCI5_BASE_3__ + 0x3E
+sfrb(UCB3IV_L, UCB3IV_L_);
+#define UCB3IV_H_ __MSP430_USCI5_BASE_3__ + 0x3F
+sfrb(UCB3IV_H, UCB3IV_H_);
+
+#endif /* __MSP430_USCI5_BASE_3__ */
+
+#endif /* __MSP430_HEADERS_USCI_H__ */