X-Git-Url: https://oss.titaniummirror.com/gitweb/?a=blobdiff_plain;f=doc%2Fhtml%2Ftep117.html;h=2f84dc7abfb89549521cc33dcaa32ac06f161fff;hb=826bb539a6c489db5b216e7326bf693ec67d15e5;hp=077bb58acbbd913edf7387d9583c518928db15bc;hpb=e375f4f25e4f47409d09d6a13f57aff159c20886;p=tinyos-2.x.git diff --git a/doc/html/tep117.html b/doc/html/tep117.html index 077bb58a..2f84dc7a 100644 --- a/doc/html/tep117.html +++ b/doc/html/tep117.html @@ -3,7 +3,7 @@ - + Low-Level I/O -

Low-Level I/O

@@ -303,14 +302,15 @@ ul.auto-toc { - + - +
Phil Buonadonna, Jonathan Hui
Draft-Created:23-Jan-2006
Draft-Version:1.1.2.9
Draft-Version:1.5
Draft-Modified:2006-09-30
Draft-Modified:2006-12-12
Draft-Discuss:TinyOS Developer List <tinyos-devel at mail.millennium.berkeley.edu>
+

Note

This memo documents a part of TinyOS for the TinyOS Community, and @@ -318,13 +318,13 @@ requests discussion and suggestions for improvements. Distribution of this memo is unlimited. This memo is in full compliance with TEP 1.

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Abstract

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Abstract

The memo documents the TinyOS 2.x interfaces used for controlling digital IO functionality and digital interfaces.

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1. Introduction

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1. Introduction

The canonical TinyOS device is likely to have a variety of digital interfaces. These interfaces may be divided into two broad categories. The first are general purpose digital I/O lines (pins) for @@ -338,8 +338,8 @@ bus formats, we presume SPI, I2C, and UART to have the largest coverage.

This memo documents the interfaces used for pins and the three buses.

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2. Pins

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2. Pins

General Purpose I/O (GPIO) pins are single, versatile digital I/O signals individually controllable on a particular chip or platform. Each GPIO can be placed into either an input mode or an @@ -380,8 +380,8 @@ interfaces:

  • GpioCapture
  • -
    -

    2.1 GeneralIO

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    2.1 GeneralIO

    The GeneralIO HIL interface is the fundamental mechanism for controlling a GPIO pin. The interface provides a mechanism for setting the pin mode and reading/setting the pin value. The toggle function switches the @@ -403,8 +403,8 @@ interface GeneralIO }

    -
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    2.2 GpioInterrupt

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    2.2 GpioInterrupt

    The GPIO Interrupt HIL interface provides baseline event control for a GPIO pin. It provides a mechanism to detect a rising edge OR a falling edge. Note that calls to enableRisingEdge and enableFallingEdge are @@ -424,8 +424,8 @@ interface GpioInterrupt { }

    -
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    2.3 GpioCapture

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    2.3 GpioCapture

    The GpioCapture interface provides a means of associating a timestamp with a GPIO event. Platforms MAY provide this interface.

    Some platforms may have hardware support for such a feature. Other @@ -447,14 +447,14 @@ interface GpioCapture {

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    3. Buses

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    3. Buses

    Bus operations may be divided into two categories: data and control. The control operations of a particular bus controller are platform specific and not covered here. Instead, we focus on the data interfaces at the HIL level that are expected to be provided.

    -
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    3.1 Serial Peripheral Interface

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    3.1 Serial Peripheral Interface

    The Serial Peripheral Interface (SPI) is part of a larger class of Synchronous Serial Protocols. The term SPI typically refers to the Motorola SPI protocols. Other protocols include the National @@ -484,8 +484,8 @@ interface SpiPacket { }

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    3.2 I2C

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    3.2 I2C

    The Inter-Integrated Circuit (I2C) interface is another type of digital bus that is often used for chip-to-chip communication. It is also known as a two-wire interface.

    @@ -506,7 +506,7 @@ interface I2CPacket<addr_size> {

    The interface is typed according to the addressing space the underlying implementation supports. Valid type values are below.

    -TI2CExtdAddr - Interfaces uses the extended (10-bit) addressing mode.
    +TI2CExtdAddr - Interfaces uses the extended (10-bit) addressing mode. 
     TI2CBasicAddr - Interfaces uses the basic (7-bit) addressing mode.
     

    The i2c_flags_t values are defined below. The flags define the @@ -516,12 +516,12 @@ ORed together.

    I2C_START - Transmit an I2C STOP at the beginning of the operation. I2C_STOP - Transmit an I2C STOP at the end of the operation. Cannot be used with the I2C_ACK_END flag. -I2C_ACK_END - ACK the last byte sent from the buffer. This flags is only valid +I2C_ACK_END - ACK the last byte sent from the buffer. This flags is only valid a write operation. Cannot be used with the I2C_STOP flag.
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    3.3 UART

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    3.3 UART

    The Universal Asynchronous Receiver/Transmitter (UART) interface is a type of serial interconnect. The interface is "asynchronous" since it recovers timing from the data stream itself, rather than a separate @@ -539,11 +539,11 @@ enabled, the enableReceiveInterrupt command MUST return FAIL.

    interface UartStream { async command error_t send( uint8_t* buf, uint16_t len ); async event void sendDone( uint8_t* buf, uint16_t len, error_t error ); - + async command error_t enableReceiveInterrupt(); async command error_t disableReceiveInterrupt(); async event void receivedByte( uint8_t byte ); - + async command error_t receive( uint8_t* buf, uint8_t len ); async event void receiveDone( uint8_t* buf, uint16_t len, error_t error ); } @@ -563,8 +563,8 @@ interface UartByte {
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    4. Implementation

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    4. Implementation

    Example implementations of the pin interfaces can be found in tos/chips/msp430/pins, tos/chips/atm128/pins, and tos/chips/pxa27x/gpio.

    Example implementations of the SPI interfaces can be found in tos/chips/msp430/usart, @@ -574,8 +574,8 @@ tos/chips/atm128/i2c, and tos/chips/pxa27x/i2c.

    Example implementations of the UART interfaces can be found in tos/chips/msp430/usart, tos/chips/atm128/uart/ and tos/chips/pxa27x/uart.

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    5. Author's Address

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    5. Author's Address

    Phil Buonadonna
    Arch Rock Corporation
    @@ -593,8 +593,8 @@ tos/chips/atm128/uart/ and tos/chips/pxa27x/uart.

    phone - +1 415 692-0828 x2835
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