X-Git-Url: https://oss.titaniummirror.com/gitweb/?a=blobdiff_plain;f=gcc%2Fconfig%2Fi386%2Fi386-modes.def;fp=gcc%2Fconfig%2Fi386%2Fi386-modes.def;h=9c948026f7544b1b27223e66dbfac1c1a7f6e2cc;hb=6fed43773c9b0ce596dca5686f37ac3fc0fa11c0;hp=0000000000000000000000000000000000000000;hpb=27b11d56b743098deb193d510b337ba22dc52e5c;p=msp430-gcc.git diff --git a/gcc/config/i386/i386-modes.def b/gcc/config/i386/i386-modes.def new file mode 100644 index 00000000..9c948026 --- /dev/null +++ b/gcc/config/i386/i386-modes.def @@ -0,0 +1,92 @@ +/* Definitions of target machine for GCC for IA-32. + Copyright (C) 2002, 2004, 2005, 2007, 2008 Free Software Foundation, Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3, or (at your option) +any later version. + +GCC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GCC; see the file COPYING3. If not see +. */ + +/* The x86_64 ABI specifies both XF and TF modes. + XFmode is __float80 is IEEE extended; TFmode is __float128 + is IEEE quad. */ + +FRACTIONAL_FLOAT_MODE (XF, 80, 12, ieee_extended_intel_96_format); +FLOAT_MODE (TF, 16, ieee_quad_format); + +/* In ILP32 mode, XFmode has size 12 and alignment 4. + In LP64 mode, XFmode has size and alignment 16. */ +ADJUST_FLOAT_FORMAT (XF, (TARGET_128BIT_LONG_DOUBLE + ? &ieee_extended_intel_128_format + : TARGET_96_ROUND_53_LONG_DOUBLE + ? &ieee_extended_intel_96_round_53_format + : &ieee_extended_intel_96_format)); +ADJUST_BYTESIZE (XF, TARGET_128BIT_LONG_DOUBLE ? 16 : 12); +ADJUST_ALIGNMENT (XF, TARGET_128BIT_LONG_DOUBLE ? 16 : 4); + +/* Add any extra modes needed to represent the condition code. + + For the i386, we need separate modes when floating-point + equality comparisons are being done. + + Add CCNO to indicate comparisons against zero that requires + Overflow flag to be unset. Sign bit test is used instead and + thus can be used to form "a&b>0" type of tests. + + Add CCGC to indicate comparisons against zero that allows + unspecified garbage in the Carry flag. This mode is used + by inc/dec instructions. + + Add CCGOC to indicate comparisons against zero that allows + unspecified garbage in the Carry and Overflow flag. This + mode is used to simulate comparisons of (a-b) and (a+b) + against zero using sub/cmp/add operations. + + Add CCA to indicate that only the Above flag is valid. + Add CCC to indicate that only the Carry flag is valid. + Add CCO to indicate that only the Overflow flag is valid. + Add CCS to indicate that only the Sign flag is valid. + Add CCZ to indicate that only the Zero flag is valid. */ + +CC_MODE (CCGC); +CC_MODE (CCGOC); +CC_MODE (CCNO); +CC_MODE (CCA); +CC_MODE (CCC); +CC_MODE (CCO); +CC_MODE (CCS); +CC_MODE (CCZ); +CC_MODE (CCFP); +CC_MODE (CCFPU); + +/* Vector modes. */ +VECTOR_MODES (INT, 4); /* V4QI V2HI */ +VECTOR_MODES (INT, 8); /* V8QI V4HI V2SI */ +VECTOR_MODES (INT, 16); /* V16QI V8HI V4SI V2DI */ +VECTOR_MODES (INT, 32); /* V32QI V16HI V8SI V4DI */ +VECTOR_MODES (FLOAT, 8); /* V4HF V2SF */ +VECTOR_MODES (FLOAT, 16); /* V8HF V4SF V2DF */ +VECTOR_MODES (FLOAT, 32); /* V16HF V8SF V4DF */ +VECTOR_MODE (INT, DI, 1); /* V1DI */ +VECTOR_MODE (INT, SI, 1); /* V1SI */ +VECTOR_MODE (INT, QI, 2); /* V2QI */ +VECTOR_MODE (INT, DI, 8); /* V8DI */ +VECTOR_MODE (INT, HI, 32); /* V32HI */ +VECTOR_MODE (INT, QI, 64); /* V64QI */ +VECTOR_MODE (FLOAT, DF, 8); /* V8DF */ +VECTOR_MODE (FLOAT, SF, 16); /* V16SF */ + +INT_MODE (OI, 32); + +/* The symbol Pmode stands for one of the above machine modes (usually SImode). + The tm.h file specifies which one. It is not a distinct mode. */