X-Git-Url: https://oss.titaniummirror.com/gitweb/?a=blobdiff_plain;f=include%2Fmsp430%2Fsd16.h;h=1faaeb97066069f00a298b3f61adb629cdf2c3c0;hb=6f720ff00773571c2fa2d35e67bff68547617639;hp=fcbd35857728124f96009ca92ff73b7a05eed303;hpb=807b2dd5b7365eb87b482197af3b4a3f520c14f7;p=msp430-libc.git diff --git a/include/msp430/sd16.h b/include/msp430/sd16.h index fcbd358..1faaeb9 100644 --- a/include/msp430/sd16.h +++ b/include/msp430/sd16.h @@ -9,24 +9,30 @@ * (c) 2003 by Steve Underwood * Originally based in part on work by Texas Instruments Inc. * - * $Id: sd16.h,v 1.8 2006/12/26 10:33:14 coppice Exp $ + * $Id: sd16.h,v 1.10 2009/01/11 23:11:48 sb-sf Exp $ */ /* Switches: +__MSP430_SD16IV_BASE__ - SD16IV register address +__MSP430_SD16MEM_BASE__ - SD16MEM0 register address -__msp430_have_sd16a - the SD16 is the "A" type -__msp430_have_sd16_1 -__msp430_have_sd16_2 +__MSP430_HAS_SD16_A__ - the SD16 is the "A" type +__MSP430_HAS_SD16_BUF__ - the SD16(_A) has input buffer and SD16AE reg. +__MSP430_HAS_SD16_CH1__ - the SD16(_A) has channel 1 +__MSP430_HAS_SD16_CH2__ - the SD16(_A) has channel 2 +__MSP430_HAS_SD16_CH3__ - the SD16(_A) has channel 3 */ #define SD16CTL_ 0x0100 /* Sigma Delta ADC 16 Control Register */ sfrw(SD16CTL, SD16CTL_); -#define SD16IV_ 0x0110 /* SD16 Interrupt Vector Register */ +#define SD16IV_ __MSP430_SD16IV_BASE__ /* SD16 Interrupt Vector Register */ sfrw(SD16IV, SD16IV_); -#if defined(__msp430_have_sd16a) +#if defined(__MSP430_HAS_SD16_A__) +#if defined(__MSP430_HAS_SD16_BUF__) #define SD16AE_ 0x00B7 /* SD16 Analog Input Enable Register */ sfrb(SD16AE, SD16AE_); +#endif #else #define SD16CONF0_ 0x00B7 /* SD16 Internal Configuration Register 0 */ sfrb(SD16CONF0, SD16CONF0_); @@ -41,32 +47,76 @@ sfrb(SD16INCTL0, SD16INCTL0_); sfrb(SD16PRE0, SD16PRE0_); #define SD16CCTL0_ 0x0102 /* SD16 Channel 0 Control Register */ sfrw(SD16CCTL0, SD16CCTL0_); -#define SD16MEM0_ 0x0112 /* SD16 Channel 0 Conversion Memory */ +#define SD16MEM0_ __MSP430_SD16MEM_BASE__ + 0x00 /* SD16 Channel 0 Conversion Memory */ sfrw(SD16MEM0, SD16MEM0_); -#if defined(__msp430_have_sd16_1) +#if defined(__MSP430_HAS_SD16_CH1__) #define SD16INCTL1_ 0x00B1 /* SD16 Input Control Register Channel 1 */ sfrb(SD16INCTL1, SD16INCTL1_); #define SD16PRE1_ 0x00B9 /* SD16 Preload Register Channel 1 */ sfrb(SD16PRE1, SD16PRE1_); #define SD16CCTL1_ 0x0104 /* SD16 Channel 1 Control Register */ sfrw(SD16CCTL1, SD16CCTL1_); -#define SD16MEM1_ 0x0114 /* SD16 Channel 1 Conversion Memory */ +#define SD16MEM1_ __MSP430_SD16MEM_BASE__ + 0x02 /* SD16 Channel 1 Conversion Memory */ sfrw(SD16MEM1, SD16MEM1_); #endif -#if defined(__msp430_have_sd16_2) +#if defined(__MSP430_HAS_SD16_CH2__) #define SD16INCTL2_ 0x00B2 /* SD16 Input Control Register Channel 2 */ sfrb(SD16INCTL2, SD16INCTL2_); #define SD16PRE2_ 0x00BA /* SD16 Preload Register Channel 2 */ sfrb(SD16PRE2, SD16PRE2_); #define SD16CCTL2_ 0x0106 /* SD16 Channel 2 Control Register */ sfrw(SD16CCTL2, SD16CCTL2_); -#define SD16MEM2_ 0x0116 /* SD16 Channel 2 Conversion Memory */ +#define SD16MEM2_ __MSP430_SD16MEM_BASE__ + 0x04 /* SD16 Channel 2 Conversion Memory */ sfrw(SD16MEM2, SD16MEM2_); #endif -#if defined(__msp430_have_sd16a) +#if defined(__MSP430_HAS_SD16_CH3__) +#define SD16INCTL3_ 0x00B3 /* SD16 Input Control Register Channel 3 */ +sfrb(SD16INCTL3, SD16INCTL3_); +#define SD16PRE3_ 0x00BB /* SD16 Preload Register Channel 3 */ +sfrb(SD16PRE3, SD16PRE3_); +#define SD16CCTL3_ 0x0108 /* SD16 Channel 3 Control Register */ +sfrw(SD16CCTL3, SD16CCTL3_); +#define SD16MEM3_ __MSP430_SD16MEM_BASE__ + 0x06 /* SD16 Channel 3 Conversion Memory */ +sfrw(SD16MEM3, SD16MEM3_); +#endif + +#if defined(__MSP430_HAS_SD16_CH4__) +#define SD16INCTL4_ 0x00B4 /* SD16 Input Control Register Channel 4 */ +sfrb(SD16INCTL4, SD16INCTL4_); +#define SD16PRE4_ 0x00BC /* SD16 Preload Register Channel 4 */ +sfrb(SD16PRE4, SD16PRE4_); +#define SD16CCTL4_ 0x010A /* SD16 Channel 4 Control Register */ +sfrw(SD16CCTL4, SD16CCTL4_); +#define SD16MEM4_ __MSP430_SD16MEM_BASE__ + 0x08 /* SD16 Channel 4 Conversion Memory */ +sfrw(SD16MEM4, SD16MEM4_); +#endif + +#if defined(__MSP430_HAS_SD16_CH5__) +#define SD16INCTL5_ 0x00B5 /* SD16 Input Control Register Channel 5 */ +sfrb(SD16INCTL5, SD16INCTL5_); +#define SD16PRE5_ 0x00BD /* SD16 Preload Register Channel 5 */ +sfrb(SD16PRE5, SD16PRE5_); +#define SD16CCTL5_ 0x010C /* SD16 Channel 5 Control Register */ +sfrw(SD16CCTL5, SD16CCTL5_); +#define SD16MEM5_ __MSP430_SD16MEM_BASE__ + 0x0A /* SD16 Channel 5 Conversion Memory */ +sfrw(SD16MEM5, SD16MEM5_); +#endif + +#if defined(__MSP430_HAS_SD16_CH6__) +#define SD16INCTL6_ 0x00B6 /* SD16 Input Control Register Channel 6 */ +sfrb(SD16INCTL6, SD16INCTL6_); +#define SD16PRE6_ 0x00BE /* SD16 Preload Register Channel 6 */ +sfrb(SD16PRE6, SD16PRE6_); +#define SD16CCTL6_ 0x010E /* SD16 Channel 6 Control Register */ +sfrw(SD16CCTL6, SD16CCTL6_); +#define SD16MEM6_ __MSP430_SD16MEM_BASE__ + 0x0C /* SD16 Channel 6 Conversion Memory */ +sfrw(SD16MEM6, SD16MEM6_); +#endif + +#if defined(__MSP430_HAS_SD16_A__) /* SD16AE */ #define SD16AE0 0x0001 /* SD16 External Input Enable 0 */ #define SD16AE1 0x0002 /* SD16 External Input Enable 1 */ @@ -118,7 +168,7 @@ sfrw(SD16MEM2, SD16MEM2_); #define SD16DIV0 0x0040 /* SD16 Clock Divider Select 0 */ #define SD16DIV1 0x0080 /* SD16 Clock Divider Select 1 */ #define SD16LP 0x0100 /* SD16 Low Power Mode Enable */ -#if defined(__msp430_have_sd16a) +#if defined(__MSP430_HAS_SD16_A__) #define SD16XDIV0 0x0200 /* SD16 2.Clock Divider Select 0 */ #define SD16XDIV1 0x0400 /* SD16 2.Clock Divider Select 1 */ //#define SD16XDIV2 0x0800) /* SD16 2.Clock Divider Select 2 */ @@ -129,7 +179,7 @@ sfrw(SD16MEM2, SD16MEM2_); #define SD16DIV_2 (SD16DIV1) /* SD16 Clock Divider Select /4 */ #define SD16DIV_3 (SD16DIV0|SD16DIV1) /* SD16 Clock Divider Select /8 */ -#if defined(__msp430_have_sd16a) +#if defined(__MSP430_HAS_SD16_A__) #define SD16XDIV_0 (0x0000) /* SD16 2.Clock Divider Select /1 */ #define SD16XDIV_1 (SD16XDIV0) /* SD16 2.Clock Divider Select /3 */ #define SD16XDIV_2 (SD16XDIV1) /* SD16 2.Clock Divider Select /16 */ @@ -153,7 +203,7 @@ sfrw(SD16MEM2, SD16MEM2_); #define SD16OSR0 0x0100 /* SD16 Channel x OverSampling Ratio 0 */ #define SD16OSR1 0x0200 /* SD16 Channel x OverSampling Ratio 1 */ #define SD16SNGL 0x0400 /* SD16 Channel x Single Conversion On/Off */ -#if defined(__msp430_have_sd16a) +#if defined(__MSP430_HAS_SD16_A__) #define SD16XOSR 0x0800 /* SD16 Channel x Extended OverSampling Ratio */ #define SD16UNI 0x1000 /* SD16 Channel x Bipolar(0) / Unipolar(1) Mode */ #define SD16BUF0 0x2000 /* SD16 Channel x High Impedance Input Buffer Select: 0 */ @@ -161,7 +211,7 @@ sfrw(SD16MEM2, SD16MEM2_); #define SD16BUFG 0x8000 /* SD16 Channel x Buffer Gain 0:Gain=1 / 1:Gain=2 */ #endif -#if defined(__msp430_have_sd16a) +#if defined(__MSP430_HAS_SD16_A__) #define SD16OSR_1024 (SD16XOSR|SD16OSR0) /* SD16 Channel x OverSampling Ratio 1024 */ #define SD16OSR_512 (SD16XOSR) /* SD16 Channel x OverSampling Ratio 512 */ #endif @@ -170,14 +220,14 @@ sfrw(SD16MEM2, SD16MEM2_); #define SD16OSR_64 (2<<8) /* SD16 Channel x OverSampling Ratio 64 */ #define SD16OSR_32 (3<<8) /* SD16 Channel x OverSampling Ratio 32 */ -#if defined(__msp430_have_sd16a) +#if defined(__MSP430_HAS_SD16_A__) #define SD16BUF_0 (0<<13) /* SD16 High Imp. Input Buffer: Disabled */ #define SD16BUF_1 (1<<13) /* SD16 High Imp. Input Buffer: Slow */ #define SD16BUF_2 (2<<13) /* SD16 High Imp. Input Buffer: Meduim */ #define SD16BUF_3 (3<<13) /* SD16 High Imp. Input Buffer: Fast */ #endif -#if !defined(__msp430_have_sd16a) +#if !defined(__MSP430_HAS_SD16_A__) #define AFEINCTL0 SD16INCTL0 /* SD16 Input Control Register Channel 0 */ #define AFEINCTL1 SD16INCTL1 /* SD16 Input Control Register Channel 1 */ #define AFEINCTL2 SD16INCTL2 /* SD16 Input Control Register Channel 2 */ @@ -194,7 +244,7 @@ sfrw(SD16MEM2, SD16MEM2_); #define SD16DIV_DIV4 SD16DIV_2 /* SD16 Clock Divider Select /4 */ #define SD16DIV_DIV8 SD16DIV_3 /* SD16 Clock Divider Select /8 */ -#if defined(__msp430_have_sd16a) +#if defined(__MSP430_HAS_SD16_A__) #define SD16XDIV_DIV1 SD16XDIV_0 /* SD16 2.Clock Divider Select /1 */ #define SD16XDIV_DIV2 SD16XDIV_1 /* SD16 2.Clock Divider Select /3 */ #define SD16XDIV_DIV4 SD16XDIV_2 /* SD16 2.Clock Divider Select /16 */