X-Git-Url: https://oss.titaniummirror.com/gitweb/?a=blobdiff_plain;f=include%2Fmsp430%2Ftimera.h;fp=include%2Fmsp430%2Ftimera.h;h=f0c45ab67986837b084eb923492e09d3f392d4ec;hb=6f720ff00773571c2fa2d35e67bff68547617639;hp=258ecfe76d68d2fe1ae65ec3691783c4f5525d16;hpb=807b2dd5b7365eb87b482197af3b4a3f520c14f7;p=msp430-libc.git diff --git a/include/msp430/timera.h b/include/msp430/timera.h index 258ecfe..f0c45ab 100644 --- a/include/msp430/timera.h +++ b/include/msp430/timera.h @@ -1,5 +1,5 @@ -#if !defined(__msp430_headers_timera_h__) -#define __msp430_headers_timera_h__ +#if !defined(__MSP430_HEADERS_TIMERA_H__) +#define __MSP430_HEADERS_TIMERA_H__ /* timera.h * @@ -9,17 +9,179 @@ * (c) 2002 by M. P. Ashton * Originally based in part on work by Texas Instruments Inc. * - * $Id: timera.h,v 1.13 2006/04/19 20:09:52 cliechti Exp $ + * 2009-05-19 - modifications by S. Balling + * - added T0A5 + * - added T1A3 + * 2009-10-08 - modifications by J.M.Gross + * - added TIV defines for T0A5 and T1A3 (and TB7) + * - changed T0A5 and T1A3 to use external base address + * + * $Id: timera.h,v 1.15 2009/06/04 21:55:18 cliechti Exp $ */ -/* Switches: +/* Switches: __MSP430_HAS_TA2__ - if the device has a timer0 A with 2 channels __MSP430_HAS_TA3__ - if the device has a timer0 A with 3 channels -__MSP430_HAS_T1A5__ - if the device has a timer1 A, as well as timer0 A +__MSP430_HAS_T1A2__ - if the device has a timer1 A with 2 channels, as well as timer0 A +__MSP430_HAS_T1A5__ - if the device has a timer1 A with 5 channels, as well as timer0 A +__MSP430_HAS_T0A5__ - if the device has a timer0 A with 5 channels +__MSP430_T0A_BASE__ - base address for timer 0 A (5) +__MSP430_HAS_T1A3__ - if the device has a timer1 A with 3 channels +__MSP430_T1A_BASE__ - base address for timer 1 A (3) */ +#if defined(__MSP430_HAS_T0A5__) +#define TA0CTL_ __MSP430_T0A_BASE__ + 0x00 // Timer A 0 Control +sfrw (TA0CTL,TA0CTL_); +#define TA0CTL_L_ __MSP430_T0A_BASE__ + 0x00 +sfrb (TA0CTL_L,TA0CTL_L_); +#define TA0CTL_H_ __MSP430_T0A_BASE__ + 0x01 +sfrb (TA0CTL_H,TA0CTL_H_); +#define TA0CCTL0_ __MSP430_T0A_BASE__ + 0x02 // Timer A 0 Capture/Compare Control 0 +sfrw (TA0CCTL0,TA0CCTL0_); +#define TA0CCTL0_L_ __MSP430_T0A_BASE__ + 0x02 +sfrb (TA0CCTL0_L,TA0CCTL0_L_); +#define TA0CCTL0_H_ __MSP430_T0A_BASE__ + 0x03 +sfrb (TA0CCTL0_H,TA0CCTL0_H_); +#define TA0CCTL1_ __MSP430_T0A_BASE__ + 0x04 // Timer A 0 Capture/Compare Control 1 +sfrw (TA0CCTL1,TA0CCTL1_); +#define TA0CCTL1_L_ __MSP430_T0A_BASE__ + 0x04 +sfrb (TA0CCTL1_L,TA0CCTL1_L_); +#define TA0CCTL1_H_ __MSP430_T0A_BASE__ + 0x05 +sfrb (TA0CCTL1_H,TA0CCTL1_H_); +#define TA0CCTL2_ __MSP430_T0A_BASE__ + 0x06 // Timer A 0 Capture/Compare Control 2 +sfrw (TA0CCTL2,TA0CCTL2_); +#define TA0CCTL2_L_ __MSP430_T0A_BASE__ + 0x06 +sfrb (TA0CCTL2_L,TA0CCTL2_L_); +#define TA0CCTL2_H_ __MSP430_T0A_BASE__ + 0x07 +sfrb (TA0CCTL2_H,TA0CCTL2_H_); +#define TA0CCTL3_ __MSP430_T0A_BASE__ + 0x08 // Timer A 0 Capture/Compare Control 3 +sfrw (TA0CCTL3,TA0CCTL3_); +#define TA0CCTL3_L_ __MSP430_T0A_BASE__ + 0x08 +sfrb (TA0CCTL3_L,TA0CCTL3_L_); +#define TA0CCTL3_H_ __MSP430_T0A_BASE__ + 0x09 +sfrb (TA0CCTL3_H,TA0CCTL3_H_); +#define TA0CCTL4_ __MSP430_T0A_BASE__ + 0x0A // Timer A 0 Capture/Compare Control 4 +sfrw (TA0CCTL4,TA0CCTL4_); +#define TA0CCTL4_L_ __MSP430_T0A_BASE__ + 0x0A +sfrb (TA0CCTL4_L,TA0CCTL4_L_); +#define TA0CCTL4_H_ __MSP430_T0A_BASE__ + 0x0B +sfrb (TA0CCTL4_H,TA0CCTL4_H_); +#define TA0R_ __MSP430_T0A_BASE__ + 0x10 // Timer A 0 +sfrw (TA0R,TA0R_); +#define TA0R_L_ __MSP430_T0A_BASE__ + 0x10 +sfrb (TA0R_L,TA0R_L_); +#define TA0R_H_ __MSP430_T0A_BASE__ + 0x11 +sfrb (TA0R_H,TA0R_H_); +#define TA0CCR0_ __MSP430_T0A_BASE__ + 0x12 // Timer A 0 Capture/Compare 0 +sfrw (TA0CCR0,TA0CCR0_); +#define TA0CCR0_L_ __MSP430_T0A_BASE__ + 0x12 +sfrb (TA0CCR0_L,TA0CCR0_L_); +#define TA0CCR0_H_ __MSP430_T0A_BASE__ + 0x13 +sfrb (TA0CCR0_H,TA0CCR0_H_); +#define TA0CCR1_ __MSP430_T0A_BASE__ + 0x14 // Timer A 0 Capture/Compare 1 +sfrw (TA0CCR1,TA0CCR1_); +#define TA0CCR1_L_ __MSP430_T0A_BASE__ + 0x14 +sfrb (TA0CCR1_L,TA0CCR1_L_); +#define TA0CCR1_H_ __MSP430_T0A_BASE__ + 0x15 +sfrb (TA0CCR1_H,TA0CCR1_H_); +#define TA0CCR2_ __MSP430_T0A_BASE__ + 0x16 // Timer A 0 Capture/Compare 2 +sfrw (TA0CCR2,TA0CCR2_); +#define TA0CCR2_L_ __MSP430_T0A_BASE__ + 0x16 +sfrb (TA0CCR2_L,TA0CCR2_L_); +#define TA0CCR2_H_ __MSP430_T0A_BASE__ + 0x17 +sfrb (TA0CCR2_H,TA0CCR2_H_); +#define TA0CCR3_ __MSP430_T0A_BASE__ + 0x18 // Timer A 0 Capture/Compare 3 +sfrw (TA0CCR3,TA0CCR3_); +#define TA0CCR3_L_ __MSP430_T0A_BASE__ + 0x18 +sfrb (TA0CCR3_L,TA0CCR3_L_); +#define TA0CCR3_H_ __MSP430_T0A_BASE__ + 0x19 +sfrb (TA0CCR3_H,TA0CCR3_H_); +#define TA0CCR4_ __MSP430_T0A_BASE__ + 0x1A // Timer A 0 Capture/Compare 4 +sfrw (TA0CCR4,TA0CCR4_); +#define TA0CCR4_L_ __MSP430_T0A_BASE__ + 0x1A +sfrb (TA0CCR4_L,TA0CCR4_L_); +#define TA0CCR4_H_ __MSP430_T0A_BASE__ + 0x1B +sfrb (TA0CCR4_H,TA0CCR4_H_); +#define TA0EX0_ __MSP430_T0A_BASE__ + 0x20 // Timer A 0 Expansion Register 0 +sfrw (TA0EX0,TA0EX0_); +#define TA0EX0_L_ __MSP430_T0A_BASE__ + 0x20 +sfrb (TA0EX0_L,TA0EX0_L_); +#define TA0EX0_H_ __MSP430_T0A_BASE__ + 0x21 +sfrb (TA0EX0_H,TA0EX0_H_); +#define TA0IV_ __MSP430_T0A_BASE__ + 0x2E // Timer A 0 Interrupt Vector Word +sfrw (TA0IV,TA0IV_); +#define TA0IV_L_ __MSP430_T0A_BASE__ + 0x2E +sfrb (TA0IV_L,TA0IV_L_); +#define TA0IV_H_ __MSP430_T0A_BASE__ + 0x2F +sfrb (TA0IV_H,TA0IV_H_); +#endif /* __MSP430_HAS_T0A5__ */ + +#if defined(__MSP430_HAS_T1A3__) +#define TA1CTL_ __MSP430_T1A_BASE__ + 0x00 // Timer A 1 Control +sfrw (TA1CTL,TA1CTL_); +#define TA1CTL_L_ __MSP430_T1A_BASE__ + 0x00 +sfrb (TA1CTL_L,TA1CTL_L_); +#define TA1CTL_H_ __MSP430_T1A_BASE__ + 0x01 +sfrb (TA1CTL_H,TA1CTL_H_); +#define TA1CCTL0_ __MSP430_T1A_BASE__ + 0x02 // Timer A 1 Capture/Compare Control 0 +sfrw (TA1CCTL0,TA1CCTL0_); +#define TA1CCTL0_L_ __MSP430_T1A_BASE__ + 0x02 +sfrb (TA1CCTL0_L,TA1CCTL0_L_); +#define TA1CCTL0_H_ __MSP430_T1A_BASE__ + 0x03 +sfrb (TA1CCTL0_H,TA1CCTL0_H_); +#define TA1CCTL1_ __MSP430_T1A_BASE__ + 0x04 // Timer A 1 Capture/Compare Control 1 +sfrw (TA1CCTL1,TA1CCTL1_); +#define TA1CCTL1_L_ __MSP430_T1A_BASE__ + 0x04 +sfrb (TA1CCTL1_L,TA1CCTL1_L_); +#define TA1CCTL1_H_ __MSP430_T1A_BASE__ + 0x05 +sfrb (TA1CCTL1_H,TA1CCTL1_H_); +#define TA1CCTL2_ __MSP430_T1A_BASE__ + 0x06 // Timer A 1 Capture/Compare Control 2 +sfrw (TA1CCTL2,TA1CCTL2_); +#define TA1CCTL2_L_ __MSP430_T1A_BASE__ + 0x06 +sfrb (TA1CCTL2_L,TA1CCTL2_L_); +#define TA1CCTL2_H_ __MSP430_T1A_BASE__ + 0x07 +sfrb (TA1CCTL2_H,TA1CCTL2_H_); +#define TA1R_ __MSP430_T1A_BASE__ + 0x10 // Timer A 1 +sfrw (TA1R,TA1R_); +#define TA1R_L_ __MSP430_T1A_BASE__ + 0x10 +sfrb (TA1R_L,TA1R_L_); +#define TA1R_H_ __MSP430_T1A_BASE__ + 0x11 +sfrb (TA1R_H,TA1R_H_); +#define TA1CCR0_ __MSP430_T1A_BASE__ + 0x12 // Timer A 1 Capture/Compare 0 +sfrw (TA1CCR0,TA1CCR0_); +#define TA1CCR0_L_ __MSP430_T1A_BASE__ + 0x12 +sfrb (TA1CCR0_L,TA1CCR0_L_); +#define TA1CCR0_H_ __MSP430_T1A_BASE__ + 0x13 +sfrb (TA1CCR0_H,TA1CCR0_H_); +#define TA1CCR1_ __MSP430_T1A_BASE__ + 0x14 // Timer A 1 Capture/Compare 1 +sfrw (TA1CCR1,TA1CCR1_); +#define TA1CCR1_L_ __MSP430_T1A_BASE__ + 0x14 +sfrb (TA1CCR1_L,TA1CCR1_L_); +#define TA1CCR1_H_ __MSP430_T1A_BASE__ + 0x15 +sfrb (TA1CCR1_H,TA1CCR1_H_); +#define TA1CCR2_ __MSP430_T1A_BASE__ + 0x16 // Timer A 1 Capture/Compare 2 +sfrw (TA1CCR2,TA1CCR2_); +#define TA1CCR2_L_ __MSP430_T1A_BASE__ + 0x16 +sfrb (TA1CCR2_L,TA1CCR2_L_); +#define TA1CCR2_H_ __MSP430_T1A_BASE__ + 0x17 +sfrb (TA1CCR2_H,TA1CCR2_H_); +#define TA1EX0_ __MSP430_T1A_BASE__ + 0x20 // Timer A 1 Expansion Register 0 +sfrw (TA1EX0,TA1EX0_); +#define TA1EX0_L_ __MSP430_T1A_BASE__ + 0x20 +sfrb (TA1EX0_L,TA1EX0_L_); +#define TA1EX0_H_ __MSP430_T1A_BASE__ + 0x21 +sfrb (TA1EX0_H,TA1EX0_H_); +#define TA1IV_ __MSP430_T1A_BASE__ + 0x2E // Timer A 1 Interrupt Vector Word +sfrw (TA1IV,TA1IV_); +#define TA1IV_L_ __MSP430_T1A_BASE__ + 0x2E +sfrb (TA1IV_L,TA1IV_L_); +#define TA1IV_H_ __MSP430_T1A_BASE__ + 0x2F +sfrb (TA1IV_H,TA1IV_H_); +#endif /* __MSP430_HAS_T1A3__ */ + #if defined(__MSP430_HAS_TA2__) || defined(__MSP430_HAS_TA3__) #define TA0IV_ 0x012E /* Timer A 0 Interrupt Vector Word */ sfrw (TA0IV,TA0IV_); @@ -63,7 +225,7 @@ sfrw (TA0CCR1,TA0CCR1_); #define CCR0_ TA0CCR0_ #define CCR1 TA0CCR1 #define CCR1_ TA0CCR1_ -#endif +#endif /* __MSP430_HAS_TA2__ || __MSP430_HAS_TA3__ */ #if defined(__MSP430_HAS_TA3__) #define TA0CCTL2_ 0x0166 /* Timer A 0 Capture/Compare Control 2 */ @@ -82,9 +244,9 @@ sfrw (TA0CCR2,TA0CCR2_); #define CCTL2_ TA0CCTL2_ #define CCR2 TA0CCR2 #define CCR2_ TA0CCR2_ -#endif +#endif /* __MSP430_HAS_TA3__ */ -#if defined(__MSP430_HAS_T1A5__) +#if defined(__MSP430_HAS_T1A2__) || defined(__MSP430_HAS_T1A5__) #define TA1IV_ 0x011E /* Timer A 1 Interrupt Vector Word */ sfrw (TA1IV, TA1IV_); #define TA1CTL_ 0x0180 /* Timer A 1 Control */ @@ -93,18 +255,21 @@ sfrw (TA1CTL, TA1CTL_); sfrw (TA1CCTL0, TA1CCTL0_); #define TA1CCTL1_ 0x0184 /* Timer A 1 Capture/Compare Control 1 */ sfrw (TA1CCTL1, TA1CCTL1_); +#if defined(__MSP430_HAS_T1A5__) #define TA1CCTL2_ 0x0186 /* Timer A 1 Capture/Compare Control 2 */ sfrw (TA1CCTL2, TA1CCTL2_); #define TA1CCTL3_ 0x0188 /* Timer A 1 Capture/Compare Control 3 */ sfrw (TA1CCTL3, TA1CCTL3_); #define TA1CCTL4_ 0x018A /* Timer A 1 Capture/Compare Control 4 */ sfrw (TA1CCTL4, TA1CCTL4_); +#endif #define TAR1_ 0x0190 /* Timer A 1 */ sfrw (TAR1, TAR1_); #define TA1CCR0_ 0x0192 /* Timer A 1 Capture/Compare 0 */ sfrw (TA1CCR0, TA1CCR0_); #define TA1CCR1_ 0x0194 /* Timer A 1 Capture/Compare 1 */ sfrw (TA1CCR1, TA1CCR1_); +#if defined(__MSP430_HAS_T1A5__) #define TA1CCR2_ 0x0196 /* Timer A 1 Capture/Compare 2 */ sfrw (TA1CCR2, TA1CCR2_); #define TA1CCR3_ 0x0198 /* Timer A 1 Capture/Compare 3 */ @@ -112,8 +277,9 @@ sfrw (TA1CCR3, TA1CCR3_); #define TA1CCR4_ 0x019A /* Timer A 1 Capture/Compare 4 */ sfrw (TA1CCR4, TA1CCR4_); #endif +#endif -#if !defined(_GNU_ASSEMBLER_) +#if !defined(__ASSEMBLER__) /* Structured declaration */ typedef struct { volatile unsigned @@ -142,40 +308,54 @@ typedef struct { cm:2; } __attribute__ ((packed)) tacctl_t; +#if defined(__MSP430_HAS_TA2__) || defined(__MSP430_HAS_TA3__) /* The timer A declaration itself */ struct timera_t { tactl_t ctl; tacctl_t cctl0; tacctl_t cctl1; +#if defined(__MSP430_HAS_TA3__) tacctl_t cctl2; - volatile unsigned dummy[4]; /* Pad to the next group of registers */ +#else + volatile unsigned dummy1[1]; /* Pad to the next group of registers */ +#endif + volatile unsigned dummy2[4]; /* Pad to the next group of registers */ volatile unsigned tar; volatile unsigned taccr0; volatile unsigned taccr1; +#if defined(__MSP430_HAS_TA3__) volatile unsigned taccr2; +#endif }; #ifdef __cplusplus extern "C" struct timera_t timera asm("0x0160"); #else //__cplusplus struct timera_t timera asm("0x0160"); #endif //__cplusplus +#endif // __MSP430_HAS_TA2__ || __MSP430_HAS_TA3__ -#if defined(__MSP430_HAS_T1A5__) +#if defined(__MSP430_HAS_T1A2__) || defined(__MSP430_HAS_T1A5__) /* The timer A1 declaration itself */ struct timera1_t { tactl_t ctl; tacctl_t cctl0; tacctl_t cctl1; +#if defined(__MSP430_HAS_T1A5__) tacctl_t cctl2; tacctl_t cctl3; tacctl_t cctl4; - volatile unsigned dummy[2]; /* Pad to the next group of registers */ +#else + volatile unsigned dummy1[3]; /* Pad to the next group of registers */ +#endif + volatile unsigned dummy2[2]; /* Pad to the next group of registers */ volatile unsigned tar; volatile unsigned taccr0; volatile unsigned taccr1; +#if defined(__MSP430_HAS_T1A5__) volatile unsigned taccr2; volatile unsigned taccr3; volatile unsigned taccr4; +#endif }; #ifdef __cplusplus extern "C" struct timera1_t timera1 asm("0x0180"); @@ -198,17 +378,25 @@ struct timera1_t timera1 asm("0x0180"); #define TAIFG 0x0001 /* Timer A counter interrupt flag */ #define MC_0 (0<<4) /* Timer A mode control: 0 - Stop */ +#define MC__STOP MC_0 #define MC_1 (1<<4) /* Timer A mode control: 1 - Up to CCR0 */ +#define MC__UP MC_1 #define MC_2 (2<<4) /* Timer A mode control: 2 - Continous up */ +#define MC__CONTINOUS MC_2 /* (sic) */ #define MC_3 (3<<4) /* Timer A mode control: 3 - Up/Down */ +#define MC__UPDOWN MC_3 #define ID_0 (0<<6) /* Timer A input divider: 0 - /1 */ #define ID_1 (1<<6) /* Timer A input divider: 1 - /2 */ #define ID_2 (2<<6) /* Timer A input divider: 2 - /4 */ #define ID_3 (3<<6) /* Timer A input divider: 3 - /8 */ #define TASSEL_0 (0<<8) /* Timer A clock source select: 0 - TACLK */ +#define TASSEL__TACLK TASSEL_0 #define TASSEL_1 (1<<8) /* Timer A clock source select: 1 - ACLK */ +#define TASSEL__ACLK TASSEL_1 #define TASSEL_2 (2<<8) /* Timer A clock source select: 2 - SMCLK */ +#define TASSEL__SMCLK TASSEL_2 #define TASSEL_3 (3<<8) /* Timer A clock source select: 3 - INCLK */ +#define TASSEL__INCLK TASSEL_3 #define CM1 0x8000 /* Capture mode 1 */ #define CM0 0x4000 /* Capture mode 0 */ @@ -273,6 +461,12 @@ struct timera1_t timera1 asm("0x0180"); #define CM_NEG CM_2 #define CM_BOTH CM_3 +#define CCIS_CCIA CCIS_0 +#define CCIS_CCIB CCIS_1 +#define CCIS_GND CCIS_2 +#define CCIS_VCC CCIS_3 + + /* TimerA IV names */ #if defined(__MSP430_HAS_TA3__) || defined(__MSP430_HAS_TA2____) #define TAIV_NONE 0x00 /* No interrupt pending */ @@ -283,4 +477,17 @@ struct timera1_t timera1 asm("0x0180"); #define TAIV_OVERFLOW 0x0A /* Timer overflow TAIFG Lowest */ #endif /*__MSP430_HAS_TA3__ || __MSP430_HAS_TA2__*/ +/* on newer devices, TIMERA0, TIMERA1 and TIMERB have identical TIV registers */ +#if defined(__MSP430_HAS_T0A5__) || defined(__MSP430_HAS_T1A3__) || !defined(TIV_NONE) /* in case already defined for new TIMERB(7) */ + #define TIV_NONE 0x00 /* No interrupt pending */ + #define TIV_CCR1 0x02 /* Capture/compare 1 TACCR1 CCIFG Highest */ + #define TIV_CCR2 0x04 /* Capture/compare 2 TACCR2 CCIFG */ + #define TIV_CCR3 0x06 /* Capture/compare 2 TACCR2 CCIFG */ + #define TIV_CCR4 0x08 /* Capture/compare 2 TACCR2 CCIFG */ + #define TIV_CCR5 0x0A /* Capture/compare 2 TACCR2 CCIFG */ + #define TIV_CCR6 0x0C /* Capture/compare 2 TACCR2 CCIFG */ + #define TIV_OVERFLOW 0x0E /* Timer overflow TAIFG Lowest */ #endif + + +#endif /*__MSP430_HEADERS_TIMERA_H__*/