X-Git-Url: https://oss.titaniummirror.com/gitweb/?a=blobdiff_plain;f=src%2Fgcrt0.S;h=c7c9acbd81c0c5e32e1522522ca5e2d3acf73e45;hb=6f720ff00773571c2fa2d35e67bff68547617639;hp=2d1dd9b358bf1158d1bd68cb37207a7c493ee6f1;hpb=807b2dd5b7365eb87b482197af3b4a3f520c14f7;p=msp430-libc.git

diff --git a/src/gcrt0.S b/src/gcrt0.S
index 2d1dd9b..c7c9acb 100644
--- a/src/gcrt0.S
+++ b/src/gcrt0.S
@@ -22,39 +22,115 @@ General Public License for more details.  */
 
 ;; -*- mode: asm -*-
 
+
 #include <io.h>
+#include "core_common.inc"
+/***************************************************************
+ *	Declare registers used in library routines
+ ***************************************************************/
+.macro  MAKE_WEAK   name
+        .weak   __\name
+        .set    __\name, \name
+.endm
+        MAKE_WEAK   WDTCTL
+#if defined (__MSP430_HAS_HW_MUL__)
+        MAKE_WEAK   MPY
+        MAKE_WEAK   MPYS
+        MAKE_WEAK   MAC
+        MAKE_WEAK   MACS
+        MAKE_WEAK   OP2
+        MAKE_WEAK   RESLO
+        MAKE_WEAK   RESHI
+        MAKE_WEAK   SUMEXT
+#if defined (__MSP430_HAS_HW_MUL32__)
+        MAKE_WEAK   MPY32L
+        MAKE_WEAK   MPY32H
+        MAKE_WEAK   MPYS32L
+        MAKE_WEAK   MPYS32H
+        MAKE_WEAK   MAC32L
+        MAKE_WEAK   MAC32H
+        MAKE_WEAK   MACS32L
+        MAKE_WEAK   MACS32H
+        MAKE_WEAK   OP2L
+        MAKE_WEAK   OP2H
+        MAKE_WEAK   RES0
+        MAKE_WEAK   RES1
+        MAKE_WEAK   RES2
+        MAKE_WEAK   RES3
+        MAKE_WEAK   MPY32CTL0
+#endif
+#endif
+	
+/***************************************************************
+ *	Include routines that reference chip-specific values
+ ***************************************************************/
+#include "stdlib/__low_level_init.S"
 
 /***************************************************************
  *	Interrupt Vectors:
  *	WARNING!!! All vectors must be defined here!!!
  *	User may not define its interrupt service routines!
  ***************************************************************/
-
-        .weak _unexpected_
-	.global _unexpected_1_
-	
-	.text
+        .text
         .p2align 1,0
+_branch_to_unexpected_:
+        XBR     #_unexpected_
 
-_unexpected_1_:
-	br	#_unexpected_
-_unexpected_:
-        reti
-
-.section .vectors, "ax", @progbits
+        .section .vectors, "ax", @progbits
 
 .macro  VEC name
-	.weak   \name
-        .set    \name, _unexpected_1_
+        .weak   \name
+        .equ    \name, _branch_to_unexpected_
         .word   \name
 .endm
 
 .global InterruptVectors
         .type   InterruptVectors, @object
 
-#if defined(__MSP430X__)
-	.size InterruptVectors, 0x40
+#if defined(__MSP430X2__)
+        .size InterruptVectors, 0x80
+#elif defined(__MSP430X__)
+        .size InterruptVectors, 0x40
+#else
+        .size InterruptVectors, 0x20
+#endif
+
 InterruptVectors:
+#if defined(__MSP430X2__)
+/* 80 */	VEC vector_ff80
+/* 82 */	VEC vector_ff82
+/* 84 */	VEC vector_ff84
+/* 86 */	VEC vector_ff86
+/* 88 */	VEC vector_ff88
+/* 8a */	VEC vector_ff8a
+/* 8c */	VEC vector_ff8c
+/* 8e */	VEC vector_ff8e
+/* 90 */	VEC vector_ff90
+/* 92 */	VEC vector_ff92
+/* 94 */	VEC vector_ff94
+/* 96 */	VEC vector_ff96
+/* 98 */	VEC vector_ff98
+/* 9a */	VEC vector_ff9a
+/* 9c */	VEC vector_ff9c
+/* 9e */	VEC vector_ff9e
+/* a0 */	VEC vector_ffa0
+/* a2 */	VEC vector_ffa2
+/* a4 */	VEC vector_ffa4
+/* a6 */	VEC vector_ffa6
+/* a8 */	VEC vector_ffa8
+/* aa */	VEC vector_ffaa
+/* ac */	VEC vector_ffac
+/* ae */	VEC vector_ffae
+/* b0 */	VEC vector_ffb0
+/* b2 */	VEC vector_ffb2
+/* b4 */	VEC vector_ffb4
+/* b6 */	VEC vector_ffb6
+/* b8 */	VEC vector_ffb8
+/* ba */	VEC vector_ffba
+/* bc */	VEC vector_ffbc
+/* be */	VEC vector_ffbe
+#endif
+#if defined(__MSP430X__) || defined(__MSP430X2__)
 /* c0 */	VEC vector_ffc0
 /* c2 */	VEC vector_ffc2
 /* c4 */	VEC vector_ffc4
@@ -71,9 +147,6 @@ InterruptVectors:
 /* da */	VEC vector_ffda
 /* dc */	VEC vector_ffdc
 /* de */	VEC vector_ffde
-#else
-	.size InterruptVectors, 0x20
-InterruptVectors:
 #endif
 /* e0 */	VEC vector_ffe0
 /* e2 */	VEC vector_ffe2
@@ -90,6 +163,6 @@ InterruptVectors:
 /* f8 */	VEC vector_fff8
 /* fa */	VEC vector_fffa
 /* fc */	VEC vector_fffc
-		.word _reset_vector__
+        .word _reset_vector__
 
 /* end of Interrupt vectors declarations */