X-Git-Url: https://oss.titaniummirror.com/gitweb/?a=blobdiff_plain;f=tos%2Fchips%2Fmsp430%2Fadc12%2FMsp430Adc12.h;fp=tos%2Fchips%2Fmsp430%2Fadc12%2FMsp430Adc12.h;h=90952a0c2594b0ed06190466660e11d2b8299e98;hb=1a329382c4f4556fd52d85f4e3f4a67e54911682;hp=a8f9aa6712f9bb08c7b17ed7ed33a3b5d278bfb5;hpb=3837fe262225242d1629ba72bdf12f6d162ba5c0;p=tinyos-2.x.git diff --git a/tos/chips/msp430/adc12/Msp430Adc12.h b/tos/chips/msp430/adc12/Msp430Adc12.h index a8f9aa67..90952a0c 100644 --- a/tos/chips/msp430/adc12/Msp430Adc12.h +++ b/tos/chips/msp430/adc12/Msp430Adc12.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2004, Technische Universitaet Berlin + * Copyright (c) 2006, Technische Universitaet Berlin * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -42,79 +42,84 @@ #define CHECK_ARGS /* - * The msp430adc12_channel_config_t encapsulates all relevant flags for - * sampling a single ADC12 channel on a per-client basis. They are taken from - * the following MSP430 registers: ADC12CTL0, ADC12CTL1, ADC12MCTLx and TACTL - * of TimerA (if applicable) and named according to section "17.3 ADC12 - * Registers" of the "MSP430x1xx Family User's Guide", - * http://focus.ti.com/lit/ug/slau049e/slau049e.pdf). - * - * .inch: ADC12 input channel (ADC12MCTLx register). An (external) input channel - * maps to one of msp430's A0-A7 pins (see device specific data sheet). + * The msp430adc12_channel_config_t includes all relevant flags to configure + * the ADC12 for single channel conversions. They are contained in the following + * MSP430 registers: ADC12CTL0, ADC12CTL1, ADC12MCTLx and TACTL of TimerA (if + * applicable) and named according to section "17.3 ADC12 Registers" of the + * "MSP430x1xx Family User's Guide". + * + * ********************************** + * + * .inch: ADC12 input channel (ADC12MCTLx register). An (external) input + * channel maps to one of msp430's A0-A7 pins (see device specific data sheet). * - * .sref: reference voltage (ADC12MCTLx register). If - * REFERENCE_VREFplus_AVss or REFERENCE_VREFplus_VREFnegterm is chosen - * AND the client wires to Msp430Adc12RefVoltAutoClientC (or - * REF_VOLT_AUTO_CONFIGURE is defined and the client wires to - * AdcReadClientC, AdcReadNowClientC or AdcReadStreamClientC) then the - * reference voltage generator is automatically switched on to the - * voltage level defined by the "ref2_5v" flag (see below) whenever the - * client accesses the ADC12. Otherwise both flags are ignored. + * .sref: reference voltage (ADC12MCTLx register). If REFERENCE_VREFplus_AVss + * or REFERENCE_VREFplus_VREFnegterm is chosen AND the client wires to the + * Msp430Adc12ClientAutoRVGC or Msp430Adc12ClientAutoDMA_RVGC component then + * the reference voltage generator has automatically been enabled to the + * voltage level defined by the "ref2_5v" flag (see below) when the + * Resource.granted() event is signalled to the client. Otherwise this flag is + * ignored. * - * .ref2_5v: Reference generator voltage level (ADC12CTL0 register). See - * explanation to "sref" flag. + * .ref2_5v: Reference generator voltage level (ADC12CTL0 register). See "sref" + * flag. * - * .adc12ssel: ADC12 clock source select for the sample-hold-time - * (ADC12CTL1 register). In combination the "adc12ssel", "adc12div" and - * "sht" define the sample-hold-time: "adc12ssel" defines the clock - * source, "adc12div" defines the ADC12 clock divider and "sht" define - * the time expressed in jiffies. + * .adc12ssel: ADC12 clock source select for the sample-hold-time (ADC12CTL1 + * register). In combination the "adc12ssel", "adc12div" and "sht" define the + * sample-hold-time: "adc12ssel" defines the clock source, "adc12div" defines + * the ADC12 clock divider and "sht" define the time expressed in jiffies. + * (the sample-hold-time depends on the resistence of the attached sensor, and + * is calculated using to the formula in section 17.2.4 of the user guide) * * .adc12div: ADC12 clock divider (ADC12CTL1 register). See "adc12ssel". * * .sht: Sample-and-hold time (ADC12CTL1 register). See "adc12ssel". * - * .sampcon_ssel: In combination with "sampcon_id" and the "jiffies" - * parameter in the Msp430Adc12SingleChannel interface commands the - * "sampcon_ssel" defines the sampling rate (TASSEL in TACTL register, - * TimerA). It is the clock source for the SAMPCON signal, which - * triggers the actual sampling. It is ignored when - * Msp430Adc12SingleChannel.getSingleData() is used or the "jiffies" - * parameter is zero; otherwise the SAMPCON signal is sourced from - * TimerA, so that the multiple conversion mode can be made with the - * user defined sampling rate. + * .sampcon_ssel: Clock source for the sampling period (TASSEL for TimerA). + * When an ADC client specifies a non-zero "jiffies" parameter (passed in the + * relevant Msp430Adc12SingleChannel interface commands), the ADC + * implementation will automatically configure TimerA to be sourced from + * "sampcon_ssel" with an input divider of "sampcon_id". During the sampling + * process TimerA will then be used to trigger a conversion every "jiffies" + * clock ticks. * - * .sampcon_id: Input divider for "sampcon_ssel" (IDx in TACTL - * register, TimerA). See "sampcon_ssel". + * .sampcon_id: Input divider for "sampcon_ssel" (IDx in TACTL register, + * TimerA). See "sampcon_ssel". * * * ********************************** * - * EXAMPLE: Assuming that SMCLK runs at 1 MHz the following command fills the - * user buffer with 2000 conversion results sampled on channel A2 with a - * sampling rate of 4000 Hz, i.e. the multipleDataReady() event is signalled - * after 500 ms. Note that the sampling rate is defined by the combination of - * SAMPCON_SOURCE_SMCLK, SAMPCON_CLOCK_DIV_1 and the "jiffies" parameter of - * 250. - * - * - * uint16_t buffer[2000]; - * msp430adc12_channel_config_t config = { - * INPUT_CHANNEL_A2, REFERENCE_VREFplus_AVss, REFVOLT_LEVEL_1_5, - * SHT_SOURCE_SMCLK, SHT_CLOCK_DIV_1, SAMPLE_HOLD_64_CYCLES, - * SAMPCON_SOURCE_SMCLK, SAMPCON_CLOCK_DIV_1 - * }; - * - * event void Resource.granted() - * { - * if (call SingleChannel.getMultipleData(&config, buffer, 2000, 250) - * == SUCCESS) - * { - * // .. multipleDataReady() event will be signalled in 500ms - * } else { - * // check error - * } - * } + * EXAMPLE: Assuming that SMCLK runs at 1 MHz the following code snippet + * performs 2000 ADC conversions on channel A2 with a sampling period of 4000 Hz. + * The sampling period is defined by the combination of SAMPCON_SOURCE_SMCLK, + * SAMPCON_CLOCK_DIV_1 and a "jiffies" parameter of (1000000 / 4000) = 250. + + #define NUM_SAMPLES 2000 + uint16_t buffer[NUM_SAMPLES]; + + msp430adc12_channel_config_t config = { + INPUT_CHANNEL_A2, REFERENCE_VREFplus_AVss, REFVOLT_LEVEL_NONE, + SHT_SOURCE_SMCLK, SHT_CLOCK_DIV_1, SAMPLE_HOLD_64_CYCLES, + SAMPCON_SOURCE_SMCLK, SAMPCON_CLOCK_DIV_1 + }; + + event void Boot.booted() + { + call Resource.request(); + } + + event void Resource.granted() + { + error_t result; + result = call SingleChannel.configureMultiple(&config, buffer, BUFFER_SIZE, 250); + if (result == SUCCESS) + call SingleChannel.getData(); + } + + async event uint16_t* SingleChannel.multipleDataReady(uint16_t *buf, uint16_t length) + { + // buffer contains conversion results + } */ @@ -227,7 +232,6 @@ enum sampcon_id_enum // The unique string for accessing HAL2 via ReadStream #define ADCC_READ_STREAM_SERVICE "AdcC.ReadStream.Client" - typedef struct { volatile unsigned