X-Git-Url: https://oss.titaniummirror.com/gitweb/?a=blobdiff_plain;f=tos%2Fchips%2Fmsp430%2Fusart%2FMsp430SpiNoDmaP.nc;h=57102aaf7d0dccd839aa3ea623c0ff2aefca9152;hb=337d0b13acf569c2640b3ed7b7f5c7cec35d7ddd;hp=fcb277700ec6876d098ac050b75b1750e03bcd16;hpb=1a329382c4f4556fd52d85f4e3f4a67e54911682;p=tinyos-2.x.git diff --git a/tos/chips/msp430/usart/Msp430SpiNoDmaP.nc b/tos/chips/msp430/usart/Msp430SpiNoDmaP.nc index fcb27770..57102aaf 100644 --- a/tos/chips/msp430/usart/Msp430SpiNoDmaP.nc +++ b/tos/chips/msp430/usart/Msp430SpiNoDmaP.nc @@ -86,7 +86,9 @@ implementation { } async command void ResourceConfigure.unconfigure[ uint8_t id ]() { + call Usart.resetUsart(TRUE); call Usart.disableSpi(); + call Usart.resetUsart(FALSE); } event void UsartResource.granted[ uint8_t id ]() { @@ -95,11 +97,13 @@ implementation { async command uint8_t SpiByte.write( uint8_t tx ) { uint8_t byte; - call Usart.disableRxIntr(); + // we are in spi mode which is configured to have turned off interrupts + //call Usart.disableRxIntr(); call Usart.tx( tx ); while( !call Usart.isRxIntrPending() ); + call Usart.clrRxIntr(); byte = call Usart.rx(); - call Usart.enableRxIntr(); + //call Usart.enableRxIntr(); return byte; } @@ -107,7 +111,7 @@ implementation { default async command error_t UsartResource.request[ uint8_t id ]() { return FAIL; } default async command error_t UsartResource.immediateRequest[ uint8_t id ]() { return FAIL; } default async command error_t UsartResource.release[ uint8_t id ]() { return FAIL; } - default async command msp430_spi_config_t* Msp430SpiConfigure.getConfig[uint8_t id]() { + default async command msp430_spi_union_config_t* Msp430SpiConfigure.getConfig[uint8_t id]() { return &msp430_spi_default_config; } @@ -127,8 +131,10 @@ implementation { while ( ++m_pos < end ) { while( !call Usart.isTxIntrPending() ); + call Usart.clrTxIntr(); call Usart.tx( m_tx_buf ? m_tx_buf[ m_pos ] : 0 ); while( !call Usart.isRxIntrPending() ); + call Usart.clrRxIntr(); tmp = call Usart.rx(); if ( m_rx_buf ) m_rx_buf[ m_pos - 1 ] = tmp;