X-Git-Url: https://oss.titaniummirror.com/gitweb/?a=blobdiff_plain;f=tos%2Fchips%2Fmsp430%2Fusci%2FHplMsp430UsciC.nc;h=f8f84a9e49c0c151f466a050a69af0b6b6b34caf;hb=9b58ecb229fe2466638908e2e3c28f66f0439116;hp=c6ac8b24006cd2b37c58159bd34fabaedbbceaf8;hpb=eaf09b7f1f9b7501d842707cc3d290cdd8d3bb98;p=tinyos-2.x.git

diff --git a/tos/chips/msp430/usci/HplMsp430UsciC.nc b/tos/chips/msp430/usci/HplMsp430UsciC.nc
index c6ac8b24..f8f84a9e 100644
--- a/tos/chips/msp430/usci/HplMsp430UsciC.nc
+++ b/tos/chips/msp430/usci/HplMsp430UsciC.nc
@@ -47,7 +47,7 @@
  
 configuration HplMsp430UsciC {
   provides {
-#if defined(__MSP430_HAS_USCIAB0__) || defined(__MSP430_HAS_USCI__)
+#if defined(__MSP430_HAS_USCI_AB0__) || defined(__MSP430_HAS_USCI__)
     interface HplMsp430UsciReg as RegA0;
     interface HplMsp430UsciInt as IntA0;
     interface HplMsp430UsciReg as RegB0;
@@ -62,11 +62,12 @@ configuration HplMsp430UsciC {
   }
 }
 implementation {
-#if defined(__MSP430_HAS_USCI__)
+#if defined(__MSP430_HAS_USCI_AB0__)
   components new HplMsp430UsciRegP(UCA0CTL0_, UCA0CTL1_, UCA0BR0_, UCA0BR1_,
     UCA0MCTL_, 0/*UCA0I2CIE_*/, UCA0STAT_, UCA0RXBUF_, UCA0TXBUF_, UCA0ABCTL_,
     UCA0IRTCTL_, UCA0IRRCTL_, 0/*UCA0I2COA_*/, 0/*UCA0I2CSA_*/, IE2_, IFG2_,
-    UCA0RXIFG, UCA0TXIFG) as RegA0P;
+    UCA0RXIFG, UCA0TXIFG)
+    as RegA0P;
   RegA0 = RegA0P.Reg;
 
   components new HplMsp430UsciRegP(UCB0CTL0_, UCB0CTL1_, UCB0BR0_, UCB0BR1_,
@@ -75,19 +76,16 @@ implementation {
     UCB0I2CSA_, IE2_, IFG2_, UCB0RXIFG, UCB0TXIFG) as RegB0P;
   RegB0 = RegB0P.Reg;
 
-  components new HplMsp430UsciIntP(USCIRX_VECTOR, USCITX_VECTOR, UCA0RXIFG,
-    UCA0TXIFG, UCB0RXIFG, UCB0TXIFG, UCA0CTL0_, UCA0CTL1_, UCA0RXBUF_,
-    UCB0CTL0_, UCB0CTL1_, UCB0RXBUF_, IFG2_) as Int0P;
+  components new HplMsp430UsciIntP(USCIAB0RX_VECTOR, USCIAB0TX_VECTOR,
+    UCA0RXIFG, UCA0TXIFG, UCB0RXIFG, UCB0TXIFG, UCA0CTL0_, UCA0CTL1_,
+    UCA0RXBUF_, UCB0CTL0_, UCB0CTL1_, UCB0RXBUF_, IFG2_) as Int0P;
   IntA0 = Int0P.IntA;
   IntB0 = Int0P.IntB;
-
-#elif defined(__MSP430_HAS_USCIAB0__)
-
+#elif defined(__MSP430_HAS_USCI__)
   components new HplMsp430UsciRegP(UCA0CTL0_, UCA0CTL1_, UCA0BR0_, UCA0BR1_,
     UCA0MCTL_, 0/*UCA0I2CIE_*/, UCA0STAT_, UCA0RXBUF_, UCA0TXBUF_, UCA0ABCTL_,
     UCA0IRTCTL_, UCA0IRRCTL_, 0/*UCA0I2COA_*/, 0/*UCA0I2CSA_*/, IE2_, IFG2_,
-    UCA0RXIFG, UCA0TXIFG)
-    as RegA0P;
+    UCA0RXIFG, UCA0TXIFG) as RegA0P;
   RegA0 = RegA0P.Reg;
 
   components new HplMsp430UsciRegP(UCB0CTL0_, UCB0CTL1_, UCB0BR0_, UCB0BR1_,
@@ -96,14 +94,14 @@ implementation {
     UCB0I2CSA_, IE2_, IFG2_, UCB0RXIFG, UCB0TXIFG) as RegB0P;
   RegB0 = RegB0P.Reg;
 
-  components new HplMsp430UsciIntP(USCIAB0RX_VECTOR, USCIAB0TX_VECTOR,
-    UCA0RXIFG, UCA0TXIFG, UCB0RXIFG, UCB0TXIFG, UCA0CTL0_, UCA0CTL1_,
-    UCA0RXBUF_, UCB0CTL0_, UCB0CTL1_, UCB0RXBUF_, IFG2_) as Int0P;
+  components new HplMsp430UsciIntP(USCIRX_VECTOR, USCITX_VECTOR, UCA0RXIFG,
+    UCA0TXIFG, UCB0RXIFG, UCB0TXIFG, UCA0CTL0_, UCA0CTL1_, UCA0RXBUF_,
+    UCB0CTL0_, UCB0CTL1_, UCB0RXBUF_, IFG2_) as Int0P;
   IntA0 = Int0P.IntA;
   IntB0 = Int0P.IntB;
 #endif
 
-#if defined(__MSP430_HAS_USCIAB1__)
+#if defined(__MSP430_HAS_USCI_AB1__)
   components new HplMsp430UsciRegP(UCA1CTL0_, UCA1CTL1_, UCA1BR0_, UCA1BR1_,
     UCA1MCTL_, 0/*UCA1I2CIE_*/, UCA1STAT_, UCA1RXBUF_, UCA1TXBUF_, UCA1ABCTL_,
     UCA1IRTCTL_, UCA1IRRCTL_, 0/*UCA1I2COA_*/, 0/*UCA1I2CSA_*/, IE2_, IFG2_,
@@ -122,4 +120,5 @@ implementation {
   IntA1 = Int1P.IntA;
   IntB1 = Int1P.IntB;
 #endif
+#endif
 }