X-Git-Url: https://oss.titaniummirror.com/gitweb/?a=blobdiff_plain;f=tos%2Fchips%2Fmsp430%2Fusci%2FHplMsp430UsciInt0P.nc;h=9d75d9d9f940bebe5f3d90f27856e1cc760a2253;hb=a04046a3331f1baba1e6a568613fec5db58bbe7b;hp=1ba7ef20668adcf4ec1fd65226b53db1a970fc53;hpb=c4a3d36739346681572c7eda2a6243a8634474db;p=tinyos-2.x.git

diff --git a/tos/chips/msp430/usci/HplMsp430UsciInt0P.nc b/tos/chips/msp430/usci/HplMsp430UsciInt0P.nc
index 1ba7ef20..9d75d9d9 100644
--- a/tos/chips/msp430/usci/HplMsp430UsciInt0P.nc
+++ b/tos/chips/msp430/usci/HplMsp430UsciInt0P.nc
@@ -26,13 +26,13 @@
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
  * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
- 
+
 /**
  * HPL interrupt interface for the USCI0 peripheral.
- * 
+ *
  * @author R. Steve McKown <rsmckown@gmail.com>
  */
- 
+
 #include "Msp430Usci.h"
 #include "msp430hardware.h"
 
@@ -67,37 +67,50 @@ implementation
    * modes.
    */
   TOSH_SIGNAL(USCIAB0RX_VECTOR) {
-    if (READ_FLAG(UC0IFG, UCA0RXIFG)) {
+    if (READ_FLAG(UC0IFG & UC0IE, UCA0RXIE)) {
       volatile uint8_t c = UCA0RXBUF; /* read to clear UCA0RXIFG */
       if (READ_FLAG(UCA0CTL1, UCBRK)) {
-	UCA0CTL1 &= ~UCBRK;
+	CLR_FLAG(UCA0CTL1, UCBRK);
 	if (READ_FLAG(UCA0CTL0, UCMODE_3) == UCMODE_3)
-	  UCA0CTL1 &= ~UCDORM;
+	  CLR_FLAG(UCA0CTL1, UCDORM);
 	signal IntA.brk();
       } else
 	signal IntA.rx(c);
-    } else if (READ_FLAG(UC0IFG, UCB0RXIFG))
+    } else if (READ_FLAG(UC0IFG & UC0IE, UCB0RXIE)) {
       signal IntB.rx(UCB0RXBUF); /* read clears UCB0RXIFG */
-    else if (READ_FLAG(UCB0STAT, UCALIFG))
+
+    /* FIXME: the arbitration of I2C interrupts are not vetted.  If, for example
+     * the UCALIFG bit gets set and neither it nor the corresponding interrupt
+     * enable bit is never unset, then an ISR configured for UCSTTIFG or
+     * UCSTPIFG will never be signalled.
+     */
+
+    } else if (READ_FLAG(UCB0STAT, UCALIFG)) {
+      CLR_FLAG(UCB0STAT, UCALIFG);
       signal IntB.i2cCal();
-    else if (READ_FLAG(UCB0STAT, UCNACKIFG))
-      signal IntB.i2cNak();
-    else if (READ_FLAG(UCB0STAT, UCSTTIFG))
+    } else if (READ_FLAG(UCB0STAT, UCNACKIFG)) {
+      CLR_FLAG(UCB0STAT, UCNACKIFG);
+      CLR_FLAG(UC0IFG, UCB0TXIFG); /* Errata USCI25; 'reset' means clear? */
+      signal IntB.i2cNack();
+    } else if (READ_FLAG(UCB0STAT, UCSTTIFG)) {
+      CLR_FLAG(UCB0STAT, UCSTTIFG);
       signal IntB.i2cStart();
-    else if (READ_FLAG(UCB0STAT, UCSTPIFG))
+    } else if (READ_FLAG(UCB0STAT, UCSTPIFG)) {
+      CLR_FLAG(UCB0STAT, UCSTPIFG);
       signal IntB.i2cStop();
+    }
   }
-  
+
   /* This interrupt vector signals transmit events.  USCI_A0 can receive events
    * for UART and SPI modes, while USCI_B0 can receive events for I2C and SPI
    * modes.
    */
   TOSH_SIGNAL(USCIAB0TX_VECTOR) {
-    if (READ_FLAG(UC0IFG, UCB0RXIFG))
+    if (READ_FLAG(UC0IFG & UC0IE, UCB0RXIE))
       signal IntB.rx(UCB0RXBUF); /* I2C receive */
-    else if (READ_FLAG(UC0IFG, UCA0TXIFG))
+    else if (READ_FLAG(UC0IFG & UC0IE, UCA0TXIFG))
       signal IntA.tx();
-    else if (READ_FLAG(UC0IFG, UCB0TXIFG))
+    else if (READ_FLAG(UC0IFG & UC0IE, UCB0TXIFG))
       signal IntB.tx();
   }
 
@@ -106,7 +119,7 @@ implementation
   default async event void IntA.tx() {}
   /* i2c is not available for A devices, so the below are never signalled */
   default async event void IntA.i2cCal() {}
-  default async event void IntA.i2cNak() {}
+  default async event void IntA.i2cNack() {}
   default async event void IntA.i2cStart() {}
   default async event void IntA.i2cStop() {}
 
@@ -115,7 +128,7 @@ implementation
   default async event void IntB.rx(uint8_t byte) {}
   default async event void IntB.tx() {}
   default async event void IntB.i2cCal() {}
-  default async event void IntB.i2cNak() {}
+  default async event void IntB.i2cNack() {}
   default async event void IntB.i2cStart() {}
   default async event void IntB.i2cStop() {}
 }