X-Git-Url: https://oss.titaniummirror.com/gitweb/?a=blobdiff_plain;f=tos%2Fchips%2Fmsp430%2Fusci%2FMsp430SpiP.nc;h=22bfbbd376b1aa00237b8539a94b7ab402ea7a4f;hb=753d22d3f0f9764e9a4cdfbefdcf45ff9db4c3cc;hp=dad8e824bd420bf37f8f2c511e83ae57d603714a;hpb=e40462f2112327c1cc2ce8be8c0f497cc4ddbeba;p=tinyos-2.x.git

diff --git a/tos/chips/msp430/usci/Msp430SpiP.nc b/tos/chips/msp430/usci/Msp430SpiP.nc
index dad8e824..22bfbbd3 100644
--- a/tos/chips/msp430/usci/Msp430SpiP.nc
+++ b/tos/chips/msp430/usci/Msp430SpiP.nc
@@ -28,7 +28,9 @@
  */
  
 /**
- * Spi implementation using a USCI device.
+ * Spi implementation using a USCI device.  When being used as a SPI slave, the
+ * CSn interface should be wired to the chip select driven by the SPI master so
+ * the module can know when a communications session is terminated unexpectedly.
  *
  * TODO: Implement error checking via UCxxSTAT
  *
@@ -46,6 +48,7 @@ generic module Msp430SpiP(uint16_t blockSize) {
   uses {
     interface HplMsp430UsciReg as Registers;
     interface HplMsp430UsciInt as Interrupts;
+    interface GeneralIO as CSn;
     interface HplMsp430GeneralIO as STE;
     interface HplMsp430GeneralIO as SIMO;
     interface HplMsp430GeneralIO as SOMI;
@@ -69,17 +72,17 @@ implementation {
   };
 
   uint8_t m_pins;
-  uint8_t* m_txBuf;
-  uint8_t* m_rxBuf;
-  uint16_t m_len;
-  uint16_t m_pos;
+  norace uint8_t* m_txBuf;
+  norace uint8_t* m_rxBuf;
+  norace uint16_t m_len;
+  norace uint16_t m_pos;
 
-  inline bool is4pin() /* true if the SPI bus is in 4-pin mode */
+  inline bool is4pin() /* TRUE if the SPI bus is in 4-pin mode */
   {
     return (call Registers.getCtl0(UCMODE_3)) != UCMODE_0;
   }
 
-  inline bool isBusy() /* true if a SPI transaction is in progress */
+  inline bool isBusy() /* TRUE if a SPI transaction is in progress */
   {
     atomic return m_len != 0;
   }
@@ -158,12 +161,24 @@ implementation {
     }
   }
 
+  task void signalSendDone()
+  {
+    error_t error = (m_pos == m_len) ? SUCCESS : FAIL;
+
+    m_len = 0;
+    atomic signal SpiPacket.sendDone(m_txBuf, m_rxBuf, m_pos, error);
+  }
+
   async command void ResourceConfigure.unconfigure()
   {
     atomic {
       /* Disable the device */
       call Registers.setCtl1(UCSWRST);
 
+      /* Ensure SpiPacket.sendDone is posted if a trx was in progress */
+      if (m_len)
+	post signalSendDone();
+
       /* Clear interrupts and interrupt flags.  We only used Rx */
       call Registers.clrIeRx();
       call Registers.clrIfgRx();
@@ -192,25 +207,43 @@ implementation {
     }
   }
 
+  bool waitOnRx()
+  {
+    for (;;) {
+      if (call Registers.getIfgRx())
+	return TRUE;
+      if (call CSn.get())		/* SPI master has unselected us */
+	return FALSE;
+    }
+  }
+
+  bool waitOnTx()
+  {
+    for (;;) {
+      if (call Registers.getIfgTx())
+	return TRUE;
+      if (call CSn.get())		/* SPI master has unselected us */
+	return FALSE;
+    }
+  }
+
   async command uint8_t SpiByte.write(uint8_t byte)
   {
-    if (isBusy())
-      return 0;
-    else {
-      while (!call Registers.getIfgTx() && !call Registers.getCtl1(UCSWRST));
-      call Registers.setTxbuf(byte);
-      while(!call Registers.getIfgRx() && !call Registers.getCtl1(UCSWRST));
-      return call Registers.getRxbuf();
+    atomic {
+      if (isBusy())
+	return 0;
+      else {
+	waitOnTx();
+	call Registers.setTxbuf(byte);
+	waitOnRx();
+	return call Registers.getRxbuf();
+      }
     }
   }
 
-  void sendData()
+  /* If we are a slave, return FALSE if the master has unasserted CSn. */
+  bool sendData()
   {
-    /* We don't need to check Registers.getIfgTx() (aks UCxxTXIFG), as
-     * sendData() is only called after peripheral init or receipt of the rx()
-     * interrupt.  SPI on msp430 guarantees UCxxTXIFG is asserted in both of
-     * these cases.
-     */
     atomic {
       uint16_t end = m_pos + (blockSize ? blockSize : BLOCKSIZE_DEFAULT);
       uint8_t tmp;
@@ -219,13 +252,14 @@ implementation {
 	end = m_len;
       call Registers.setTxbuf(m_txBuf ? m_txBuf[m_pos] : 0);
       while (++m_pos < end) {
-	while (!call Registers.getIfgRx() && !call Registers.getCtl1(UCSWRST));
+	waitOnRx();
 	tmp = call Registers.getRxbuf();
 	if (m_rxBuf)
-	  m_rxBuf[m_pos - 1] = call Registers.getRxbuf();
-	while (!call Registers.getIfgTx() && !call Registers.getCtl1(UCSWRST));
+	  m_rxBuf[m_pos - 1] = tmp;
+	waitOnTx();
 	call Registers.setTxbuf(m_txBuf ? m_txBuf[m_pos] : 0);
       }
+      return call CSn.get() ? FALSE : TRUE;
     }
   }
 
@@ -235,40 +269,31 @@ implementation {
     if (isBusy() || (!txBuf && !rxBuf) || len == 0)
       return FAIL;
     else {
-      atomic {
-	m_txBuf = txBuf;
-	m_rxBuf = rxBuf;
-	m_len = len;
-	m_pos = 0;
+      m_txBuf = txBuf;
+      m_rxBuf = rxBuf;
+      m_len = len;
+      m_pos = 0;
+      if (sendData())
 	call Registers.setIeRx();
-	sendData();
-	return SUCCESS;
-      }
+      else
+	post signalSendDone();
+      return SUCCESS;
     }
   }
 
   async event void Interrupts.tx() {}
 
-  task void signalSendDone()
-  {
-    atomic {
-      uint16_t len = m_len;
-      m_len = 0;
-      signal SpiPacket.sendDone(m_txBuf, m_rxBuf, len, SUCCESS);
-    }
-  }
-
   async event void Interrupts.rx(uint8_t byte)
   {
     if (m_rxBuf)
       m_rxBuf[m_pos - 1] = byte;
 
-    if (m_pos < m_len)
-      sendData();
-    else {
-      call Registers.clrIeRx();
-      post signalSendDone(); /* Don't signal from ISR context */
+    if (m_pos < m_len) {
+      if (sendData())
+	return;
     }
+    call Registers.clrIeRx();
+    post signalSendDone();
   }
 
   default async event void SpiPacket.sendDone(uint8_t*, uint8_t*, uint16_t,
@@ -292,4 +317,6 @@ implementation {
   async event void Interrupts.i2cCal() {}
   async event void Interrupts.brk() {}
   async event void Interrupts.i2cNak() {}
+
+  default async command bool CSn.get() { return FALSE; }
 }