X-Git-Url: https://oss.titaniummirror.com/gitweb/?a=blobdiff_plain;f=tos%2Fchips%2Fmsp430%2Fusci%2FMsp430SpiP.nc;h=93b942227bb5baf4f5be13d088a5ab0203b2f296;hb=a04046a3331f1baba1e6a568613fec5db58bbe7b;hp=22584fd8f39d2545ed998a9cef127e8fa80db243;hpb=10acc57d16a648d746eed9d5c6264850f7c52fde;p=tinyos-2.x.git diff --git a/tos/chips/msp430/usci/Msp430SpiP.nc b/tos/chips/msp430/usci/Msp430SpiP.nc index 22584fd8..93b94222 100644 --- a/tos/chips/msp430/usci/Msp430SpiP.nc +++ b/tos/chips/msp430/usci/Msp430SpiP.nc @@ -26,14 +26,20 @@ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ - + /** - * Spi implementation using a USCI device. + * Spi implementation using a USCI device. When being used as a SPI slave, the + * CSn interface should be wired to the chip select driven by the SPI master so + * the module can know when a communications session is terminated unexpectedly. + * + * TODO: Implement error checking via UCxxSTAT + * + * NOTE: Define NO_REN_ON_SPI to disable PxREN bits when SPI is acquired. * - * @author R. Steve McKown + * @author R. Steve McKown */ - -generic module Msp430SpiP() { + +generic module Msp430SpiP(uint16_t blockSize) { provides { interface SpiByte; interface SpiPacket; @@ -42,125 +48,276 @@ generic module Msp430SpiP() { uses { interface HplMsp430UsciReg as Registers; interface HplMsp430UsciInt as Interrupts; + interface GeneralIO as CSn; interface HplMsp430GeneralIO as STE; interface HplMsp430GeneralIO as SIMO; interface HplMsp430GeneralIO as SOMI; - interface HplMsp430GeneralIO as SCL; - interface Msp430UsciSpiConfigure; /* maybe just Msp430UsciConfigure */ - interface Counter + interface HplMsp430GeneralIO as CLK; + interface AsyncConfigure as Configure; interface ArbiterInfo; } } implementation { - #define saveBits(pin, pos, dir, out, ren) { \ - if (call pin.isOutput()) \ - dir |= (1 << pos); \ - if (call pin.getOut()) \ - out |= (1 << pos); \ - if (call pin.isRen()) \ - ren |= (1 << pos); \ - } - - #define restoreBits(pin, pos, dir, out, ren) { \ - if (ren & (1 << pos)) \ - call pin.enableRen(); \ - else \ - call pin.disableRen(); \ - if (out & (1 << pos)) \ - call pin.set(); \ - else \ - call pin.clr(); \ - if (dir & (1 << pos)) \ - call pin.makeOutput(); \ - else \ - call pin.makeInput(); \ - } - - uint8_t dir; /* Pin state storage to allow for proper unconfiguration */ - uint8_t out; - uint8_t ren; - - async command void ResourceConfigure.configure(); + enum { + BLOCKSIZE_DEFAULT = 64, + + /* Bit positions in m_pins */ + PINS_STE = 0, + PINS_SOMI, + PINS_SIMO, + PINS_CLK, +#ifdef NO_REN_ON_SPI + PINS_RENADDR, /* This gets added to store the PxREN bit */ +#endif + }; + + uint8_t m_pins; + norace uint8_t* m_txBuf; + norace uint8_t* m_rxBuf; + norace uint16_t m_len; + norace uint16_t m_pos; + + inline bool is4pin() /* TRUE if the SPI bus is in 4-pin mode */ { - call Registers.setCtl0(UCSYNC); - /* Save pin states */ - dir = out = ren = 0; - saveBits(STE, 0, dir, out, ren); - saveBits(SIMO, 1, dir, out, ren); - saveBits(SOMI, 2, dir, out, ren); - saveBits(SCL, 3, dir, out, ren); - /* FIXME: use Msp430UsciConfig to configure ports */ - /* FIXME: we may need to have REN/DIR stuff in the configuration... */ - if (call Registers.getCtl1(UCMODE_3) != UCMODE_0) { - call STE.selectModuleFunc(); - call SIMO.selectModuleFunc(); - call SOMI.selectModuleFunc(); - call SCL.selectModuleFunc(); - /* Clear interrupts; we'll add them as needed */ - call Registers.clrCtl1(UCRXEIE|UCBRKIE); - call Registers.clrIeRx(); - call Registers.clrIeTx(); - /* Enable the device */ - call Registers.clrCtl0(UCSYNC); + return (call Registers.getCtl0(UCMODE_3)) != UCMODE_0; } - async command void ResourceConfigure.unconfigure(); + inline bool isBusy() /* TRUE if a SPI transaction is in progress */ { - /* Disable the device */ - call Registers.setCtl0(UCSYNC); - /* Clear interrupts and interrupt flags */ - call Registers.clrIeRx(); - call Registers.clrIeTx(); - call Registers.clrIfgRx(); - call Registers.clrIfgTx(); - /* Restore pins to state just before configure() */ - restoreBits(SIMO, 1, dir, out, ren); - restoreBits(SOMI, 2, dir, out, ren); - restoreBits(SCL, 3, dir, out, ren); - call SIMO.selectIOFunc(); - call SOMI.selectIOFunc(); - call SCL.selectIOFunc(); - /* Restore more if we were using 4-pin SPI */ - if (call Registers.getCtl1(UCMODE_3) != UCMODE_0) { - restoreBits(STE, 0, dir, out, ren); - call STE.selectIOFunc(); + atomic return m_len != 0; + } + + async command void ResourceConfigure.configure() + { + atomic { + const msp430_usci_spi_t* config = call Configure.get(); + uint8_t ctl0; + + call Registers.setCtl1(UCSWRST); + + /* UCMODE_3 is invalid for SPI. Presume the configuration data + * are wrong and force 3-pin SPI as a minimially safe alternative. + */ + ctl0 = config->ctl0 | UCSYNC; + if ((ctl0 & UCMODE_3) == UCMODE_3) + ctl0 &= ~(UCMODE_3); + + /* Configure USCI registers */ + call Registers.assignCtl0(ctl0); + call Registers.assignCtl1(config->ctl1 | UCSWRST); + call Registers.assignBr0(config->brx & 0xff); + call Registers.assignBr1(config->brx >> 8); + call Registers.assignMctl(0); + if (config->uclisten) + call Registers.setStat(UCLISTEN); + else + call Registers.clrStat(UCLISTEN); + + /* Configure pins for SPI, saving prior pin states */ + m_pins = 0; +#ifdef NO_REN_ON_SPI + /* - First save off and disable PxREN bits */ + if (is4pin() && call STE.isRen()) { + m_pins |= (1 << (PINS_STE + PINS_RENADDR)); + call STE.disableRen(); + } + if (call SOMI.isRen()) { + m_pins |= (1 << (PINS_SOMI + PINS_RENADDR)); + call SOMI.disableRen(); + } + if (call SIMO.isRen()) { + m_pins |= (1 << (PINS_SIMO + PINS_RENADDR)); + call SIMO.disableRen(); + } + if (call CLK.isRen()) { + m_pins |= (1 << (PINS_CLK + PINS_RENADDR)); + call CLK.disableRen(); + } +#endif + /* - Then save off IOFunc state and enable ModuleFunc */ + if (is4pin() && call STE.isIOFunc()) { + m_pins |= (1 << PINS_STE); + call STE.selectModuleFunc(); + } + if (call SOMI.isIOFunc()) { + m_pins |= (1 << PINS_SOMI); + call SOMI.selectModuleFunc(); + } + if (call SIMO.isIOFunc()) { + m_pins |= (1 << PINS_SIMO); + call SIMO.selectModuleFunc(); + } + if (call CLK.isIOFunc()) { + m_pins |= (1 << PINS_CLK); + call CLK.selectModuleFunc(); + } + + /* Clear interrupts; we'll add them as needed */ + call Registers.clrIeRx(); + call Registers.clrIeTx(); + + /* Enable the device */ + call Registers.clrCtl1(UCSWRST); } } + task void signalSendDone() + { + error_t error = (m_pos == m_len) ? SUCCESS : FAIL; + + m_len = 0; + atomic signal SpiPacket.sendDone(m_txBuf, m_rxBuf, m_pos, error); + } - async event void Interrupts.tx() + async command void ResourceConfigure.unconfigure() { - while (slen && call Registers.getIfgTx()) { - call Registers.setTxbuf(*sbuf); - if (--slen) - sbuf++; + atomic { + /* Disable the device */ + call Registers.setCtl1(UCSWRST); + + /* Ensure SpiPacket.sendDone is posted if a trx was in progress */ + if (m_len) + post signalSendDone(); + + /* Clear interrupts and interrupt flags. We only used Rx */ + call Registers.clrIeRx(); + call Registers.clrIfgRx(); + + /* Restore pins to their pre-configure state */ + /* - First restore IOFunc states */ + if (is4pin() && (m_pins & (1 << PINS_STE))) + call STE.selectIOFunc(); + if (m_pins & (1 << PINS_SIMO)) + call SIMO.selectIOFunc(); + if (m_pins & (1 << PINS_SOMI)) + call SOMI.selectIOFunc(); + if (m_pins & (1 << PINS_CLK)) + call CLK.selectIOFunc(); + /* - Then restore PxREN bits */ +#ifdef NO_REN_ON_SPI + if (is4pin() && (m_pins & (1 << (PINS_STE + PINS_RENADDR)))) + call STE.enableRen(); + if (m_pins & (1 << (PINS_SIMO + PINS_RENADDR))) + call SIMO.enableRen(); + if (m_pins & (1 << (PINS_SOMI + PINS_RENADDR))) + call SOMI.enableRen(); + if (m_pins & (1 << (PINS_CLK + PINS_RENADDR))) + call CLK.enableRen(); +#endif } - if (slen == 0 && sobuf) { - call Registers.clrIeTx(); - call Registers.clrIfgTx(); - sobuf = 0; - signal UartStream.sendDone(sobuf, solen, SUCCESS); + } + + bool waitOnRx() + { + for (;;) { + if (call Registers.getIfgRx()) + return TRUE; + if (call CSn.get()) /* SPI master has unselected us */ + return FALSE; } } - async event void Interrupts.rx(uint8_t byte) + bool waitOnTx() { - if (robuf) { - /* receive() takes precedence if active */ - while (rlen && call Registers.getIfgRx()) { - *rbuf = byte; - if (--rlen) - rbuf++; + for (;;) { + if (call Registers.getIfgTx()) + return TRUE; + if (call CSn.get()) /* SPI master has unselected us */ + return FALSE; + } + } + + async command uint8_t SpiByte.write(uint8_t byte) + { + atomic { + if (isBusy()) + return 0; + else { + waitOnTx(); + call Registers.setTxbuf(byte); + waitOnRx(); + return call Registers.getRxbuf(); } - if (rlen == 0 && robuf) { - if (rxie) { - call Registers.clrIeRx(); - call Registers.clrIfgRx(); - } - robuf = 0; - signal UartStream.receiveDone(robuf, rolen, SUCCESS); + } + } + + /* If we are a slave, return FALSE if the master has unasserted CSn. */ + bool sendData() + { + atomic { + uint16_t end = m_pos + (blockSize ? blockSize : BLOCKSIZE_DEFAULT); + uint8_t tmp; + + if (end > m_len) + end = m_len; + waitOnTx(); /* Don't assume that the last tx is done already */ + call Registers.setTxbuf(m_txBuf ? m_txBuf[m_pos] : 0); + while (++m_pos < end) { + waitOnRx(); + tmp = call Registers.getRxbuf(); + if (m_rxBuf) + m_rxBuf[m_pos - 1] = tmp; + waitOnTx(); + call Registers.setTxbuf(m_txBuf ? m_txBuf[m_pos] : 0); } - } else - signal UartStream.receivedByte(byte); + return call CSn.get() ? FALSE : TRUE; + } } + + async command error_t SpiPacket.send(uint8_t* txBuf, uint8_t* rxBuf, + uint16_t len) + { + if (isBusy() || (!txBuf && !rxBuf) || len == 0) + return FAIL; + else { + m_txBuf = txBuf; + m_rxBuf = rxBuf; + m_len = len; + m_pos = 0; + if (sendData()) + call Registers.setIeRx(); + else + post signalSendDone(); + return SUCCESS; + } + } + + async event void Interrupts.tx() {} + + async event void Interrupts.rx(uint8_t byte) + { + if (m_rxBuf) + m_rxBuf[m_pos - 1] = byte; + + if (m_pos < m_len) { + if (sendData()) + return; + } + call Registers.clrIeRx(); + post signalSendDone(); + } + + default async event void SpiPacket.sendDone(uint8_t*, uint8_t*, uint16_t, + error_t) {} + + default async command const msp430_usci_spi_t* Configure.get() + { + const static msp430_usci_spi_t def = { + ctl0: UCSYNC | UCMODE_0 | UCMST, /* 3-pin SPI mode 0, LSB first */ + ctl1: UCSWRST | UCSSEL_3, /* SPI clock source is SMCLK */ + brx: 10, /* SPI clock=SMCLK/10; ~105KHz if SMCLK=1MHz */ + uclisten: FALSE, + ren: USCI_REN_NONE + }; + + return &def; + } + + async event void Interrupts.i2cStart() {} + async event void Interrupts.i2cStop() {} + async event void Interrupts.i2cCal() {} + async event void Interrupts.brk() {} + async event void Interrupts.i2cNack() {} + + default async command bool CSn.get() { return FALSE; } }