X-Git-Url: https://oss.titaniummirror.com/gitweb/?a=blobdiff_plain;f=tos%2Fchips%2Fmsp430%2Fusci%2FMsp430SpiP.nc;h=ed8b6743722994273d3d70816f4bad0e8cbf2d07;hb=be862ab07d080085823951d18dcb27a28a310ace;hp=22bfbbd376b1aa00237b8539a94b7ab402ea7a4f;hpb=753d22d3f0f9764e9a4cdfbefdcf45ff9db4c3cc;p=tinyos-2.x.git

diff --git a/tos/chips/msp430/usci/Msp430SpiP.nc b/tos/chips/msp430/usci/Msp430SpiP.nc
index 22bfbbd3..ed8b6743 100644
--- a/tos/chips/msp430/usci/Msp430SpiP.nc
+++ b/tos/chips/msp430/usci/Msp430SpiP.nc
@@ -10,7 +10,7 @@
  * - Redistributions in binary form must reproduce the above copyright
  *   notice, this list of conditions and the following disclaimer in the
  *   documentation and/or other materials provided with the distribution.
- * - Neither the name of the Technische Universität Berlin nor the names
+ * - Neither the name of the Titanium Mirror, Inc. nor the names
  *   of its contributors may be used to endorse or promote products derived
  *   from this software without specific prior written permission.
  *
@@ -26,7 +26,7 @@
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
  * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
- 
+
 /**
  * Spi implementation using a USCI device.  When being used as a SPI slave, the
  * CSn interface should be wired to the chip select driven by the SPI master so
@@ -38,7 +38,7 @@
  *
  * @author R. Steve McKown <rsmckown@gmail.com>
  */
- 
+
 generic module Msp430SpiP(uint16_t blockSize) {
   provides {
     interface SpiByte;
@@ -250,6 +250,7 @@ implementation {
 
       if (end > m_len)
 	end = m_len;
+      waitOnTx(); /* Don't assume that the last tx is done already */
       call Registers.setTxbuf(m_txBuf ? m_txBuf[m_pos] : 0);
       while (++m_pos < end) {
 	waitOnRx();
@@ -301,7 +302,7 @@ implementation {
 
   default async command const msp430_usci_spi_t* Configure.get()
   {
-    const static msp430_usci_spi_t def = { 
+    const static msp430_usci_spi_t def = {
       ctl0: UCSYNC | UCMODE_0 | UCMST,	/* 3-pin SPI mode 0, LSB first */
       ctl1: UCSWRST | UCSSEL_3,		/* SPI clock source is SMCLK */
       brx: 10,			/* SPI clock=SMCLK/10; ~105KHz if SMCLK=1MHz */
@@ -316,7 +317,7 @@ implementation {
   async event void Interrupts.i2cStop() {}
   async event void Interrupts.i2cCal() {}
   async event void Interrupts.brk() {}
-  async event void Interrupts.i2cNak() {}
+  async event void Interrupts.i2cNack() {}
 
   default async command bool CSn.get() { return FALSE; }
 }