X-Git-Url: https://oss.titaniummirror.com/gitweb/?a=blobdiff_plain;f=tos%2Fchips%2Fmsp430%2Fusci%2FMsp430UartP.nc;h=605c426960f5d926d10670ec8582a70dc76383f6;hb=2d252cfb688eee6ff8aa13bef1efb1627cb866f8;hp=a4bec07698e521599d379e4c4634fb885e8d296a;hpb=88bc2aa5e7e7c3870700a40d78829b51d3ae3754;p=tinyos-2.x.git

diff --git a/tos/chips/msp430/usci/Msp430UartP.nc b/tos/chips/msp430/usci/Msp430UartP.nc
index a4bec076..605c4269 100644
--- a/tos/chips/msp430/usci/Msp430UartP.nc
+++ b/tos/chips/msp430/usci/Msp430UartP.nc
@@ -26,7 +26,7 @@
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
  * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
- 
+
 /**
  * Uart implementation using a USCI device.
  *
@@ -35,7 +35,7 @@
  *
  * @author R. Steve McKown <rsmckown@gmail.com>
  */
- 
+
 generic module Msp430UartP() {
   provides {
     interface UartStream;
@@ -55,7 +55,7 @@ generic module Msp430UartP() {
 implementation {
   enum {
     /* Bit positions in m_pins */
-    PINS_RXD = 1,
+    PINS_RXD = 0,
     PINS_TXD
   };
 
@@ -104,12 +104,20 @@ implementation {
 	call TXD.selectModuleFunc();
       }
 
+      /* Reset important state variables */
+      m_robuf = 0;
+      m_sobuf = 0;
+
       /* Clear interrupts; we'll add them as needed */
       call Registers.clrIeRx();
       call Registers.clrIeTx();
 
       /* Enable the device */
       call Registers.clrCtl1(UCSWRST);
+
+      /* TOS convention is for receive interrupts on by default. */
+      call Registers.clrIfgRx();
+      call Registers.setIeRx();
     }
   }
 
@@ -124,10 +132,14 @@ implementation {
       call Registers.clrIeTx();
       call Registers.clrIfgRx();
 
+      /* Reset important state variables */
+      m_robuf = 0;
+      m_sobuf = 0;
+
       /* Restore pins to their pre-configure state */
-      if (m_pins & PINS_RXD)
+      if (m_pins & (1 << PINS_RXD))
 	call RXD.selectIOFunc();
-      if (m_pins & PINS_TXD)
+      if (m_pins & (1 << PINS_TXD))
 	call TXD.selectIOFunc();
     }
   }
@@ -158,16 +170,18 @@ implementation {
     /* FIXME: this can cause an arbitrarily long ISR, if m_slen is large.
      * But depending on timing, we may always only write 1 byte.
      */
-    while (!call Registers.getIfgTx()); /* in case interleaved UB.send */
-    while (m_slen && call Registers.getIfgTx()) {
-      call Registers.setTxbuf(*m_sbuf);
-      if (--m_slen)
-	m_sbuf++;
-    }
-    if (m_slen == 0) {
-      call Registers.clrIeTx();
-      m_sobuf = 0;
-      signal UartStream.sendDone(m_sobuf, m_solen, SUCCESS);
+    if (m_sobuf) {
+      while (!call Registers.getIfgTx()); /* in case interleaved UB.send */
+      while (m_slen && call Registers.getIfgTx()) {
+	call Registers.setTxbuf(*m_sbuf);
+	if (--m_slen)
+	  m_sbuf++;
+      }
+      if (m_slen == 0) {
+	call Registers.clrIeTx();
+	m_sobuf = 0;
+	signal UartStream.sendDone(m_sobuf, m_solen, SUCCESS);
+      }
     }
   }
 
@@ -256,7 +270,7 @@ implementation {
 
   default async command const msp430_usci_uart_t* Configure.get()
   {
-    const static msp430_usci_uart_t def = { 
+    const static msp430_usci_uart_t def = {
       ctl0: UCMODE_0,		/* async, lsb first, 8N1 */
       ctl1: UCSWRST | UCSSEL_3,	/* clock uart from SMCLK */
       brx: UBRX_1MHZ_115200,