X-Git-Url: https://oss.titaniummirror.com/gitweb/?a=blobdiff_plain;f=tos%2Fchips%2Fmsp430%2Fusci%2FMsp430UartP.nc;h=72df1df0c1827f63ef14f7836a5927aaa43b3828;hb=e9bfab607e051bae6afb47b44892ce37541d1b44;hp=dcdc5b380d8370aa01507bf9783a5ececba13822;hpb=9b3bcb092b6b9fba236a452663d71a39189ea283;p=tinyos-2.x.git diff --git a/tos/chips/msp430/usci/Msp430UartP.nc b/tos/chips/msp430/usci/Msp430UartP.nc index dcdc5b38..72df1df0 100644 --- a/tos/chips/msp430/usci/Msp430UartP.nc +++ b/tos/chips/msp430/usci/Msp430UartP.nc @@ -26,7 +26,7 @@ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ - + /** * Uart implementation using a USCI device. * @@ -35,7 +35,7 @@ * * @author R. Steve McKown */ - + generic module Msp430UartP() { provides { interface UartStream; @@ -146,14 +146,9 @@ implementation { atomic { if (m_sobuf || !buf || !len) return FAIL; - m_sobuf = buf; - m_solen = len; - while (!call Registers.getIfgTx()); + m_sbuf = m_sobuf = buf; + m_slen = m_solen = len; call Registers.setIeTx(); - call Registers.setTxbuf(*m_sobuf); - m_slen = m_solen - 1; - if (m_slen) - m_sbuf = m_sobuf + 1; return SUCCESS; } } @@ -163,12 +158,13 @@ implementation { /* FIXME: this can cause an arbitrarily long ISR, if m_slen is large. * But depending on timing, we may always only write 1 byte. */ + while (!call Registers.getIfgTx()); /* in case interleaved UB.send */ while (m_slen && call Registers.getIfgTx()) { call Registers.setTxbuf(*m_sbuf); if (--m_slen) m_sbuf++; } - if (m_slen == 0 && m_sobuf) { + if (m_slen == 0) { call Registers.clrIeTx(); m_sobuf = 0; signal UartStream.sendDone(m_sobuf, m_solen, SUCCESS); @@ -260,7 +256,7 @@ implementation { default async command const msp430_usci_uart_t* Configure.get() { - const static msp430_usci_uart_t def = { + const static msp430_usci_uart_t def = { ctl0: UCMODE_0, /* async, lsb first, 8N1 */ ctl1: UCSWRST | UCSSEL_3, /* clock uart from SMCLK */ brx: UBRX_1MHZ_115200,