X-Git-Url: https://oss.titaniummirror.com/gitweb/?a=blobdiff_plain;f=tos%2Fchips%2Fmsp430%2Fusci%2FMsp430UartP.nc;h=a35dd92eb8d4b05a2296b1612ecde05f79d30b44;hb=dfbae4ae464c8990d122cc07951edcdbc1983ac4;hp=1b595bfdbd9af40369beceb8128264f6f6620183;hpb=0290d9081acdbe813926612478fbe81e7a44e3c5;p=tinyos-2.x.git diff --git a/tos/chips/msp430/usci/Msp430UartP.nc b/tos/chips/msp430/usci/Msp430UartP.nc index 1b595bfd..a35dd92e 100644 --- a/tos/chips/msp430/usci/Msp430UartP.nc +++ b/tos/chips/msp430/usci/Msp430UartP.nc @@ -26,7 +26,7 @@ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ - + /** * Uart implementation using a USCI device. * @@ -35,7 +35,7 @@ * * @author R. Steve McKown */ - + generic module Msp430UartP() { provides { interface UartStream; @@ -104,6 +104,10 @@ implementation { call TXD.selectModuleFunc(); } + /* Reset important state variables */ + m_robuf = 0; + m_sobuf = 0; + /* Clear interrupts; we'll add them as needed */ call Registers.clrIeRx(); call Registers.clrIeTx(); @@ -124,6 +128,10 @@ implementation { call Registers.clrIeTx(); call Registers.clrIfgRx(); + /* Reset important state variables */ + m_robuf = 0; + m_sobuf = 0; + /* Restore pins to their pre-configure state */ if (m_pins & PINS_RXD) call RXD.selectIOFunc(); @@ -134,10 +142,7 @@ implementation { async command error_t UartByte.send(uint8_t byte) { - /* FIXME: race with UartStream.send() */ atomic { - if (m_sobuf) - return FAIL; while (!call Registers.getIfgTx()); call Registers.setTxbuf(byte); return SUCCESS; @@ -149,29 +154,30 @@ implementation { atomic { if (m_sobuf || !buf || !len) return FAIL; - m_sobuf = buf; - m_solen = len; - while (!call Registers.getIfgTx()); + m_sbuf = m_sobuf = buf; + m_slen = m_solen = len; call Registers.setIeTx(); - call Registers.setTxbuf(*m_sobuf); - m_slen = m_solen - 1; - if (m_slen) - m_sbuf = m_sobuf + 1; return SUCCESS; } } async event void Interrupts.tx() { - while (m_slen && call Registers.getIfgTx()) { - call Registers.setTxbuf(*m_sbuf); - if (--m_slen) - m_sbuf++; - } - if (m_slen == 0 && m_sobuf) { - call Registers.clrIeTx(); - m_sobuf = 0; - signal UartStream.sendDone(m_sobuf, m_solen, SUCCESS); + /* FIXME: this can cause an arbitrarily long ISR, if m_slen is large. + * But depending on timing, we may always only write 1 byte. + */ + if (m_sobuf) { + while (!call Registers.getIfgTx()); /* in case interleaved UB.send */ + while (m_slen && call Registers.getIfgTx()) { + call Registers.setTxbuf(*m_sbuf); + if (--m_slen) + m_sbuf++; + } + if (m_slen == 0) { + call Registers.clrIeTx(); + m_sobuf = 0; + signal UartStream.sendDone(m_sobuf, m_solen, SUCCESS); + } } } @@ -236,30 +242,31 @@ implementation { async event void Interrupts.rx(uint8_t byte) { - atomic { - if (m_robuf) { - /* receive() takes precedence if active */ - while (m_rlen && call Registers.getIfgRx()) { - *m_rbuf = byte; - if (--m_rlen) - m_rbuf++; - } - if (m_rlen == 0 && m_robuf) { - if (m_rxie) { - call Registers.clrIeRx(); - call Registers.clrIfgRx(); - } - m_robuf = 0; - signal UartStream.receiveDone(m_robuf, m_rolen, SUCCESS); + if (m_robuf) { + /* receive() takes precedence if active */ + /* FIXME: an arbitrarily long ISR may occur if m_rlen is large. + * But depending on timing, we may always only read 1 byte. + */ + while (m_rlen && call Registers.getIfgRx()) { + *m_rbuf = byte; + if (--m_rlen) + m_rbuf++; + } + if (m_rlen == 0 && m_robuf) { + if (m_rxie) { + call Registers.clrIeRx(); + call Registers.clrIfgRx(); } - } else - signal UartStream.receivedByte(byte); - } + m_robuf = 0; + signal UartStream.receiveDone(m_robuf, m_rolen, SUCCESS); + } + } else + signal UartStream.receivedByte(byte); } default async command const msp430_usci_uart_t* Configure.get() { - const static msp430_usci_uart_t def = { + const static msp430_usci_uart_t def = { ctl0: UCMODE_0, /* async, lsb first, 8N1 */ ctl1: UCSWRST | UCSSEL_3, /* clock uart from SMCLK */ brx: UBRX_1MHZ_115200,