X-Git-Url: https://oss.titaniummirror.com/gitweb/?a=blobdiff_plain;f=tos%2Fchips%2Fmsp430%2Fusci%2FMsp430UsciA0C.nc;h=cf4ee6eeea608502c3732a5ff78d23c63112de5e;hb=e9bfab607e051bae6afb47b44892ce37541d1b44;hp=ed0e97539ede1f92e66ad6776d3850fe9d01e9fb;hpb=2ba7058c1f5127b488ea4994a454b02d37f7de2e;p=tinyos-2.x.git diff --git a/tos/chips/msp430/usci/Msp430UsciA0C.nc b/tos/chips/msp430/usci/Msp430UsciA0C.nc index ed0e9753..cf4ee6ee 100644 --- a/tos/chips/msp430/usci/Msp430UsciA0C.nc +++ b/tos/chips/msp430/usci/Msp430UsciA0C.nc @@ -26,40 +26,35 @@ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ - + /** * Defines the USCI_A0 peripheral. - * - * @author R. Steve McKown + * + * @author R. Steve McKown */ - + configuration Msp430UsciA0C { provides { interface HplMsp430UsciReg as Registers; - interface HplMsp430UsciIntA as Interrupts[uint8_t]; + interface HplMsp430UsciInt as Interrupts[uint8_t]; interface Resource as Resource[uint8_t]; interface ResourceRequested as ResourceRequested[uint8_t]; interface ArbiterInfo; } - uses interface ResourceConfig as ResourceConfig[uint8_t]; + uses interface ResourceConfigure as ResourceConfigure[uint8_t]; } implementation { - components new HplMsp430UsciRegP(UCA0CTL0_, UCA0CTL1_, UCA0BR0_, UCA0BR1_, - UCA0MCTL_, 0/*UCA0I2CIE_*/, UCA0STAT_, UCA0RXBUF_, UCA0TXBUF_, UCA0ABCTL_, - UCA0IRTCTL_, UCA0IRRCTL_, 0/*UCA0I2COA_*/, 0/*UCA0I2CSA_*/, IE2_, IFG2_) - as RegP; - Registers = RegP; - components new FcfsArbiterC(MSP430_USCIA0_RESOURCE) as ArbiterC; Resource = ArbiterC; ResourceRequested = ArbiterC; ResourceConfigure = ArbiterC; ArbiterInfo = ArbiterC; - components new Msp430UsciIntDispatchAP() as IntDispatchA0P; - Interrupts = IntDispatchA0P.IntAx; + components new Msp430UsciIntDispatchP() as IntDispatchA0P; + Interrupts = IntDispatchA0P; IntDispatchA0P.ArbiterInfo -> ArbiterC; - components HplMsp430UsciInt0C as Int0C; - IntDispatchA0P.RawIntAx -> Int0C.IntA; + components HplMsp430UsciC as UsciC; + Registers = UsciC.RegA0; + IntDispatchA0P.RawInt -> UsciC.IntA0; }