X-Git-Url: https://oss.titaniummirror.com/gitweb/?a=blobdiff_plain;f=tos%2Fchips%2Fmsp430%2Fusci%2FMsp430UsciB0C.nc;h=12f821ef4f8a1b2885881ed5f4619c29cf343def;hb=e9bfab607e051bae6afb47b44892ce37541d1b44;hp=2ce825fc7299bcb5d84873fbc68e86286bc1fd29;hpb=2ba7058c1f5127b488ea4994a454b02d37f7de2e;p=tinyos-2.x.git diff --git a/tos/chips/msp430/usci/Msp430UsciB0C.nc b/tos/chips/msp430/usci/Msp430UsciB0C.nc index 2ce825fc..12f821ef 100644 --- a/tos/chips/msp430/usci/Msp430UsciB0C.nc +++ b/tos/chips/msp430/usci/Msp430UsciB0C.nc @@ -26,40 +26,35 @@ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ - + /** * Defines the USCI_B0 peripheral. - * - * @author R. Steve McKown + * + * @author R. Steve McKown */ - + configuration Msp430UsciB0C { provides { interface HplMsp430UsciReg as Registers; - interface HplMsp430UsciIntA as Interrupts[uint8_t]; + interface HplMsp430UsciInt as Interrupts[uint8_t]; interface Resource as Resource[uint8_t]; interface ResourceRequested as ResourceRequested[uint8_t]; interface ArbiterInfo; } - uses interface ResourceConfig as ResourceConfig[uint8_t]; + uses interface ResourceConfigure as ResourceConfigure[uint8_t]; } implementation { - components new HplMsp430UsciRegP(UCB0CTL0_, UCB0CTL1_, UCB0BR0_, UCB0BR1_, - 0/*UCB0MCTL_*/, UCB0I2CIE_, UCB0STAT_, UCB0RXBUF_, UCB0TXBUF_, - 0/*UCB0ABCTL_*/, 0/*UCB0IRTCTL_*/, 0/*UCB0IRRCTL_*/, UCB0I2COA_, - UCB0I2CSA_, IE2_, IFG2_) as RegP; - Registers = RegP; - components new FcfsArbiterC(MSP430_USCIB0_RESOURCE) as ArbiterC; Resource = ArbiterC; ResourceRequested = ArbiterC; ResourceConfigure = ArbiterC; ArbiterInfo = ArbiterC; - components new Msp430UsciIntDispatchAP() as IntDispatchB0P; - Interrupts = IntDispatchB0P.IntAx; + components new Msp430UsciIntDispatchP() as IntDispatchB0P; + Interrupts = IntDispatchB0P; IntDispatchB0P.ArbiterInfo -> ArbiterC; - components HplMsp430UsciInt0C as Int0C; - IntDispatchB0P.RawIntAx -> Int0C.IntA; + components HplMsp430UsciC as UsciC; + Registers = UsciC.RegB0; + IntDispatchB0P.RawInt -> UsciC.IntB0; }