X-Git-Url: https://oss.titaniummirror.com/gitweb/?a=blobdiff_plain;f=tos%2Fchips%2Fmsp430%2Fusci%2FMsp430UsciB1C.nc;h=81b5e60751685f6b4edbc310ffc8ce6e05f45cef;hb=e9bfab607e051bae6afb47b44892ce37541d1b44;hp=27f4645da6dd62c13508ec93ddf6d9080698fbb9;hpb=2ba7058c1f5127b488ea4994a454b02d37f7de2e;p=tinyos-2.x.git diff --git a/tos/chips/msp430/usci/Msp430UsciB1C.nc b/tos/chips/msp430/usci/Msp430UsciB1C.nc index 27f4645d..81b5e607 100644 --- a/tos/chips/msp430/usci/Msp430UsciB1C.nc +++ b/tos/chips/msp430/usci/Msp430UsciB1C.nc @@ -26,40 +26,35 @@ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ - + /** * Defines the USCI_B1 peripheral. - * - * @author R. Steve McKown + * + * @author R. Steve McKown */ - + configuration Msp430UsciB1C { provides { interface HplMsp430UsciReg as Registers; - interface HplMsp430UsciIntA as Interrupts[uint8_t]; + interface HplMsp430UsciInt as Interrupts[uint8_t]; interface Resource as Resource[uint8_t]; interface ResourceRequested as ResourceRequested[uint8_t]; interface ArbiterInfo; } - uses interface ResourceConfig as ResourceConfig[uint8_t]; + uses interface ResourceConfigure as ResourceConfigure[uint8_t]; } implementation { - components new HplMsp430UsciRegP(UCB1CTL0_, UCB1CTL1_, UCB1BR0_, UCB1BR1_, - 0/*UCB1MCTL_*/, UCB1I2CIE_, UCB1STAT_, UCB1RXBUF_, UCB1TXBUF_, - 0/*UCB1ABCTL_*/, 0/*UCB1IRTCTL_*/, 0/*UCB1IRRCTL_*/, UCB1I2COA_, - UCB1I2CSA_, IE2_, IFG2_) as RegP; - Registers = RegP; - components new FcfsArbiterC(MSP430_USCIB1_RESOURCE) as ArbiterC; Resource = ArbiterC; ResourceRequested = ArbiterC; ResourceConfigure = ArbiterC; ArbiterInfo = ArbiterC; - components new Msp430UsciIntDispatchAP() as IntDispatchB1P; - Interrupts = IntDispatchB1P.IntAx; + components new Msp430UsciIntDispatchP() as IntDispatchB1P; + Interrupts = IntDispatchB1P; IntDispatchB1P.ArbiterInfo -> ArbiterC; - components HplMsp430UsciInt0C as Int0C; - IntDispatchB1P.RawIntAx -> Int0C.IntA; + components HplMsp430UsciC as UsciC; + Registers = UsciC.RegB1; + IntDispatchB1P.RawInt -> UsciC.IntB1; }