X-Git-Url: https://oss.titaniummirror.com/gitweb/?a=blobdiff_plain;f=tos%2Fplatforms%2Ftmicore%2FMoteClockP.nc;h=a3353972854fe9a639a7208464269bf4e733a28e;hb=33953a2e344b09fcd13b3bc53a421da4c51336d7;hp=1e141b45cafe3b150024d7a4891297734fcbb1d1;hpb=67ea6e597465286a923da75687454a88104bd6ef;p=tinyos-2.x.git diff --git a/tos/platforms/tmicore/MoteClockP.nc b/tos/platforms/tmicore/MoteClockP.nc index 1e141b45..a3353972 100644 --- a/tos/platforms/tmicore/MoteClockP.nc +++ b/tos/platforms/tmicore/MoteClockP.nc @@ -26,36 +26,51 @@ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ - + /** - * @author R. Steve McKown + * @author R. Steve McKown */ - + +#include "Msp430Timer.h" + module MoteClockP { provides interface Init; uses interface Init as SubInit; - } implementation { + MSP430REG_NORACE(TAIV); + MSP430REG_NORACE(TBIV); + command error_t Init.init() { - if (CALBC1_8MHZ != 0xff || CALDCO_8MHZ != 0xff) { - /* Initialize timers */ - TACTL = TASSEL_2 | TACLR | TAIE; - TAIV = 0; - TBCTL = TBSSEL_1 | TBCLR | TBIE; - TBIV = 0; + volatile uint16_t i; - /* Initialize DCO from calibrated data */ - BCSCTL1 = CALBC1_8MHZ; - DCOCTL = CALDCO_8MHZ; +#if defined (CALDCO_8MHZ_) && !defined(__DisableCalData) + if (CALBC1_8MHZ != 0xff || CALDCO_8MHZ != 0xff) { + /* Use built-in constant */ + atomic { + /* Initialize timers */ + TACTL = TASSEL_2 | TACLR | TAIE; + TAIV = 0; + TBCTL = TBSSEL_1 | TBCLR | TBIE; + TBIV = 0; - /* Turn on TimerB, aka the 32KHz clock */ - TBCTL |= MC1; + /* Initialize DCO from calibrated data. DCO = 8MHz. SMCLK = DCO/8 */ + BCSCTL1 = CALBC1_8MHZ; + BCSCTL2 = SELM_0 | DIVM_0 | DIVS_3; + DCOCTL = CALDCO_8MHZ; + /* Turn on timers A and B */ + TACTL |= MC_2; + TBCTL |= MC_2; + } return SUCCESS; - } else - return call SubInit.init(); + } +#endif + + /* Calibrate DCOCLK to ACLK when calibration data are disabled or erased */ + for (i = 0; i < 0xfffe; i++); /* ensure LFXT1 is stable */ + return call SubInit.init(); } }