X-Git-Url: https://oss.titaniummirror.com/gitweb/?a=blobdiff_plain;f=tos%2Fplatforms%2Ftmicore%2FMoteClockP.nc;h=a3353972854fe9a639a7208464269bf4e733a28e;hb=33953a2e344b09fcd13b3bc53a421da4c51336d7;hp=543aab467e4bc3800ffc1d5a500167a5dc61aa59;hpb=8ee154990c9e647f77ba3218b5d37774355b5ad8;p=tinyos-2.x.git diff --git a/tos/platforms/tmicore/MoteClockP.nc b/tos/platforms/tmicore/MoteClockP.nc index 543aab46..a3353972 100644 --- a/tos/platforms/tmicore/MoteClockP.nc +++ b/tos/platforms/tmicore/MoteClockP.nc @@ -26,30 +26,27 @@ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ - + /** - * @author R. Steve McKown + * @author R. Steve McKown */ - -//#include "msp430hardware.h" -#include "Msp430Timer.h" -#define MS430DCOSPEC_H -#define TARGET_DCO_KHZ 8192 // the target DCO clock rate in binary kHz -//#define TARGET_DCO_KHZ 4096 // the target DCO clock rate in binary kHz -#define ACLK_KHZ 32 // the ACLK rate in binary kHz +#include "Msp430Timer.h" module MoteClockP { provides interface Init; - uses { - interface Init as SubInit; - interface Msp430ClockInit; - } + uses interface Init as SubInit; } implementation { + MSP430REG_NORACE(TAIV); + MSP430REG_NORACE(TBIV); + command error_t Init.init() { + volatile uint16_t i; + +#if defined (CALDCO_8MHZ_) && !defined(__DisableCalData) if (CALBC1_8MHZ != 0xff || CALDCO_8MHZ != 0xff) { /* Use built-in constant */ atomic { @@ -64,38 +61,16 @@ implementation { BCSCTL2 = SELM_0 | DIVM_0 | DIVS_3; DCOCTL = CALDCO_8MHZ; - /* Turn on TimerB, aka the 32KHz clock */ - TBCTL |= MC1; + /* Turn on timers A and B */ + TACTL |= MC_2; + TBCTL |= MC_2; } return SUCCESS; - } else { - /* Constant not present; calibrate on the fly */ - int i; - - for (i = 0; i < 0xfffe; i++); /* ensure LFXT1 is stable */ - return call SubInit.init(); } - } - - event void Msp430ClockInit.setupDcoCalibrate() - { - call Msp430ClockInit.defaultSetupDcoCalibrate(); - } - - event void Msp430ClockInit.initClocks() - { - /* We run at 8MHz, so SMCLK divider needs to be /8 */ - call Msp430ClockInit.defaultInitClocks(); - BCSCTL2 |= DIVS_3; - } +#endif - event void Msp430ClockInit.initTimerA() - { - call Msp430ClockInit.defaultInitTimerA(); - } - - event void Msp430ClockInit.initTimerB() - { - call Msp430ClockInit.defaultInitTimerB(); + /* Calibrate DCOCLK to ACLK when calibration data are disabled or erased */ + for (i = 0; i < 0xfffe; i++); /* ensure LFXT1 is stable */ + return call SubInit.init(); } }