From: mmaroti <mmaroti>
Date: Thu, 24 Apr 2008 22:31:25 +0000 (+0000)
Subject: Allow possibly multiple slaves for the Atmega128 SPI bus.
X-Git-Tag: release_tinyos_2_1_0_0~450
X-Git-Url: https://oss.titaniummirror.com/gitweb/?a=commitdiff_plain;h=b3b5a0c4051c2ef8e6c27ac0750f5a1742a38452;p=tinyos-2.x.git

Allow possibly multiple slaves for the Atmega128 SPI bus.
Move the slave select logic from the HPL SPI to the user of the resouce.
This touched the MicaZ SPI access (but not the mica2 which uses its own logic)
---

diff --git a/tos/chips/atm128/spi/Atm128SpiC.nc b/tos/chips/atm128/spi/Atm128SpiC.nc
index 637232fd..c10a9f57 100644
--- a/tos/chips/atm128/spi/Atm128SpiC.nc
+++ b/tos/chips/atm128/spi/Atm128SpiC.nc
@@ -70,7 +70,6 @@ configuration Atm128SpiC {
 }
 implementation {
   components Atm128SpiP as SpiMaster, HplAtm128SpiC as HplSpi;
-  components HplAtm128GeneralIOC as IO;
   components new SimpleFcfsArbiterC("Atm128SpiC.Resource") as Arbiter;
   components McuSleepC;
   
@@ -81,7 +80,7 @@ implementation {
   Resource     = SpiMaster;
 
   SpiMaster.ResourceArbiter -> Arbiter;
-  SpiMaster.ArbiterInfo    -> Arbiter;
+  SpiMaster.ArbiterInfo     -> Arbiter;
   SpiMaster.Spi             -> HplSpi;
   SpiMaster.McuPowerState   -> McuSleepC;
 }
diff --git a/tos/chips/atm128/spi/Atm128SpiP.nc b/tos/chips/atm128/spi/Atm128SpiP.nc
index 1c94d692..da7f0629 100644
--- a/tos/chips/atm128/spi/Atm128SpiP.nc
+++ b/tos/chips/atm128/spi/Atm128SpiP.nc
@@ -101,7 +101,6 @@ implementation {
   command error_t Init.init() {
     return SUCCESS;
   }
-  bool started;
   
   void startSpi() {
     call Spi.enableSpi(FALSE);
@@ -119,7 +118,6 @@ implementation {
 
   void stopSpi() {
     call Spi.enableSpi(FALSE);
-    started = FALSE;
     atomic {
       call Spi.sleep();
     }
diff --git a/tos/chips/atm128/spi/HplAtm128SpiP.nc b/tos/chips/atm128/spi/HplAtm128SpiP.nc
index b29396d1..17c003f7 100644
--- a/tos/chips/atm128/spi/HplAtm128SpiP.nc
+++ b/tos/chips/atm128/spi/HplAtm128SpiP.nc
@@ -80,10 +80,9 @@ implementation {
     call MOSI.makeOutput();
     call MISO.makeInput();
     call SCK.makeOutput();
-    call SS.makeOutput();
     call SPI.setMasterBit(TRUE);
-    call SS.clr();
   }
+
   async command void SPI.initSlave() {
     call MISO.makeOutput();
     call MOSI.makeInput();
@@ -93,7 +92,7 @@ implementation {
   }
   
   async command void SPI.sleep() {
-    call SS.set();
+//    call SS.set();	// why was this needed?
   }
   
   async command uint8_t SPI.read()        { return SPDR; }
diff --git a/tos/chips/rf230/RF230LayerP.nc b/tos/chips/rf230/RF230LayerP.nc
index 153b9ee1..d9d06d5e 100644
--- a/tos/chips/rf230/RF230LayerP.nc
+++ b/tos/chips/rf230/RF230LayerP.nc
@@ -236,6 +236,7 @@ implementation
 	event void SpiResource.granted()
 	{
 		// TODO: this should not be here, see my comment in HplRF230C.nc
+		call SELN.makeOutput();
 		call SELN.set();
 
 		if( state == STATE_P_ON )
@@ -255,6 +256,7 @@ implementation
 		if( call SpiResource.immediateRequest() == SUCCESS )
 		{
 			// TODO: this should not be here, see my comment in HplRF230C.nc
+			call SELN.makeOutput();
 			call SELN.set();
 
 			return TRUE;
diff --git a/tos/platforms/iris/chips/rf230/HplRF230C.nc b/tos/platforms/iris/chips/rf230/HplRF230C.nc
index 113d47cd..91962f7e 100644
--- a/tos/platforms/iris/chips/rf230/HplRF230C.nc
+++ b/tos/platforms/iris/chips/rf230/HplRF230C.nc
@@ -49,8 +49,6 @@ implementation
 	HplRF230P.PortCLKM -> IO.PortD6;
 	HplRF230P.PortIRQ -> IO.PortD4;
 	
-	// TODO: Ask why the HplAtm128SpiC does SlaveSelect via PortB0
-	// TODO: Remove the unused started field from Atm128SpiP
 	components Atm128SpiC as SpiC;
 	SpiResource = SpiC.Resource[unique("Atm128SpiC.Resource")];
 	SpiByte = SpiC;
diff --git a/tos/platforms/micaz/chips/cc2420/HplCC2420SpiC.nc b/tos/platforms/micaz/chips/cc2420/HplCC2420SpiC.nc
index 03f283f5..2d92cafa 100644
--- a/tos/platforms/micaz/chips/cc2420/HplCC2420SpiC.nc
+++ b/tos/platforms/micaz/chips/cc2420/HplCC2420SpiC.nc
@@ -46,10 +46,12 @@ generic configuration HplCC2420SpiC() {
 
 implementation {
 
-  components Atm128SpiC;
+  components Atm128SpiC, HplCC2420SpiP, HplAtm128GeneralIOC as IO;
 
   Init = Atm128SpiC;
-  Resource = Atm128SpiC.Resource[ unique("Atm128SpiC.Resource") ];
+  Resource = HplCC2420SpiP;
+  HplCC2420SpiP.SubResource -> Atm128SpiC.Resource[ unique("Atm128SpiC.Resource") ];
+  HplCC2420SpiP.SS -> IO.PortB0;  // Slave set line
   SpiByte = Atm128SpiC;
   SpiPacket = Atm128SpiC;
 
diff --git a/tos/platforms/micaz/chips/cc2420/HplCC2420SpiP.nc b/tos/platforms/micaz/chips/cc2420/HplCC2420SpiP.nc
new file mode 100644
index 00000000..9b663179
--- /dev/null
+++ b/tos/platforms/micaz/chips/cc2420/HplCC2420SpiP.nc
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2005 Arch Rock Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the
+ *   distribution.
+ * - Neither the name of the Arch Rock Corporation nor the names of
+ *   its contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
+ * ARCHED ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE
+ */
+
+/**
+ * Automatic slave select update for the SpiResource
+ *
+ * @author Miklos Maroti
+ */
+
+module HplCC2420SpiP
+{
+	provides interface Resource;
+  
+	uses
+	{
+		interface Resource as SubResource;	// raw SPI resource
+		interface GeneralIO as SS;			// Slave set line
+	}
+}
+
+implementation
+{
+	async command error_t Resource.request()
+	{
+		return call SubResource.request();
+	}
+
+	async command error_t Resource.immediateRequest()
+	{
+		error_t error = call SubResource.immediateRequest();
+		if( error == SUCCESS )
+		{
+			call SS.makeOutput();
+			call SS.clr();
+		}
+		return error;
+	}
+
+	event void SubResource.granted()
+	{
+		call SS.makeOutput();
+		call SS.clr();
+
+		signal Resource.granted();
+	}
+	
+	async command error_t Resource.release()
+	{
+		if( call SubResource.isOwner() )
+			call SS.set();
+
+		return call SubResource.release();
+	}
+
+	async command bool Resource.isOwner()
+	{
+		return call SubResource.isOwner();
+	}
+}