From: kusy Date: Tue, 27 May 2008 17:44:42 +0000 (+0000) Subject: adding support for PXA27X Quick Capture X-Git-Tag: release_tinyos_2_1_0_0~370 X-Git-Url: https://oss.titaniummirror.com/gitweb/?a=commitdiff_plain;h=d774944cb95a418bea87471fb399c3e4cba39050;p=tinyos-2.x.git adding support for PXA27X Quick Capture --- diff --git a/tos/chips/pxa27x/cif/HplPXA27XQuickCaptInt.nc b/tos/chips/pxa27x/cif/HplPXA27XQuickCaptInt.nc new file mode 100644 index 00000000..f0c22a3d --- /dev/null +++ b/tos/chips/pxa27x/cif/HplPXA27XQuickCaptInt.nc @@ -0,0 +1,74 @@ +/* tab:4 + * IMPORTANT: READ BEFORE DOWNLOADING, COPYING, INSTALLING OR USING. By + * downloading, copying, installing or using the software you agree to + * this license. If you do not agree to this license, do not download, + * install, copy or use the software. + * + * Intel Open Source License + * + * Copyright (c) 2005 Intel Corporation + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * Neither the name of the Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL OR ITS + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** + * Description - PXA27X Quick Capture Interface. + * + * @author Konrad Lorincz + * @version 1.0, August 10, 2005 + */ +/** + * Modified and ported to tinyos-2.x. + * + * @author Brano Kusy + * @version October 25, 2007 + */ + +interface HplPXA27XQuickCaptInt +{ + command error_t init(uint8_t color); + command void enable(); + command error_t setImageSize(uint16_t sizeX, uint16_t sizeY, uint8_t colorType); + command void initDMA(uint32_t num_bytes, void *buf); + async command void disableQuick(); + async command void startDMA(); + + // Events/Interrupts + command void enableStartOfFrame(); + command void disableStartOfFrame(); /*new*/ + async event void startOfFrame(); + + command void enableEndOfFrame(); + async event void endOfFrame(); + + command void enableEndOfLine(); + async event void endOfLine(); + + command void enableRecvDataAvailable(); + async event void recvDataAvailable(uint8_t channel); + + command void enableFIFOOverrun(); + async event void fifoOverrun(uint8_t channel); +} diff --git a/tos/chips/pxa27x/cif/HplPXA27XQuickCaptIntC.nc b/tos/chips/pxa27x/cif/HplPXA27XQuickCaptIntC.nc new file mode 100644 index 00000000..b40e38d5 --- /dev/null +++ b/tos/chips/pxa27x/cif/HplPXA27XQuickCaptIntC.nc @@ -0,0 +1,74 @@ +/* tab:4 + * IMPORTANT: READ BEFORE DOWNLOADING, COPYING, INSTALLING OR USING. By + * downloading, copying, installing or using the software you agree to + * this license. If you do not agree to this license, do not download, + * install, copy or use the software. + * + * Intel Open Source License + * + * Copyright (c) 2005 Intel Corporation + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * Neither the name of the Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL OR ITS + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** + * Wiring for the PXA27X Quick Capture Interface. + * + * @author Konrad Lorincz + * @version 1.0 - September 10, 2005 + */ + /** + * Modified and ported to tinyos-2.x. + * + * @author Brano Kusy (branislav.kusy@gmail.com) + * @version October 25, 2007 + */ + +#include "PXA27XQuickCaptInt.h" + +configuration HplPXA27XQuickCaptIntC +{ + provides interface HplPXA27XQuickCaptInt; +} +implementation +{ + components HplPXA27XQuickCaptIntM; + HplPXA27XQuickCaptInt = HplPXA27XQuickCaptIntM; + + components HplPXA27xInterruptM; + HplPXA27XQuickCaptIntM.PPID_CIF_Irq -> HplPXA27xInterruptM.PXA27xIrq[PPID_CIF]; + + components HplPXA27xDMAC; + HplPXA27XQuickCaptIntM.pxa_dma -> HplPXA27xDMAC.HplPXA27xDMAChnl[CIF_CHAN]; + + components dmaArrayC; + HplPXA27XQuickCaptIntM.dmaArray -> dmaArrayC; + + components GeneralIOC; + HplPXA27XQuickCaptIntM.LED_PIN -> GeneralIOC.GeneralIO[106]; //A40-29 + + components LedsC; + HplPXA27XQuickCaptIntM.Leds -> LedsC; +} diff --git a/tos/chips/pxa27x/cif/HplPXA27XQuickCaptIntM.nc b/tos/chips/pxa27x/cif/HplPXA27XQuickCaptIntM.nc new file mode 100644 index 00000000..abfe1945 --- /dev/null +++ b/tos/chips/pxa27x/cif/HplPXA27XQuickCaptIntM.nc @@ -0,0 +1,322 @@ +/* tab:4 + * IMPORTANT: READ BEFORE DOWNLOADING, COPYING, INSTALLING OR USING. By + * downloading, copying, installing or using the software you agree to + * this license. If you do not agree to this license, do not download, + * install, copy or use the software. + * + * Intel Open Source License + * + * Copyright (c) 2005 Intel Corporation + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * Neither the name of the Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL OR ITS + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** + * Wiring for the PXA27X Quick Capture Interface. + * + * @author Konrad Lorincz + * @version 1.0 - September 10, 2005 + */ + /** + * Modified and ported to tinyos-2.x. + * + * @author Brano Kusy (branislav.kusy@gmail.com) + * @version October 25, 2007 + */ +#include "SCCB.h" +#include "OV7649.h" +#include "PXA27XQuickCaptInt.h" +#include "DMA.h" +#include "dmaArray.h" + +module HplPXA27XQuickCaptIntM +{ + provides interface HplPXA27XQuickCaptInt; + + uses interface HplPXA27xInterrupt as PPID_CIF_Irq; + uses interface Leds; + uses interface GeneralIO as LED_PIN; + uses interface dmaArray; + uses interface HplPXA27xDMAChnl as pxa_dma; +} +implementation +{ + + DescArray descArray; + void CIF_configurePins(); + + void CIF_init(uint8_t color){ + CIF_configurePins(); + + //atomic enabledInterrupts = 0; + + CKEN |= CKEN24_CIF; // enable the CIF clock + + call PPID_CIF_Irq.allocate(); // generate an CIF interrupt + call PPID_CIF_Irq.enable(); // enable the CIF interrupt mask + + // ------------------------------------------------------ + // (1) - Disable the CIF interface + call HplPXA27XQuickCaptInt.disableQuick(); + + // (2) - Set the timing/clocks + // a. Have the mote supply the MCLK to the camera sensor + CICR4 = CICR4_DIV(CICR4, 1); // Set the MCLK clock rate to 15 MHz + CICR4 |= CICR4_MCLK_EN; + //was: CICR4 = CICR4_DIV(CICR4, 2); // Set the MCLK clock rate to 15 MHz + // b. Have the camera suply the PCLK to the mote + CICR4 |= CICR4_PCLK_EN; + + // c. Set the synchronization signals to be active low + //was: CICR4 |= CICR4_HSP; // HREF is active-low? + //was: CICR4 |= CICR4_VSP; // VSYNC is active-low + // it seems we use active VSP and HSP + + // (3) - Set the data format (nbr pixels, color space, encoding, etc.) + //was: CICR1 = CICR1_DW(CICR1, 4); // Data Width: 10 bits wide data from the sensor + //was: CICR1 = CICR1_COLOR_SP(CICR1, 0); // Color Space: Raw + //was: CICR1 = CICR1_RAW_BPP(CICR1, 2); // Raw bits per pixel: 10 + //was: CICR3 = CICR3_LPF(CICR3, (1024-1)); // lines per frame (rows): 1024 + //was: CICR1 = CICR1_PPL(CICR1, (1280-1)); // pixels per line (cols): 1280 + CICR1 = CICR1_DW(CICR1, 2); // Data Width: 8 bits wide data from the sensor + CICR1 = CICR1_RGB_BPP(CICR1, 2); // RGB bits per pixel: 16 + CICR1 = CICR1_RAW_BPP(CICR1, 0); // RAW bits per pixel: 8 + CICR3 = CICR3_LPF(CICR3, (240-1)); // lines per frame (height): 240 + if (color == COLOR_RGB565) + { + CICR1 = CICR1_PPL(CICR1, (320-1)); // pixels per line (width): 320 + CICR1 = CICR1_COLOR_SP(CICR1, 1); // Color Space: RGB + } + else + { + CICR1 = CICR1_PPL(CICR1, (2*320-1)); // pixels per line (width): 320 + CICR1 = CICR1_COLOR_SP(CICR1, 0); // Color Space: RAW (default) + } + + // (4) - FIFO DMA threshold level + CIFR = CIFR_THL_0(CIFR, 0); // 96 bytes of more in FIFO 0 causea a DMA request + + // (5) - Initialize the DMA + //CIF_InitDMA(); + + // (6) - Enable the CIF with DMA + //was: CIF_setAndEnableCICR0(CICR0 | CICR0_DMA_EN); + + //new: all CICR0 bits should be set with a single command + CICR0 = ((CICR0 | CICR0_DMA_EN) & ~(CICR0_SOFM)) & ~(CICR0_EOFM); + } + + void CIF_setAndEnableCICR0(uint32_t data) + { + call HplPXA27XQuickCaptInt.disableQuick(); + CICR0 = (data | CICR0_EN); + } + + command error_t HplPXA27XQuickCaptInt.init(uint8_t color) + { + CIF_init(color); + return SUCCESS; + } + + command void HplPXA27XQuickCaptInt.enable() + { + uint32_t tempCICR0 = CICR0; + tempCICR0 |= CICR0_EN; + tempCICR0 &= ~(CICR0_DIS); //new + CICR0 = tempCICR0; + } + + async command void HplPXA27XQuickCaptInt.disableQuick() + { + led_clr();//call LED_PIN.clr(); + CICR0 &= ~(CICR0_EN); + CISR |= CISR_CQD; + } + + async command void HplPXA27XQuickCaptInt.startDMA() + { + atomic{ + uint32_t dcsr = call pxa_dma.getDCSR(); + + call pxa_dma.setMap(DMAREQ_CIF_RECV_0); + call pxa_dma.setDALGNbit(1); + dcsr &= ~(DCSR_RUN); + dcsr &= ~(DCSR_NODESCFETCH); + call pxa_dma.setDCSR(dcsr); + call pxa_dma.setDDADR((uint32_t)call dmaArray.array_get(&descArray, 0) ); + call pxa_dma.setDCSR((call pxa_dma.getDCSR()) | DCSR_RUN ); + } + } + + command error_t HplPXA27XQuickCaptInt.setImageSize(uint16_t sizeX, uint16_t sizeY, uint8_t colorType) + { + //was: if (sizeX > 2048 || sizeY > 2048) + if (sizeX > 320 || sizeY > 240) + return FAIL; + + + + // (1) - Set the Quick Capture Interface Size + //was: call HplPXA27XQuickCaptInt.disableQuick(); + CICR3 = CICR3_LPF(CICR3, (sizeY-1)); + //was: CICR1 = CICR1_PPL(CICR1, (sizeX-1)); + if (colorType == COLOR_RGB565) + CICR1 = CICR1_PPL(CICR1, (sizeX-1)); + else + CICR1 = CICR1_PPL(CICR1, (2*sizeX-1)); + + //was: call HplPXA27XQuickCaptInt.enable(); + + // (2) - Set the DMA transfer size + //was: nbrBytesToTransfer = sizeX*sizeY*2; // each pixel is 2 bytes + + return SUCCESS; + } + + command void HplPXA27XQuickCaptInt.initDMA(uint32_t num_bytes, void *buf) //CIF_InitDMA() + { + call dmaArray.init(&descArray, num_bytes, CIBR0_ADDR, buf); + } + + command void HplPXA27XQuickCaptInt.disableStartOfFrame() {CIF_setAndEnableCICR0(CICR0 | CICR0_SOFM);} + command void HplPXA27XQuickCaptInt.enableStartOfFrame() {CIF_setAndEnableCICR0(CICR0 & ~(CICR0_SOFM));} + command void HplPXA27XQuickCaptInt.enableEndOfFrame() {CIF_setAndEnableCICR0(CICR0 & ~(CICR0_EOFM));} + command void HplPXA27XQuickCaptInt.enableEndOfLine() {CIF_setAndEnableCICR0(CICR0 & ~(CICR0_EOLM));} + command void HplPXA27XQuickCaptInt.enableRecvDataAvailable() {CIF_setAndEnableCICR0(CICR0 & ~(CICR0_RDAVM));} + command void HplPXA27XQuickCaptInt.enableFIFOOverrun() {CIF_setAndEnableCICR0(CICR0 & ~(CICR0_FOM));} + + default async event void HplPXA27XQuickCaptInt.startOfFrame() { return;} + default async event void HplPXA27XQuickCaptInt.endOfFrame() { return;} + default async event void HplPXA27XQuickCaptInt.endOfLine() { return;} + default async event void HplPXA27XQuickCaptInt.recvDataAvailable(uint8_t channel) { return;} + default async event void HplPXA27XQuickCaptInt.fifoOverrun(uint8_t channel) { return;} + + async event void PPID_CIF_Irq.fired() + { + + //atomic{printfUART(">>>>>>>>>>>>>>> PPID_CIF_Irq.fired() >>>>>>>>>>>\n", "");} + volatile uint32_t tempCISR; + call Leds.led0Toggle(); + + atomic { tempCISR = CISR; } + // Start-Of-Frame + if ((tempCISR & CISR_SOF) && (~(CICR0) & CICR0_SOFM)) { + atomic CISR |= CISR_SOF; + led_set();//call LED_PIN.set(); + signal HplPXA27XQuickCaptInt.startOfFrame(); + // this disables CIF after the current frame capture is done + CICR0 |= CICR0_DIS; + } + // End-Of-Frame + if ((tempCISR & CISR_EOF) && (~(CICR0) & CICR0_EOFM)) { + atomic CISR |= CISR_EOF; + led_clr();//call LED_PIN.clr(); + signal HplPXA27XQuickCaptInt.endOfFrame(); + return; + } + // End-Of-Line + if ((tempCISR & CISR_EOL) && (~(CICR0) & CICR0_EOLM)) { + atomic CISR |= CISR_EOL; + signal HplPXA27XQuickCaptInt.endOfLine(); + } + // Receive-Data-Available + if (~(CICR0) & CICR0_RDAVM) { + if (tempCISR & CISR_RDAV_2) { // channel 2 + atomic CISR |= CISR_RDAV_2; + signal HplPXA27XQuickCaptInt.recvDataAvailable(2); + } + if (tempCISR & CISR_RDAV_1) { // channel 1 + atomic CISR |= CISR_RDAV_1; + signal HplPXA27XQuickCaptInt.recvDataAvailable(1); + } + if (tempCISR & CISR_RDAV_0) { // channel 0 + atomic CISR |= CISR_RDAV_0; + signal HplPXA27XQuickCaptInt.recvDataAvailable(0); + } + } + // FIFO Overrun + if (~(CICR0) & CICR0_FOM) { + if (tempCISR & CISR_IFO_2) { // channel 2 + atomic CISR |= CISR_IFO_2; + signal HplPXA27XQuickCaptInt.fifoOverrun(2); + } + if (tempCISR & CISR_IFO_1) { // channel 1 + atomic CISR |= CISR_IFO_1; + signal HplPXA27XQuickCaptInt.fifoOverrun(1); + } + if (tempCISR & CISR_IFO_0) { // channel 0 + atomic CISR |= CISR_IFO_0; + signal HplPXA27XQuickCaptInt.fifoOverrun(0); + } + } + + } + + void CIF_configurePins() + { + // (1) - Configure the GPIO Alt functions and direction + // --- Template ---- + //_GPIO_setaltfn(PIN, PIN_ALTFN); + //_GPDR(PIN) &= ~_GPIO_bit(PIN); // input + //_GPDR(PIN) |= _GPIO_bit(PIN); // output + // ----------------- + + + _GPIO_setaltfn(PIN_CIF_MCLK, PIN_CIF_MCLK_ALTFN); + _GPIO_setaltfn(PIN_CIF_PCLK, PIN_CIF_PCLK_ALTFN); + _GPIO_setaltfn(PIN_CIF_FV, PIN_CIF_FV_ALTFN); + _GPIO_setaltfn(PIN_CIF_LV, PIN_CIF_LV_ALTFN); + + _GPIO_setaltfn(PIN_CIF_DD0, PIN_CIF_DD0_ALTFN); + _GPIO_setaltfn(PIN_CIF_DD1, PIN_CIF_DD1_ALTFN); + _GPIO_setaltfn(PIN_CIF_DD2, PIN_CIF_DD2_ALTFN); + _GPIO_setaltfn(PIN_CIF_DD3, PIN_CIF_DD3_ALTFN); + _GPIO_setaltfn(PIN_CIF_DD4, PIN_CIF_DD4_ALTFN); + _GPIO_setaltfn(PIN_CIF_DD5, PIN_CIF_DD5_ALTFN); + _GPIO_setaltfn(PIN_CIF_DD6, PIN_CIF_DD6_ALTFN); + _GPIO_setaltfn(PIN_CIF_DD7, PIN_CIF_DD7_ALTFN); + + GPDR(PIN_CIF_MCLK) |= _GPIO_bit(PIN_CIF_MCLK); // output (if sensor is master) + GPDR(PIN_CIF_PCLK) &= ~_GPIO_bit(PIN_CIF_PCLK); // input (if sensor is master) + GPDR(PIN_CIF_FV) &= ~_GPIO_bit(PIN_CIF_FV); // input (if sensor is master) + GPDR(PIN_CIF_LV) &= ~_GPIO_bit(PIN_CIF_LV); // input (if sensor is master) + GPDR(PIN_CIF_DD0) &= ~_GPIO_bit(PIN_CIF_DD0); // input + GPDR(PIN_CIF_DD1) &= ~_GPIO_bit(PIN_CIF_DD1); // input + GPDR(PIN_CIF_DD2) &= ~_GPIO_bit(PIN_CIF_DD2); // input + GPDR(PIN_CIF_DD3) &= ~_GPIO_bit(PIN_CIF_DD3); // input + GPDR(PIN_CIF_DD4) &= ~_GPIO_bit(PIN_CIF_DD4); // input + GPDR(PIN_CIF_DD5) &= ~_GPIO_bit(PIN_CIF_DD5); // input + GPDR(PIN_CIF_DD6) &= ~_GPIO_bit(PIN_CIF_DD6); // input + GPDR(PIN_CIF_DD7) &= ~_GPIO_bit(PIN_CIF_DD7); // input + } + + async event void pxa_dma.interruptDMA(){ + call pxa_dma.setDCMD(0); + call pxa_dma.setDCSR(DCSR_EORINT | DCSR_ENDINTR + | DCSR_STARTINTR | DCSR_BUSERRINTR); + } + +} + diff --git a/tos/chips/pxa27x/cif/PXA27XQuickCaptInt.h b/tos/chips/pxa27x/cif/PXA27XQuickCaptInt.h new file mode 100644 index 00000000..1e10bb9e --- /dev/null +++ b/tos/chips/pxa27x/cif/PXA27XQuickCaptInt.h @@ -0,0 +1,113 @@ +/* tab:4 + * IMPORTANT: READ BEFORE DOWNLOADING, COPYING, INSTALLING OR USING. By + * downloading, copying, installing or using the software you agree to + * this license. If you do not agree to this license, do not download, + * install, copy or use the software. + * + * Intel Open Source License + * + * Copyright (c) 2005 Intel Corporation + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * Neither the name of the Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL OR ITS + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** + * @author Konrad Lorincz + * @version 1.0, August 15, 2005 + */ +/** + * @brief Ported to TOS2 + * @author Brano Kusy (branislav.kusy@gmail.com) + */ +#ifndef PXA27XQuickCaptInt_H +#define PXA27XQuickCaptInt_H + +/******************************************************************************/ +/* Configure the GPIO Alt functions and directions +/* Note: +/* - In Sensor Master-Parallel mode, CIF_FV and CIF_LV are set to INPUTS +/* - In Sensor Slave-Parallel mode, CIF_FV and CIF_LV are set to OUTPUTS +// Configure the GPIO Alt Functions and Directions +// --- Template ---- +// _GPIO_setaltfn(PIN, PIN_ALTFN); +// _GPDR(PIN) &= ~_GPIO_bit(PIN); // input +// _GPDR(PIN) |= _GPIO_bit(PIN); // output +// ----------------- +/******************************************************************************/ + +// (1) - Define the Pin mappings (options are listed as +#define PIN_CIF_MCLK 53 // <23,O,1> <42,O,3> <53,O,2> +#define PIN_CIF_MCLK_ALTFN 2 +#define PIN_CIF_PCLK 54 // <26,I,2> <45,I,3> <54,I,3> +#define PIN_CIF_PCLK_ALTFN 3 +#define PIN_CIF_FV 84 // <24,I,1> <24,O,1> <43,I,3> <43,O,3> <84,I,3> <84,O,3> +#define PIN_CIF_FV_ALTFN 3 +#define PIN_CIF_LV 85 // <25,I,1> <25,O,1> <44,I,3> <44,O,3> <85,I,3> <85,O,3> +#define PIN_CIF_LV_ALTFN 3 + +#define PIN_CIF_DD0 81 // <27,I,3> <47,I,1> <81,I,2> <98,I,2> +#define PIN_CIF_DD0_ALTFN 2 // SSPEXTCLK STD_TXD BB_OB_DAT0 FF_RTS + // CIF_DD0 KP_DKIN5 + // GPIO27_LED_B +#define PIN_CIF_DD1 55 // <55,I,1> <105,I,1> <114*,I,1> +#define PIN_CIF_DD1_ALTFN 1 // BB_IB_DAT1 KP_MKOUT2 CC2420_FIFO + // NPREG UVS0 + +#define PIN_CIF_DD2 51 // <51,I,1> <104,I,1> <116*,I,1> +#define PIN_CIF_DD2_ALTFN 1 // BB_OB_DAT3 KP_MKOUT1 CC2420_CCA + // U_DET + +#define PIN_CIF_DD3 50 // <50,I,1> <103,I,1> <115*,I,2> +#define PIN_CIF_DD3_ALTFN 1 // BB_OB_DAT2 KP_MKOUT0 CC2420_VREG_EN + // NPIOR U_EN + +#define PIN_CIF_DD4 52 // <52,I,1> <83,I,3> <90,I,3> <95,I,2> +#define PIN_CIF_DD4_ALTFN 1 // BB_OB_CLK BB_IB_CLK NURST KP_DKIN2 + // GPIO95_LED_R + +#define PIN_CIF_DD5 48 // <48,I,1> <82,I,3> <91,I,3> <94,I,2> +#define PIN_CIF_DD5_ALTFN 1 // BB_OB_DAT1 BB_IB_DAT0 UCLK KP_DKIN1 + // GPIO94_D_CARD + +#define PIN_CIF_DD6 17 // <17,I,2> <93,I,2> +#define PIN_CIF_DD6_ALTFN 2 // CIF_DD6 KP_DKIN0 + // PWM_OUT_1 GPIO93_D_CARD + +#define PIN_CIF_DD7 12 // <12,I,2> <108,I,1> +#define PIN_CIF_DD7_ALTFN 2 // CIF_DD7 KP_MKOUT5 + // 48MHz + +//#define PIN_CIF_DD8 107 // <107,I,1> +//#define PIN_CIF_DD8_ALTFN 1 // CIF_DD8 +// KP_MKOUT4 +//#define PIN_CIF_DD9 106 // <106,I,1> +//#define PIN_CIF_DD9_ALTFN 1 // CIF_DD9 + +// =================================================================== +#define CIF_CHAN (11) +#define CIBR0_ADDR (0x50000028) +#define CICR0_DIS (1 << 27) /* Quick Capture Interface Disable */ + +#endif diff --git a/tos/chips/pxa27x/cif/dmaArray.h b/tos/chips/pxa27x/cif/dmaArray.h new file mode 100644 index 00000000..d501b665 --- /dev/null +++ b/tos/chips/pxa27x/cif/dmaArray.h @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2005 Yale University. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * 3. All advertising materials mentioning features or use of this + * software must display the following acknowledgement: + * This product includes software developed by the Embedded Networks + * and Applications Lab (ENALAB) at Yale University. + * 4. Neither the name of the University nor that of the Laboratory + * may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY YALE UNIVERSITY AND CONTRIBUTORS ``AS IS'' + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ + /** + * @brief dma array operations + * @author Andrew Barton-Sweeney (abs@cs.yale.edu) + * @author Thiago Teixeira + */ + /** + * Modified and ported to tinyos-2.x. + * + * @author Brano Kusy (branislav.kusy@gmail.com) + * @version October 25, 2007 + */ +#ifndef _DMA_ARRAY_H +#define _DMA_ARRAY_H + +typedef struct { + uint32_t DDADR; + uint32_t DSADR; + uint32_t DTADR; + uint32_t DCMD; +} DMADescriptor_t; + + +#define MAX_DESC_TRANSFER 8184 // max is 8K-1, CIF requires a multiple of 8 //8192 + +// ---------------------------------------------- +#define DescArray_NBR_DESC 20//8 +#define DescArray_BYTE_ALLIGNMENT 16 +#define DescArray_BUFFER_SIZE (DescArray_NBR_DESC*sizeof(DMADescriptor_t) + DescArray_BYTE_ALLIGNMENT) + +typedef struct DescArray +{ + uint8_t data[DescArray_BUFFER_SIZE]; // The data is alligned from data[baseIndex] +} DescArray; + +#endif //_DMA_ARRAY_H diff --git a/tos/chips/pxa27x/cif/dmaArray.nc b/tos/chips/pxa27x/cif/dmaArray.nc new file mode 100644 index 00000000..118b85ee --- /dev/null +++ b/tos/chips/pxa27x/cif/dmaArray.nc @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2005 Yale University. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * 3. All advertising materials mentioning features or use of this + * software must display the following acknowledgement: + * This product includes software developed by the Embedded Networks + * and Applications Lab (ENALAB) at Yale University. + * 4. Neither the name of the University nor that of the Laboratory + * may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY YALE UNIVERSITY AND CONTRIBUTORS ``AS IS'' + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ + /** + * @brief dma array operations + * @author Andrew Barton-Sweeney (abs@cs.yale.edu) + * @author Thiago Teixeira + */ + /** + * Modified and ported to tinyos-2.x. + * + * @author Brano Kusy (branislav.kusy@gmail.com) + * @version October 25, 2007 + */ +#include "DMA.h" + +interface dmaArray{ + async command uint32_t array_getBaseIndex(DescArray *DAPtr); + async command DMADescriptor_t* array_get(DescArray *DAPtr, uint8_t descIndex); + command void init(DescArray *DAPtr, uint32_t num_bytes, uint32_t sourceAddr, void *buf); + command void setSourceAddr(DMADescriptor_t* descPtr, uint32_t val); + command void setTargetAddr(DMADescriptor_t* descPtr, uint32_t val); + command void enableSourceAddrIncrement(DMADescriptor_t* descPtr, bool enable); + command void enableTargetAddrIncrement(DMADescriptor_t* descPtr, bool enable); + command void enableSourceFlowControl(DMADescriptor_t* descPtr, bool enable); + command void enableTargetFlowControl(DMADescriptor_t* descPtr, bool enable); + command void setMaxBurstSize(DMADescriptor_t* descPtr, DMAMaxBurstSize_t size); + command void setTransferLength(DMADescriptor_t* descPtr, uint16_t length); + command void setTransferWidth(DMADescriptor_t* descPtr, DMATransferWidth_t width); +} diff --git a/tos/chips/pxa27x/cif/dmaArrayC.nc b/tos/chips/pxa27x/cif/dmaArrayC.nc new file mode 100644 index 00000000..f4bbeb1a --- /dev/null +++ b/tos/chips/pxa27x/cif/dmaArrayC.nc @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2005 Yale University. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * 3. All advertising materials mentioning features or use of this + * software must display the following acknowledgement: + * This product includes software developed by the Embedded Networks + * and Applications Lab (ENALAB) at Yale University. + * 4. Neither the name of the University nor that of the Laboratory + * may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY YALE UNIVERSITY AND CONTRIBUTORS ``AS IS'' + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ + /** + * @brief dma array operations + * @author Andrew Barton-Sweeney (abs@cs.yale.edu) + * @author Thiago Teixeira + */ + /** + * Modified and ported to tinyos-2.x. + * + * @author Brano Kusy (branislav.kusy@gmail.com) + * @version October 25, 2007 + */ +configuration dmaArrayC{ + provides interface dmaArray; +} + +implementation +{ + components dmaArrayM; + dmaArray = dmaArrayM; +} diff --git a/tos/chips/pxa27x/cif/dmaArrayM.nc b/tos/chips/pxa27x/cif/dmaArrayM.nc new file mode 100644 index 00000000..8d5ba1e6 --- /dev/null +++ b/tos/chips/pxa27x/cif/dmaArrayM.nc @@ -0,0 +1,169 @@ +/* + * Copyright (c) 2005 Yale University. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * 3. All advertising materials mentioning features or use of this + * software must display the following acknowledgement: + * This product includes software developed by the Embedded Networks + * and Applications Lab (ENALAB) at Yale University. + * 4. Neither the name of the University nor that of the Laboratory + * may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY YALE UNIVERSITY AND CONTRIBUTORS ``AS IS'' + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ + /** + * @brief dma array operations + * @author Andrew Barton-Sweeney (abs@cs.yale.edu) + * @author Thiago Teixeira + */ + /** + * Modified and ported to tinyos-2.x. + * + * @author Brano Kusy (branislav.kusy@gmail.com) + * @version October 25, 2007 + */ + +module dmaArrayM{ + provides interface dmaArray; +} + +implementation +{ + async command uint32_t dmaArray.array_getBaseIndex(DescArray *DAPtr) + { + uint32_t addr = (uint32_t) (&DAPtr->data[0]); + return DescArray_BYTE_ALLIGNMENT - (addr % DescArray_BYTE_ALLIGNMENT); + } + + async command DMADescriptor_t* dmaArray.array_get(DescArray *DAPtr, uint8_t descIndex) + { + uint32_t baseIndex = call dmaArray.array_getBaseIndex(DAPtr); + return (DMADescriptor_t*)&DAPtr->data[baseIndex + descIndex*sizeof(DMADescriptor_t)]; + } + + command void dmaArray.init(DescArray *DAPtr, + uint32_t num_bytes, + uint32_t sourceAddr, + void *buf) + { + uint8_t i = 0; + DMADescriptor_t* descPtr = NULL; + //was: uint32_t bytesLeftToSchedule = nbrBytesToTransfer; + uint32_t bytesLeftToSchedule = num_bytes; + uint32_t image_data = (uint32_t) buf; + + for (i = 0; bytesLeftToSchedule > 0; ++i) { + descPtr = call dmaArray.array_get(DAPtr, i); + + call dmaArray.setSourceAddr(descPtr, sourceAddr); + //was: call dmaArray.setTargetAddr(descPtr, &image.data[ i*(MAX_DESC_TRANSFER/4) ]); + call dmaArray.setTargetAddr(descPtr, image_data + i*MAX_DESC_TRANSFER ); + call dmaArray.enableSourceAddrIncrement(descPtr, FALSE); + call dmaArray.enableTargetAddrIncrement(descPtr, TRUE); + call dmaArray.enableSourceFlowControl(descPtr, TRUE); + call dmaArray.enableTargetFlowControl(descPtr, FALSE); + call dmaArray.setMaxBurstSize(descPtr, 3); // burst size: can be 8, 16, or 32 bytes + call dmaArray.setTransferWidth(descPtr, 3); // peripheral width for DMA transactions from CIF is always 8-bytes, regardless of DCMD[WIDTH] + + if (bytesLeftToSchedule >= MAX_DESC_TRANSFER) { + call dmaArray.setTransferLength(descPtr, MAX_DESC_TRANSFER); // 16*8 *2 =256 bytes // must be an integer multiple of 8-bytes + bytesLeftToSchedule -= MAX_DESC_TRANSFER; + } + else { + call dmaArray.setTransferLength(descPtr, bytesLeftToSchedule); + bytesLeftToSchedule = 0; + } + + // continue running the next descriptor + descPtr->DDADR = (uint32_t)call dmaArray.array_get(DAPtr, i+1); + } + + // Set the stop bit for the last descriptor + descPtr->DDADR |= DDADR_STOP; + } + + command void dmaArray.setSourceAddr(DMADescriptor_t* descPtr, uint32_t val) + { + atomic{ descPtr->DSADR = val; } + } + + command void dmaArray.setTargetAddr(DMADescriptor_t* descPtr, uint32_t val) + { + atomic{ descPtr->DTADR = val; } + } + + command void dmaArray.enableSourceAddrIncrement(DMADescriptor_t* descPtr, bool enable) + { + atomic{ descPtr->DCMD = (enable == TRUE) ? descPtr->DCMD | DCMD_INCSRCADDR : descPtr->DCMD & ~DCMD_INCSRCADDR; } + } + + command void dmaArray.enableTargetAddrIncrement(DMADescriptor_t* descPtr, bool enable) + { + atomic{ descPtr->DCMD = (enable == TRUE) ? descPtr->DCMD | DCMD_INCTRGADDR : descPtr->DCMD & ~DCMD_INCTRGADDR; } + } + + command void dmaArray.enableSourceFlowControl(DMADescriptor_t* descPtr, bool enable) + { + atomic{descPtr->DCMD = (enable == TRUE) ? descPtr->DCMD | DCMD_FLOWSRC : descPtr->DCMD & ~DCMD_FLOWSRC;} + } + + command void dmaArray.enableTargetFlowControl(DMADescriptor_t* descPtr, bool enable) + { + atomic{descPtr->DCMD = (enable == TRUE) ? descPtr->DCMD | DCMD_FLOWTRG : descPtr->DCMD & ~DCMD_FLOWTRG;} + } + + command void dmaArray.setMaxBurstSize(DMADescriptor_t* descPtr, DMAMaxBurstSize_t size) + { + if(size >= DMA_BURST_SIZE_8BYTES && size <= DMA_BURST_SIZE_32BYTES){ + //if(size >= DMA_BURST_SIZE_8BYTES && size <= DMA_BURST_SIZE_32BYTES){ + atomic{ + //clear it out since otherwise |'ing doesn't work so well + descPtr->DCMD &= ~DCMD_MAXSIZE; + descPtr->DCMD |= DCMD_SIZE(size); + } + } + } + + command void dmaArray.setTransferLength(DMADescriptor_t* descPtr, uint16_t length) + { + uint16_t currentLength; + currentLength = (length < MAX_DESC_TRANSFER) ? length : MAX_DESC_TRANSFER; + //was: currentLength = (length<8192) ? length: 8190; + atomic{ + descPtr->DCMD &= ~DCMD_MAXLEN; + descPtr->DCMD |= DCMD_LEN(currentLength); + } + } + + command void dmaArray.setTransferWidth(DMADescriptor_t* descPtr, DMATransferWidth_t width) + { + atomic{ + //clear it out since otherwise |'ing doesn't work so well + descPtr->DCMD &= ~DCMD_MAXWIDTH; + descPtr->DCMD |= DCMD_WIDTH(width); + } + } + +}