From 22eeed6c393c90c733ea4c85e852dc3d8a5365f9 Mon Sep 17 00:00:00 2001 From: r-studio Date: Mon, 7 Sep 2009 14:12:25 +0000 Subject: [PATCH] mulle files --- tos/chips/m16c62p/McuSleepC.nc | 59 + tos/chips/m16c62p/McuSleepP.nc | 66 + tos/chips/m16c62p/adc/Adc.h | 23 + tos/chips/m16c62p/adc/AdcP.nc | 151 + tos/chips/m16c62p/adc/AdcReadClientC.nc | 40 + tos/chips/m16c62p/adc/AdcReadNowClientC.nc | 43 + tos/chips/m16c62p/adc/AdcReadStreamClientC.nc | 40 + tos/chips/m16c62p/adc/AdcStreamP.nc | 270 ++ tos/chips/m16c62p/adc/HplM16c62pAdc.nc | 165 + tos/chips/m16c62p/adc/HplM16c62pAdcC.nc | 43 + tos/chips/m16c62p/adc/HplM16c62pAdcP.nc | 160 + tos/chips/m16c62p/adc/M16c62pAdc.h | 168 + tos/chips/m16c62p/adc/M16c62pAdcC.nc | 69 + tos/chips/m16c62p/adc/M16c62pAdcConfig.nc | 42 + tos/chips/m16c62p/adc/M16c62pAdcMultiple.nc | 119 + tos/chips/m16c62p/adc/M16c62pAdcP.nc | 220 ++ tos/chips/m16c62p/adc/M16c62pAdcSingle.nc | 81 + tos/chips/m16c62p/adc/WireAdcP.nc | 37 + tos/chips/m16c62p/adc/WireAdcStreamP.nc | 40 + tos/chips/m16c62p/bits.h | 74 + tos/chips/m16c62p/interrupts.h | 127 + tos/chips/m16c62p/iom16c62p.h | 2757 +++++++++++++++++ tos/chips/m16c62p/m16c62phardware.h | 150 + 23 files changed, 4944 insertions(+) create mode 100755 tos/chips/m16c62p/McuSleepC.nc create mode 100755 tos/chips/m16c62p/McuSleepP.nc create mode 100755 tos/chips/m16c62p/adc/Adc.h create mode 100755 tos/chips/m16c62p/adc/AdcP.nc create mode 100755 tos/chips/m16c62p/adc/AdcReadClientC.nc create mode 100755 tos/chips/m16c62p/adc/AdcReadNowClientC.nc create mode 100755 tos/chips/m16c62p/adc/AdcReadStreamClientC.nc create mode 100755 tos/chips/m16c62p/adc/AdcStreamP.nc create mode 100755 tos/chips/m16c62p/adc/HplM16c62pAdc.nc create mode 100755 tos/chips/m16c62p/adc/HplM16c62pAdcC.nc create mode 100755 tos/chips/m16c62p/adc/HplM16c62pAdcP.nc create mode 100755 tos/chips/m16c62p/adc/M16c62pAdc.h create mode 100755 tos/chips/m16c62p/adc/M16c62pAdcC.nc create mode 100755 tos/chips/m16c62p/adc/M16c62pAdcConfig.nc create mode 100755 tos/chips/m16c62p/adc/M16c62pAdcMultiple.nc create mode 100755 tos/chips/m16c62p/adc/M16c62pAdcP.nc create mode 100755 tos/chips/m16c62p/adc/M16c62pAdcSingle.nc create mode 100755 tos/chips/m16c62p/adc/WireAdcP.nc create mode 100755 tos/chips/m16c62p/adc/WireAdcStreamP.nc create mode 100755 tos/chips/m16c62p/bits.h create mode 100755 tos/chips/m16c62p/interrupts.h create mode 100755 tos/chips/m16c62p/iom16c62p.h create mode 100755 tos/chips/m16c62p/m16c62phardware.h diff --git a/tos/chips/m16c62p/McuSleepC.nc b/tos/chips/m16c62p/McuSleepC.nc new file mode 100755 index 00000000..864cca1d --- /dev/null +++ b/tos/chips/m16c62p/McuSleepC.nc @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2009 Communication Group and Eislab at + * Lulea University of Technology + * + * Contact: Laurynas Riliskis, LTU + * Mail: laurynas.riliskis@ltu.se + * All rights reserved. + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * - Neither the name of Communication Group at Lulea University of Technology + * nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL STANFORD + * UNIVERSITY OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED + * OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + * Wiring of TEP 112 (Microcontroller Power Management). + * + * @author Henrik Makitaavola + */ + +configuration McuSleepC +{ + provides interface McuSleep; + provides interface McuPowerState; + + uses interface McuPowerOverride; +} +implementation +{ + components McuSleepP, + M16c62pControlC; + + McuSleep = McuSleepP; + McuPowerState = McuSleepP; + McuSleepP = McuPowerOverride; + McuSleepP.M16c62pControl -> M16c62pControlC; +} diff --git a/tos/chips/m16c62p/McuSleepP.nc b/tos/chips/m16c62p/McuSleepP.nc new file mode 100755 index 00000000..3dffaf8c --- /dev/null +++ b/tos/chips/m16c62p/McuSleepP.nc @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2009 Communication Group and Eislab at + * Lulea University of Technology + * + * Contact: Laurynas Riliskis, LTU + * Mail: laurynas.riliskis@ltu.se + * All rights reserved. + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * - Neither the name of Communication Group at Lulea University of Technology + * nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL STANFORD + * UNIVERSITY OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED + * OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + * Implementation of TEP 112 (Microcontroller Power Management). + * + * @author Henrik Makitaavola + */ + +module McuSleepP +{ + provides interface McuSleep; + provides interface McuPowerState; + + uses interface McuPowerOverride; + uses interface M16c62pControl; +} +implementation +{ + async command void McuSleep.sleep() + { + call M16c62pControl.sleep(); + } + + async command void McuPowerState.update() + { + } + + default async command mcu_power_t McuPowerOverride.lowestState() + { + return M16C62P_POWER_STOP; + } +} diff --git a/tos/chips/m16c62p/adc/Adc.h b/tos/chips/m16c62p/adc/Adc.h new file mode 100755 index 00000000..5b87118a --- /dev/null +++ b/tos/chips/m16c62p/adc/Adc.h @@ -0,0 +1,23 @@ +/* $Id$ + * Copyright (c) 2005 Intel Corporation + * All rights reserved. + * + * This file is distributed under the terms in the attached INTEL-LICENSE + * file. If you do not find these files, copies can be found by writing to + * Intel Research Berkeley, 2150 Shattuck Avenue, Suite 1300, Berkeley, CA, + * 94704. Attention: Intel License Inquiry. + */ +/* + * @author David Gay + */ +#ifndef __ADC_H__ +#define __ADC_H__ + +#include "M16c62pAdc.h" + +/* Read and ReadNow share client ids */ +#define UQ_ADC_READ "adc.read" +#define UQ_ADC_READNOW UQ_ADC_READ +#define UQ_ADC_READSTREAM "adc.readstream" + +#endif // __ADC_H__ diff --git a/tos/chips/m16c62p/adc/AdcP.nc b/tos/chips/m16c62p/adc/AdcP.nc new file mode 100755 index 00000000..d456c3e1 --- /dev/null +++ b/tos/chips/m16c62p/adc/AdcP.nc @@ -0,0 +1,151 @@ +/* $Id$ + * Copyright (c) 2005 Intel Corporation + * All rights reserved. + * + * This file is distributed under the terms in the attached INTEL-LICENSE + * file. If you do not find these files, copies can be found by writing to + * Intel Research Berkeley, 2150 Shattuck Avenue, Suite 1300, Berkeley, CA, + * 94704. Attention: Intel License Inquiry. + * + * Copyright (c) 2004, Technische Universitaet Berlin + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of the Technische Universitaet Berlin nor the names + * of its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY + * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/** + * Convert M16c62p HAL A/D interface to the HIL interfaces. + * @author Fan Zhang + */ +#include "Timer.h" + +module AdcP +{ + provides { + interface Read[uint8_t client]; + interface ReadNow[uint8_t client]; + } + uses { + interface M16c62pAdcSingle; + interface M16c62pAdcConfig[uint8_t client]; + } +} +implementation { + enum { + IDLE, + ACQUIRE_DATA, + ACQUIRE_DATA_NOW, + }; + + /* Resource reservation is required, and it's incorrect to call getData + again before dataReady is signaled, so there are no races in correct + programs */ + norace uint8_t state; + norace uint8_t client; + norace uint16_t val; + + uint8_t channel() { + return call M16c62pAdcConfig.getChannel[client](); + } + + uint8_t precision() { + return call M16c62pAdcConfig.getPrecision[client](); + } + + uint8_t prescaler() { + return call M16c62pAdcConfig.getPrescaler[client](); + } + + void sample() { + call M16c62pAdcSingle.getData(channel(), precision(), prescaler()); + } + + error_t startGet(uint8_t newState, uint8_t newClient) { + /* Note: we retry imprecise results in dataReady */ + state = newState; + client = newClient; + sample(); + + return SUCCESS; + } + + command error_t Read.read[uint8_t c]() { + return startGet(ACQUIRE_DATA, c); + } + + async command error_t ReadNow.read[uint8_t c]() { + return startGet(ACQUIRE_DATA_NOW, c); + } + + task void acquiredData() { + state = IDLE; + signal Read.readDone[client](SUCCESS, val); + } + + async event void M16c62pAdcSingle.dataReady(uint16_t data, bool precise) { + switch (state) + { + case ACQUIRE_DATA: + if (!precise) + sample(); + else + { + val = data; + post acquiredData(); + } + break; + + case ACQUIRE_DATA_NOW: + if (!precise) + sample(); + else + { + state = IDLE; + signal ReadNow.readDone[client](SUCCESS, data); + } + break; + + default: + break; + } + } + + /* Configuration defaults. Read ground fast! ;-) */ + default async command uint8_t M16c62pAdcConfig.getChannel[uint8_t c]() { + return M16c62p_ADC_CHL_AN0; + } + + default async command uint8_t M16c62pAdcConfig.getPrecision[uint8_t c]() { + return M16c62p_ADC_PRECISION_10BIT; + } + + default async command uint8_t M16c62pAdcConfig.getPrescaler[uint8_t c]() { + return M16c62p_ADC_PRESCALE_2; + } + + default event void Read.readDone[uint8_t c](error_t e, uint16_t d) { } + default async event void ReadNow.readDone[uint8_t c](error_t e, uint16_t d) { } +} diff --git a/tos/chips/m16c62p/adc/AdcReadClientC.nc b/tos/chips/m16c62p/adc/AdcReadClientC.nc new file mode 100755 index 00000000..2f8588ce --- /dev/null +++ b/tos/chips/m16c62p/adc/AdcReadClientC.nc @@ -0,0 +1,40 @@ +/* $Id$ + * Copyright (c) 2005 Intel Corporation + * All rights reserved. + * + * This file is distributed under the terms in the attached INTEL-LICENSE + * file. If you do not find these files, copies can be found by writing to + * Intel Research Berkeley, 2150 Shattuck Avenue, Suite 1300, Berkeley, CA, + * 94704. Attention: Intel License Inquiry. + */ +/** + * Provide, as per TEP101, arbitrated access via a Read interface to the + * M16c62p ADC. Users of this component must link it to an + * implementation of M16c62pAdcConfig which provides the ADC parameters + * (channel, etc). + * + * @author Fan Zhang + */ + +#include "Adc.h" + +generic configuration AdcReadClientC() { + provides interface Read; + uses { + interface M16c62pAdcConfig; + interface ResourceConfigure; + } +} +implementation { + components WireAdcP, M16c62pAdcC; + + enum { + ID = unique(UQ_ADC_READ), + HAL_ID = unique(UQ_M16c62pADC_RESOURCE) + }; + + Read = WireAdcP.Read[ID]; + M16c62pAdcConfig = WireAdcP.M16c62pAdcConfig[ID]; + WireAdcP.Resource[ID] -> M16c62pAdcC.Resource[HAL_ID]; + ResourceConfigure = M16c62pAdcC.ResourceConfigure[HAL_ID]; +} diff --git a/tos/chips/m16c62p/adc/AdcReadNowClientC.nc b/tos/chips/m16c62p/adc/AdcReadNowClientC.nc new file mode 100755 index 00000000..aac167ad --- /dev/null +++ b/tos/chips/m16c62p/adc/AdcReadNowClientC.nc @@ -0,0 +1,43 @@ +/* $Id$ + * Copyright (c) 2005 Intel Corporation + * All rights reserved. + * + * This file is distributed under the terms in the attached INTEL-LICENSE + * file. If you do not find these files, copies can be found by writing to + * Intel Research Berkeley, 2150 Shattuck Avenue, Suite 1300, Berkeley, CA, + * 94704. Attention: Intel License Inquiry. + */ +/** + * Provide, as per TEP101, Resource-based access to the M16c62p ADC via a + * ReadNow interface. Users of this component must link it to an + * implementation of M16c62pAdcConfig which provides the ADC parameters + * (channel, etc). + * + * @author Fan Zhang + */ + +#include "Adc.h" + +generic configuration AdcReadNowClientC() { + provides { + interface Resource; + interface ReadNow; + } + uses { + interface M16c62pAdcConfig; + interface ResourceConfigure; + } +} +implementation { + components WireAdcP, M16c62pAdcC; + + enum { + ID = unique(UQ_ADC_READNOW), + HAL_ID = unique(UQ_M16c62pADC_RESOURCE) + }; + + ReadNow = WireAdcP.ReadNow[ID]; + M16c62pAdcConfig = WireAdcP.M16c62pAdcConfig[ID]; + Resource = M16c62pAdcC.Resource[HAL_ID]; + ResourceConfigure = M16c62pAdcC.ResourceConfigure[HAL_ID]; +} diff --git a/tos/chips/m16c62p/adc/AdcReadStreamClientC.nc b/tos/chips/m16c62p/adc/AdcReadStreamClientC.nc new file mode 100755 index 00000000..9886d13b --- /dev/null +++ b/tos/chips/m16c62p/adc/AdcReadStreamClientC.nc @@ -0,0 +1,40 @@ +/* $Id$ + * Copyright (c) 2005 Intel Corporation + * All rights reserved. + * + * This file is distributed under the terms in the attached INTEL-LICENSE + * file. If you do not find these files, copies can be found by writing to + * Intel Research Berkeley, 2150 Shattuck Avenue, Suite 1300, Berkeley, CA, + * 94704. Attention: Intel License Inquiry. + */ +/** + * Provide, as per TEP101, arbitrated access via a ReadStream interface to + * the M16c62p ADC. Users of this component must link it to an + * implementation of M16c62pAdcConfig which provides the ADC parameters + * (channel, etc). + * + * @author Fan Zhang + */ + +#include "Adc.h" + +generic configuration AdcReadStreamClientC() { + provides interface ReadStream; + uses { + interface M16c62pAdcConfig; + interface ResourceConfigure; + } +} +implementation { + components WireAdcStreamP, M16c62pAdcC; + + enum { + ID = unique(UQ_ADC_READSTREAM), + HAL_ID = unique(UQ_M16c62pADC_RESOURCE) + }; + + ReadStream = WireAdcStreamP.ReadStream[ID]; + M16c62pAdcConfig = WireAdcStreamP.M16c62pAdcConfig[ID]; + WireAdcStreamP.Resource[ID] -> M16c62pAdcC.Resource[HAL_ID]; + ResourceConfigure = M16c62pAdcC.ResourceConfigure[HAL_ID]; +} diff --git a/tos/chips/m16c62p/adc/AdcStreamP.nc b/tos/chips/m16c62p/adc/AdcStreamP.nc new file mode 100755 index 00000000..bb65d24b --- /dev/null +++ b/tos/chips/m16c62p/adc/AdcStreamP.nc @@ -0,0 +1,270 @@ +/* $Id$ + * Copyright (c) 2005 Intel Corporation + * All rights reserved. + * + * This file is distributed under the terms in the attached INTEL-LICENSE + * file. If you do not find these files, copies can be found by writing to + * Intel Research Berkeley, 2150 Shattuck Avenue, Suite 1300, Berkeley, CA, + * 94704. Attention: Intel License Inquiry. + * + * Copyright (c) 2004, Technische Universitaet Berlin + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of the Technische Universitaet Berlin nor the names + * of its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY + * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/** + * Convert M16c62p HAL A/D interface to the HIL interfaces. + * @author Fan Zhang + */ +#include "Timer.h" + +module AdcStreamP +{ + provides { + interface Init @atleastonce(); + interface ReadStream[uint8_t client]; + } + uses { + interface M16c62pAdcSingle; + interface M16c62pAdcConfig[uint8_t client]; + //interface M16c62pCalibrate; + interface Alarm; + } +} +implementation { + enum { + NSTREAM = uniqueCount(UQ_ADC_READSTREAM) + }; + + /* Resource reservation is required, and it's incorrect to call getData + again before dataReady is signaled, so there are no races in correct + programs */ + norace uint8_t client = NSTREAM; + + /* Stream data */ + struct list_entry_t { + uint16_t count; + struct list_entry_t * ONE_NOK next; + }; + struct list_entry_t *bufferQueue[NSTREAM]; + struct list_entry_t * ONE_NOK * bufferQueueEnd[NSTREAM]; + uint16_t * COUNT_NOK(lastCount) lastBuffer, lastCount; + + norace uint16_t count; + norace uint16_t * COUNT_NOK(count) buffer; + norace uint16_t * BND_NOK(buffer, buffer+count) pos; + norace uint32_t now, period; + + + command error_t Init.init() { + uint8_t i; + + for (i = 0; i != NSTREAM; i++) + bufferQueueEnd[i] = &bufferQueue[i]; + + return SUCCESS; + } + + uint8_t channel() { + return call M16c62pAdcConfig.getChannel[client](); + } + + uint8_t precision() { + return call M16c62pAdcConfig.getPrecision[client](); + } + + uint8_t prescaler() { + return call M16c62pAdcConfig.getPrescaler[client](); + } + + void sample() { + call M16c62pAdcSingle.getData(channel(), precision(), prescaler()); + } + + command error_t ReadStream.postBuffer[uint8_t c](uint16_t *buf, uint16_t n) { + if (n < sizeof(struct list_entry_t)) + return ESIZE; + atomic + { + struct list_entry_t * ONE newEntry = TCAST(struct list_entry_t * ONE, buf); + + if (!bufferQueueEnd[c]) // Can't post right now. + return FAIL; + + newEntry->count = n; + newEntry->next = NULL; + *bufferQueueEnd[c] = newEntry; + bufferQueueEnd[c] = &newEntry->next; + } + return SUCCESS; + } + + task void readStreamDone() { + uint8_t c = client; + //uint32_t actualPeriod = call M16c62pCalibrate.actualMicro(period); + uint32_t actualPeriod = period; // fanzha not debug + atomic + { + bufferQueue[c] = NULL; + bufferQueueEnd[c] = &bufferQueue[c]; + } + + client = NSTREAM; + signal ReadStream.readDone[c](SUCCESS, actualPeriod); + } + + task void readStreamFail() { + /* By now, the pending bufferDone has been signaled (see readStream). */ + struct list_entry_t *entry; + uint8_t c = client; + + atomic entry = bufferQueue[c]; + for (; entry; entry = entry->next){ + uint16_t tmp_count __DEPUTY_UNUSED__ = entry->count; + signal ReadStream.bufferDone[c](FAIL, TCAST(uint16_t * COUNT_NOK(tmp_count),entry), entry->count); + } + + atomic + { + bufferQueue[c] = NULL; + bufferQueueEnd[c] = &bufferQueue[c]; + } + + client = NSTREAM; + signal ReadStream.readDone[c](FAIL, 0); + } + + task void bufferDone() { + uint16_t *b, c; + atomic + { + b = lastBuffer; + c = lastCount; + lastBuffer = NULL; + } + + signal ReadStream.bufferDone[client](SUCCESS, b, c); + } + + void nextAlarm() { + call Alarm.startAt(now, period); + now += period; + } + + async event void Alarm.fired() { + sample(); + } + + command error_t ReadStream.read[uint8_t c](uint32_t usPeriod) + { + /* The first reading may be imprecise. So we just do a dummy read + to get things rolling - this is indicated by setting count to 0 */ + buffer = pos = NULL; + count = 0; + //period = call M16c62pCalibrate.calibrateMicro(usPeriod); + client = c; + sample(); + + return SUCCESS; + } + + void nextBuffer() { + atomic + { + struct list_entry_t *entry = bufferQueue[client]; + + if (!entry) + { + // all done + bufferQueueEnd[client] = NULL; // prevent post + post readStreamDone(); + } + else + { + uint16_t tmp_count; + bufferQueue[client] = entry->next; + if (!bufferQueue[client]) + bufferQueueEnd[client] = &bufferQueue[client]; + pos = buffer = NULL; + count = entry->count; + tmp_count = count; + pos = buffer = TCAST(uint16_t * COUNT_NOK(tmp_count), entry); + nextAlarm(); + } + } + } + + async event void M16c62pAdcSingle.dataReady(uint16_t data, bool precise) { + if (client == NSTREAM) + return; + + if (count == 0) + { + now = call Alarm.getNow(); + nextBuffer(); + } + else + { + *pos++ = data; + if (pos == buffer + count) + { + atomic + { + if (lastBuffer) + { + /* We failed to signal bufferDone in time. Fail. */ + bufferQueueEnd[client] = NULL; // prevent post + post readStreamFail(); + return; + } + else + { + lastCount = count; + lastBuffer = buffer; + } + } + post bufferDone(); + nextBuffer(); + } + else + nextAlarm(); + } + } + + /* Configuration defaults. Read ground fast! ;-) */ + default async command uint8_t M16c62pAdcConfig.getChannel[uint8_t c]() { + return M16c62p_ADC_CHL_AN0; + } + + default async command uint8_t M16c62pAdcConfig.getPrecision[uint8_t c]() { + return M16c62p_ADC_PRECISION_10BIT; + } + + default async command uint8_t M16c62pAdcConfig.getPrescaler[uint8_t c]() { + return M16c62p_ADC_PRESCALE_2; + } +} diff --git a/tos/chips/m16c62p/adc/HplM16c62pAdc.nc b/tos/chips/m16c62p/adc/HplM16c62pAdc.nc new file mode 100755 index 00000000..71f82ac6 --- /dev/null +++ b/tos/chips/m16c62p/adc/HplM16c62pAdc.nc @@ -0,0 +1,165 @@ +/// $Id$ + +/* + * Copyright (c) 2004-2005 Crossbow Technology, Inc. All rights reserved. + * + * Permission to use, copy, modify, and distribute this software and its + * documentation for any purpose, without fee, and without written agreement is + * hereby granted, provided that the above copyright notice, the following + * two paragraphs and the author appear in all copies of this software. + * + * IN NO EVENT SHALL CROSSBOW TECHNOLOGY OR ANY OF ITS LICENSORS BE LIABLE TO + * ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL + * DAMAGES ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN + * IF CROSSBOW OR ITS LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + * + * CROSSBOW TECHNOLOGY AND ITS LICENSORS SPECIFICALLY DISCLAIM ALL WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS + * ON AN "AS IS" BASIS, AND NEITHER CROSSBOW NOR ANY LICENSOR HAS ANY + * OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR + * MODIFICATIONS. + */ + +#include "M16c62pAdc.h" + +/** + * HPL interface to the M16c62p A/D conversion subsystem. + *

+ * conversion when the ADC and ADC interrupt are enabled. + * + * @author Martin Turon + * @author Hu Siquan + * @author David Gay + */ + +interface HplM16c62pAdc { + /** + * Read the ADCON0 (ADC control register 0) + * @return Current ADCON0 value + */ + async command M16c62pADCON0_t getADCON0(); + /** + * Set the ADCON0 (ADC control register 0) + * @param adcon0 New ADCON0 value + */ + async command void setADCON0(M16c62pADCON0_t adcon0); +///////////////////////////////////////////////////////////////////////////////// + /** + * Read the ADCON1 (ADC control) register + * @return Current ADCON1 value + */ + async command M16c62pADCON1_t getADCON1(); + /** + * Set the ADCON1 (ADC control) register + * @param adcon1 New ADCON1 value + */ + async command void setADCON1(M16c62pADCON1_t adcon1); +////////////////////////////////////////////////////////////////////////////////// + /** + * Read the ADCON2 (ADC control) register + * @return Current ADCON2 value + */ + async command M16c62pADCON2_t getADCON2(); + /** + * Set the ADCON2 (ADC control) register + * @param adcon2 New ADCON2 value + */ + async command void setADCON2(M16c62pADCON2_t adcon2); +///////////////////////////////////////////////////////////////////////////////// + /** + * Read the latest A/D conversion result + * @return A/D value + */ + async command uint16_t getValue(); + + /// A/D control utilities. All of these clear any pending A/D interrupt. + + /** + * Enable ADC sampling + */ + async command void enableAdc(); + /** + * Disable ADC sampling + */ + async command void disableAdc(); + + /** + * Enable ADC interrupt + */ + async command void enableInterruption(); + /** + * Disable ADC interrupt + */ + async command void disableInterruption(); + /** + * Clear the ADC interrupt flag + */ + async command void resetInterrupt(); + + /** + * Start ADC conversion. If ADC interrupts are enabled, the dataReady event + * will be signaled once (in non-continuous mode) or repeatedly (in + * continuous mode). + */ + async command void startConversion(); + /** + * Enable continuous sampling + */ + async command void setContinuous(); + /** + * Disable continuous sampling + */ + async command void setSingle(); + + /* A/D status checks */ + + /** + * Is ADC enabled? + * @return TRUE if the ADC is enabled, FALSE otherwise + */ + async command bool isEnabled(); + /** + * Is A/D conversion in progress? + * @return TRUE if the A/D conversion is in progress, FALSE otherwise + */ + async command bool isStarted(); + /** + * Is A/D conversion complete? Note that this flag is automatically + * cleared when an A/D interrupt occurs. + * @return TRUE if the A/D conversion is complete, FALSE otherwise + */ + async command bool isComplete(); + + + /** + * Set ADC precision selection bits + * @param scale New ADC prescision. Must be one of the M16c62p_ADC_PRECISION_xxx + * values from M16c62pAdc.h + */ + async command void setPrecision(uint8_t precision); + + /** + * Set ADC prescaler selection bits + * @param scale New ADC prescaler. Must be one of the M16c62p_ADC_PRESCALE_xxx + * values from M16c62pAdc.h + */ + async command void setPrescaler(uint8_t scale); + + /** + * Cancel A/D conversion and any pending A/D interrupt. Also disables the + * ADC interruption (otherwise a sample might start at the next sleep + * instruction). This command can assume that the A/D converter is enabled. + * @return TRUE if an A/D conversion was in progress or an A/D interrupt + * was pending, FALSE otherwise. In single conversion mode, a return + * of TRUE implies that the dataReady event will not be signaled. + */ + async command bool cancel(); + + /** + * A/D interrupt occured + * @param data Latest A/D conversion result + */ + async event void dataReady(uint16_t data); +} diff --git a/tos/chips/m16c62p/adc/HplM16c62pAdcC.nc b/tos/chips/m16c62p/adc/HplM16c62pAdcC.nc new file mode 100755 index 00000000..b38ca0cb --- /dev/null +++ b/tos/chips/m16c62p/adc/HplM16c62pAdcC.nc @@ -0,0 +1,43 @@ +/// $Id$ + +/* + * Copyright (c) 2004-2005 Crossbow Technology, Inc. All rights reserved. + * + * Permission to use, copy, modify, and distribute this software and its + * documentation for any purpose, without fee, and without written agreement is + * hereby granted, provided that the above copyright notice, the following + * two paragraphs and the author appear in all copies of this software. + * + * IN NO EVENT SHALL CROSSBOW TECHNOLOGY OR ANY OF ITS LICENSORS BE LIABLE TO + * ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL + * DAMAGES ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN + * IF CROSSBOW OR ITS LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + * + * CROSSBOW TECHNOLOGY AND ITS LICENSORS SPECIFICALLY DISCLAIM ALL WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS + * ON AN "AS IS" BASIS, AND NEITHER CROSSBOW NOR ANY LICENSOR HAS ANY + * OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR + * MODIFICATIONS. + */ + +#include "M16c62pAdc.h" + +/** + * HPL for the M16c62p A/D conversion susbsystem. + * + * @author Martin Turon + * @author Hu Siquan + * @author David Gay + */ + +configuration HplM16c62pAdcC { + provides interface HplM16c62pAdc; +} +implementation { + components HplM16c62pAdcP, McuSleepC; + + HplM16c62pAdc = HplM16c62pAdcP; + HplM16c62pAdcP.McuPowerState -> McuSleepC; +} diff --git a/tos/chips/m16c62p/adc/HplM16c62pAdcP.nc b/tos/chips/m16c62p/adc/HplM16c62pAdcP.nc new file mode 100755 index 00000000..01dea2d9 --- /dev/null +++ b/tos/chips/m16c62p/adc/HplM16c62pAdcP.nc @@ -0,0 +1,160 @@ +/// $Id$ +/* + * Copyright (c) 2004-2005 Crossbow Technology, Inc. All rights reserved. + * + * Permission to use, copy, modify, and distribute this software and its + * documentation for any purpose, without fee, and without written agreement is + * hereby granted, provided that the above copyright notice, the following + * two paragraphs and the author appear in all copies of this software. + * + * IN NO EVENT SHALL CROSSBOW TECHNOLOGY OR ANY OF ITS LICENSORS BE LIABLE TO + * ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL + * DAMAGES ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN + * IF CROSSBOW OR ITS LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + * + * CROSSBOW TECHNOLOGY AND ITS LICENSORS SPECIFICALLY DISCLAIM ALL WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS + * ON AN "AS IS" BASIS, AND NEITHER CROSSBOW NOR ANY LICENSOR HAS ANY + * OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR + * MODIFICATIONS. + */ + +#include "M16c62pAdc.h" + +/** + * HPL for the M16c62p A/D conversion susbsystem. + * + * @author Fan Zhang + * + */ + +module HplM16c62pAdcP +{ + provides interface HplM16c62pAdc; + uses interface McuPowerState; +} +implementation +{ + //=== Direct read of HW registers. ================================= + async command M16c62pADCON0_t HplM16c62pAdc.getADCON0() { + return *(M16c62pADCON0_t*)&ADCON0; + } + async command M16c62pADCON1_t HplM16c62pAdc.getADCON1() { + return *(M16c62pADCON1_t*)&ADCON1; + } + async command M16c62pADCON2_t HplM16c62pAdc.getADCON2() { + return *(M16c62pADCON2_t*)&ADCON2; + } + async command uint16_t HplM16c62pAdc.getValue() { + uint8_t channel = ADCON0.BYTE&0x07; + if(channel==0x00){return AD0.WORD;} + else if(channel==0x01){return AD1.WORD;} + else if(channel==0x02){return AD2.WORD;} + else if(channel==0x03){return AD3.WORD;} + else if(channel==0x04){return AD4.WORD;} + else if(channel==0x05){return AD5.WORD;} + else if(channel==0x06){return AD6.WORD;} + else {return AD7.WORD;} + + } + + DEFINE_UNION_CAST(ADCON02int, M16c62pADCON0_t, uint8_t); // type change from M16c62pADCON0_t to uint8_t + DEFINE_UNION_CAST(ADCON12int, M16c62pADCON1_t, uint8_t); + DEFINE_UNION_CAST(ADCON22int, M16c62pADCON2_t, uint8_t); + + //=== Direct write of HW registers. ================================ + async command void HplM16c62pAdc.setADCON0( M16c62pADCON0_t x ) { + ADCON0.BYTE = ADCON02int(x); + } + async command void HplM16c62pAdc.setADCON1( M16c62pADCON1_t x ) { + ADCON1.BYTE = ADCON12int(x); + } + async command void HplM16c62pAdc.setADCON2( M16c62pADCON2_t x ) { + ADCON2.BYTE = ADCON22int(x); + } + /* precision = 8 or 10, that means 8bit or 10bit */ + async command void HplM16c62pAdc.setPrecision(uint8_t precision){ + if(precision == M16c62p_ADC_PRECISION_8BIT) + ADCON1.BIT.BITS = 0; + else if(precision == M16c62p_ADC_PRECISION_10BIT) + ADCON1.BIT.BITS = 1; + } + /* Set ADC prescaler selection bits */ + async command void HplM16c62pAdc.setPrescaler(uint8_t scale){ + + if(scale == 0x00){ADCON2.BIT.CKS2=0;ADCON1.BIT.CKS1=0;ADCON0.BIT.CKS0=0;} // fAD/4 prescaler + else if(scale == 0x01){ADCON2.BIT.CKS2=0;ADCON1.BIT.CKS1=0;ADCON0.BIT.CKS0=1;} // fAD/2 prescaler + else if((scale == 0x02) || (scale == 0x03)){ADCON2.BIT.CKS2=0;ADCON1.BIT.CKS1=1;ADCON0.BIT.CKS0=0;} // fAD prescaler + else if(scale == 0x04){ADCON2.BIT.CKS2=1;ADCON1.BIT.CKS1=0;ADCON0.BIT.CKS0=0;} // fAD/12 prescaler + else if(scale == 0x05){ADCON2.BIT.CKS2=1;ADCON1.BIT.CKS1=0;ADCON0.BIT.CKS0=1;} // fAD/6 prescaler + else if((scale == 0x06) || (scale == 0x07)){ADCON2.BIT.CKS2=1;ADCON1.BIT.CKS1=1;ADCON0.BIT.CKS0=0;} // fAD/3 prescaler + + } + + // Individual bit manipulation. These all clear any pending A/D interrupt. + async command void HplM16c62pAdc.enableAdc() { + ADCON1.BIT.VCUT = 1; + call McuPowerState.update(); + } + async command void HplM16c62pAdc.disableAdc() { + ADCON1.BIT.VCUT = 0; + call McuPowerState.update(); + } + // A/D conversion interrupt control register is ADIC 2009-2-9 by Fan Zhang + async command void HplM16c62pAdc.enableInterruption() { ADIC.BIT.ILVL2=0;ADIC.BIT.ILVL1=0;ADIC.BIT.ILVL0=1; } + async command void HplM16c62pAdc.disableInterruption() { ADIC.BIT.ILVL2=0;ADIC.BIT.ILVL1=0;ADIC.BIT.ILVL0=0; } + async command void HplM16c62pAdc.startConversion() { ADCON0.BIT.ADST=1; } // ADST=6 + async command void HplM16c62pAdc.resetInterrupt() { } // Clear the ADC interrupt flag + /** + * Enable continuous sampling, that is repeat sampling mode + */ + async command void HplM16c62pAdc.setContinuous() { ADCON0.BIT.MD0=0;ADCON0.BIT.MD1=1; } + /** + * Disable continuous sampling, enable one-shot sampling mode + */ + async command void HplM16c62pAdc.setSingle() { ADCON0.BIT.MD0=0;ADCON0.BIT.MD1=0; } + + /* A/D status checks */ + async command bool HplM16c62pAdc.isEnabled(){ + // ADCON1.VCUT control the Vref connection, 0 disable connection, 1 connection + return ADCON1.BIT.VCUT; + } + + async command bool HplM16c62pAdc.isStarted() { + return ADCON0.BIT.ADST; + } + + async command bool HplM16c62pAdc.isComplete() { + // interrupt flag bit + return ADIC.BIT.IR; + } + + + /* A/D interrupt handlers. Signals dataReady event with interrupts enabled */ + default async event void HplM16c62pAdc.dataReady(uint16_t done) { } + M16C_INTERRUPT_HANDLER(M16C_AD) + { + uint16_t data = call HplM16c62pAdc.getValue(); + + __nesc_enable_interrupt(); + signal HplM16c62pAdc.dataReady(data); + } + + async command bool HplM16c62pAdc.cancel() { + /* This is tricky */ + atomic + { + /* To cancel a conversion, first turn off ADEN, then turn off + ADSC. We also cancel any pending interrupt. + Finally we reenable the ADC. + */ + //ADCON1.VCUT=0; + //ADIC.ILVL2=0;ADIC.ILVL1=0;ADIC.ILVL0=0; /* This disable ADC interrupt... */ + ADCON0.BIT.ADST=0; + //ADCON1.VCUT=1; + return TRUE; + } + } +} diff --git a/tos/chips/m16c62p/adc/M16c62pAdc.h b/tos/chips/m16c62p/adc/M16c62pAdc.h new file mode 100755 index 00000000..a8d4ba91 --- /dev/null +++ b/tos/chips/m16c62p/adc/M16c62pAdc.h @@ -0,0 +1,168 @@ +// $Id$ + +/* + * Copyright (c) 2004-2005 Crossbow Technology, Inc. All rights reserved. + * + * Permission to use, copy, modify, and distribute this software and its + * documentation for any purpose, without fee, and without written agreement is + * hereby granted, provided that the above copyright notice, the following + * two paragraphs and the author appear in all copies of this software. + * + * IN NO EVENT SHALL CROSSBOW TECHNOLOGY OR ANY OF ITS LICENSORS BE LIABLE TO + * ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL + * DAMAGES ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN + * IF CROSSBOW OR ITS LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + * + * CROSSBOW TECHNOLOGY AND ITS LICENSORS SPECIFICALLY DISCLAIM ALL WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS + * ON AN "AS IS" BASIS, AND NEITHER CROSSBOW NOR ANY LICENSOR HAS ANY + * OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR + * MODIFICATIONS. + */ + +// @author Martin Turon +// @author Hu Siquan + +#ifndef __H_M16C62PADC_H__ +#define __H_M16C62PADC_H__ + +//================== 8 channel 10-bit ADC ============================== + +/* Voltage Reference Settings */ +enum { + M16c62p_ADC_VREF_OFF = 0, //!< VR+ = AREF and VR- = GND + M16c62p_ADC_VREF_AVCC = 1,//!< VR+ = AVcc and VR- = GND +}; + +/* Voltage Reference Settings */ +enum { + M16c62p_ADC_RIGHT_ADJUST = 0, + M16c62p_ADC_LEFT_ADJUST = 1, +}; + + +/* ADC Channel Settings */ +enum { + M16c62p_ADC_CHL_AN0 = 0, + M16c62p_ADC_CHL_AN1, + M16c62p_ADC_CHL_AN2, + M16c62p_ADC_CHL_AN3, + M16c62p_ADC_CHL_AN4, + M16c62p_ADC_CHL_AN5, + M16c62p_ADC_CHL_AN6, + M16c62p_ADC_CHL_AN7, + M16c62p_ADC_CHL_AN10 = 8, + M16c62p_ADC_CHL_AN11, + M16c62p_ADC_CHL_AN12, + M16c62p_ADC_CHL_AN13, + M16c62p_ADC_CHL_AN14, + M16c62p_ADC_CHL_AN15, + M16c62p_ADC_CHL_AN16, + M16c62p_ADC_CHL_AN17, + +}; + +/* ADC Control Register 0 */ +typedef struct +{ + uint8_t ch012 : 3; //!< Analog Channel and Gain Selection Bits + uint8_t md01 : 2; //!< ADC operation mode select bit + uint8_t trg : 1; //!< Trigger select bit + uint8_t adst : 1; //!< ADC start flag + uint8_t cks0 :1; //!< Frequency Selection Bit 0 +} M16c62pADCON0_t; + +/* ADC Control Register 1 */ +typedef struct +{ + uint8_t scan01 : 2; //!< ADC scan mode select bit + uint8_t md2 : 1; //!< ADC operation mode select bit 1 + uint8_t bits : 1; //!< 8/10-bit mode select bit + uint8_t cks1 : 1; //!< Frequency select bit 1 + uint8_t vcut : 1; //!< Vref connect bit + uint8_t opa01 : 2; //!< External op-amp connection mode bit +} M16c62pADCON1_t; + +/* ADC Control Register 2 */ +typedef struct +{ + uint8_t smp : 1; //!< ADC method select bit + uint8_t adgsel01 : 2; //!< port group select: 00 select P10 group + // 01 select NULL + // 10 select P0 group + // 11 select P2 group + uint8_t bit3 : 1; //!< reserved bit (always set to 0) + uint8_t cks2 : 1; //!< Frequency select bit 2 + uint8_t bit5 : 1; //!< nothing assigned. + uint8_t bit6 : 1; //!< nothing assigned. + uint8_t bit7 : 1; //!< nothing assigned. +} M16c62pADCON2_t; + +/* ADC Prescaler Settings */ +/* Note: each platform must define M16c62p_ADC_PRESCALE to the smallest + prescaler which guarantees full A/D precision. */ +enum { + M16c62p_ADC_PRESCALE_2 = 1, + M16c62p_ADC_PRESCALE_3 = 6, + M16c62p_ADC_PRESCALE_4 = 0, + M16c62p_ADC_PRESCALE_6 = 5, + M16c62p_ADC_PRESCALE_12 = 4, + + // This special value is used to ask the platform for the prescaler + // which gives full precision. + M16c62p_ADC_PRESCALE = 2, +}; + +/* ADC Precision Settings */ +enum { + M16c62p_ADC_PRECISION_10BIT = 0, + M16c62p_ADC_PRECISION_8BIT, +}; + +/* ADC operation mode select bit */ +enum { + M16c62p_ADC_ONESHOT_MODE = 0, + M16c62p_ADC_REPEAT_MODE, +}; + +/* ADC Enable Settings */ +enum { + M16c62p_ADC_ENABLE_OFF = 0, + M16c62p_ADC_ENABLE_ON, +}; + +/* ADC Start Conversion Settings */ +enum { + M16c62p_ADC_START_CONVERSION_OFF = 0, + M16c62p_ADC_START_CONVERSION_ON, +}; + +/* ADC Free Running Select Settings */ +enum { + M16c62p_ADC_FREE_RUNNING_OFF = 0, + M16c62p_ADC_FREE_RUNNING_ON, +}; + +/* ADC Interrupt Flag Settings */ +enum { + M16c62p_ADC_INT_FLAG_OFF = 0, + M16c62p_ADC_INT_FLAG_ON, +}; + +/* ADC Interrupt Enable Settings */ +enum { + M16c62p_ADC_INT_ENABLE_OFF = 0, + M16c62p_ADC_INT_ENABLE_ON, +}; + + +typedef uint8_t M16c62p_ADCH_t; //!< ADC data register high +typedef uint8_t M16c62p_ADCL_t; //!< ADC data register low + +// The resource identifier string for the ADC subsystem +#define UQ_M16c62pADC_RESOURCE "M16c62padc.resource" + +#endif // __H_M16C62PADC_H_ + diff --git a/tos/chips/m16c62p/adc/M16c62pAdcC.nc b/tos/chips/m16c62p/adc/M16c62pAdcC.nc new file mode 100755 index 00000000..0e1ec3de --- /dev/null +++ b/tos/chips/m16c62p/adc/M16c62pAdcC.nc @@ -0,0 +1,69 @@ +/// $Id$ + +/* + * Copyright (c) 2004-2005 Crossbow Technology, Inc. All rights reserved. + * + * Permission to use, copy, modify, and distribute this software and its + * documentation for any purpose, without fee, and without written agreement is + * hereby granted, provided that the above copyright notice, the following + * two paragraphs and the author appear in all copies of this software. + * + * IN NO EVENT SHALL CROSSBOW TECHNOLOGY OR ANY OF ITS LICENSORS BE LIABLE TO + * ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL + * DAMAGES ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN + * IF CROSSBOW OR ITS LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + * + * CROSSBOW TECHNOLOGY AND ITS LICENSORS SPECIFICALLY DISCLAIM ALL WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS + * ON AN "AS IS" BASIS, AND NEITHER CROSSBOW NOR ANY LICENSOR HAS ANY + * OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR + * MODIFICATIONS. + * + * Copyright (c) 2005 Intel Corporation + * All rights reserved. + * + * This file is distributed under the terms in the attached INTEL-LICENSE + * file. If you do not find these files, copies can be found by writing to + * Intel Research Berkeley, 2150 Shattuck Avenue, Suite 1300, Berkeley, CA, + * 94704. Attention: Intel License Inquiry. + */ + +#include "M16c62pAdc.h" + +/** + * HAL for the M16c62p A/D conversion susbsystem. + * + * @author Hu Siquan + * @author David Gay + */ + +configuration M16c62pAdcC +{ + provides { + interface Resource[uint8_t client]; + interface M16c62pAdcSingle; + interface M16c62pAdcMultiple; + } + uses interface ResourceConfigure[uint8_t client]; +} +implementation +{ + components M16c62pAdcP, HplM16c62pAdcC, PlatformC, MainC, + new RoundRobinArbiterC(UQ_M16c62pADC_RESOURCE) as AdcArbiter, + new AsyncStdControlPowerManagerC() as PM; + + Resource = AdcArbiter; + ResourceConfigure = AdcArbiter; + M16c62pAdcSingle = M16c62pAdcP; + M16c62pAdcMultiple = M16c62pAdcP; + + PlatformC.SubInit -> M16c62pAdcP; + + M16c62pAdcP.HplM16c62pAdc -> HplM16c62pAdcC; + //M16c62pAdcP.M16c62pCalibrate -> PlatformC; + + PM.AsyncStdControl -> M16c62pAdcP; + PM.ResourceDefaultOwner -> AdcArbiter; +} diff --git a/tos/chips/m16c62p/adc/M16c62pAdcConfig.nc b/tos/chips/m16c62p/adc/M16c62pAdcConfig.nc new file mode 100755 index 00000000..5323e528 --- /dev/null +++ b/tos/chips/m16c62p/adc/M16c62pAdcConfig.nc @@ -0,0 +1,42 @@ +/* $Id$ + * Copyright (c) 2005 Intel Corporation + * All rights reserved. + * + * This file is distributed under the terms in the attached INTEL-LICENSE + * file. If you do not find these files, copies can be found by writing to + * Intel Research Berkeley, 2150 Shattuck Avenue, Suite 1300, Berkeley, CA, + * 94704. Attention: Intel License Inquiry. + */ + +#include "M16c62pAdc.h" + +/** + * Clients of higher level must provide this interface to + * specify which channel to sample, and with what parameters. + * + * @author Fan Zang + */ +interface M16c62pAdcConfig { + /** + * Obtain channel. + * @return The A/D channel to use. Must be one of the M16c62p_ADC_CHL_xxx + * values from M16c62pAdc.h. + */ + async command uint8_t getChannel(); + + /** + * Obtain precision setting + * @return The reference voltage to use. Must be one of the + * M16c62p_ADC_CHL_ANxx values from M16c62pAdc.h. + */ + async command uint8_t getPrecision(); + + /** + * Obtain prescaler value. + * @return The prescaler value to use. Must be one of the + * M16c62p_ADC_PRESCALE_xxx values from M16c62pAdc.h. + */ + async command uint8_t getPrescaler(); + + +} diff --git a/tos/chips/m16c62p/adc/M16c62pAdcMultiple.nc b/tos/chips/m16c62p/adc/M16c62pAdcMultiple.nc new file mode 100755 index 00000000..06fa4ba5 --- /dev/null +++ b/tos/chips/m16c62p/adc/M16c62pAdcMultiple.nc @@ -0,0 +1,119 @@ +/// $Id$ + +/* + * Copyright (c) 2004-2005 Crossbow Technology, Inc. All rights reserved. + * + * Permission to use, copy, modify, and distribute this software and its + * documentation for any purpose, without fee, and without written agreement is + * hereby granted, provided that the above copyright notice, the following + * two paragraphs and the author appear in all copies of this software. + * + * IN NO EVENT SHALL CROSSBOW TECHNOLOGY OR ANY OF ITS LICENSORS BE LIABLE TO + * ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL + * DAMAGES ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN + * IF CROSSBOW OR ITS LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + * + * CROSSBOW TECHNOLOGY AND ITS LICENSORS SPECIFICALLY DISCLAIM ALL WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS + * ON AN "AS IS" BASIS, AND NEITHER CROSSBOW NOR ANY LICENSOR HAS ANY + * OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR + * MODIFICATIONS. + * + * Copyright (c) 2002-2005 Intel Corporation + * All rights reserved. + * + * This file is distributed under the terms in the attached INTEL-LICENSE + * file. If you do not find these files, copies can be found by writing to + * Intel Research Berkeley, 2150 Shattuck Avenue, Suite 1300, Berkeley, CA, + * 94704. Attention: Intel License Inquiry. + */ + +/** + * Hardware Abstraction Layer interface of Atmega128 for acquiring data + * from multiple channels using the ATmega128's free-running mode. + *

+ * Because of the possibility that samples may be imprecise after + * switching channels and/or reference voltages, and because there + * is a one sample delay on swithcing channels and reference voltages, + * M16c62pADCMultiple is complex. Two straightforward uses are: + *

    + *
  1. Acquire N samples from channel C: + *
      + *
    1. call getData to start sampling on channel C at the desired rate + * (note that the choice of prescalers is very limited, so you + * don't have many choices for sampling rate) + *
    2. ignore the first dataReady event + *
    3. use the results of the next N dataReady() events, return FALSE + * on the last one + *
    + *
  2. Acquire one sample each from channels C1, ..., Cn (this pseudocode + * assumes that none of these channels are differential) + *
      + *
    1. call getData to start sampling on channel C1 + *
    2. on the ith dataReady event switch to channel Ci+1 by changing + * *newChannel + *
    3. the data passed to the ith dataReady event is for channel Ci-1 + * (the data from the first dataReady event is ignored) + *
    + *
+ * + * @author Hu Siquan + * @author David Gay + */ + +#include "M16c62pAdc.h" + +interface M16c62pAdcMultiple +{ + /** + * Initiates free-running ADC conversions, with the ability to switch + * channels and reference-voltage with a one sample delay. + * + * @param channel Initial A/D conversion channel. The channel can + * be changed in the dataReady event, though these changes happen + * with a one-sample delay (this is a hardware restriction). + * @param refVoltage Initial A/D reference voltage. See the + * M16c62p_ADC_VREF_xxx constants in M16c62pADC.h. Like the channel, + * the reference voltage can be changed in the dataReady event with + * a one-sample delay. + * @param leftJustify TRUE to place A/D result in high-order bits + * (i.e., shifted left by 6 bits), low to place it in the low-order bits + * @param prescaler Prescaler value for the A/D conversion clock. If you + * specify M16c62p_ADC_PRESCALE, a prescaler will be chosen that guarantees + * full precision. Other prescalers can be used to get faster conversions. + * See the ATmega128 manual for details. + * @return TRUE if the conversion will be precise, FALSE if it will be + * imprecise (due to a change in reference voltage, or switching to a + * differential input channel) + */ + async command bool getData(uint8_t channel, uint8_t precision, uint8_t prescaler); + + /** + * Returns the next sample in a free-running conversion. Allow the user + * to switch channels and/or reference voltages with a one sample delay. + * + * @param data a 2 byte unsigned data value sampled by the ADC. + * @param precise if this conversion was precise, FALSE if it wasn't + * (we assume that the second conversion after a change of reference + * voltage or after switching to a differential channel is precise) + * @param channel Channel this sample was from. + * @param newChannel Change this parameter to switch to a new channel + * for the second next sample. + * @param newRefVoltage Change this parameter to change the reference + * voltage for the second next sample. + * + * @return TRUE to continue sampling, FALSE to stop. + */ + async event bool dataReady(uint16_t data, bool precise, uint8_t channel, + uint8_t *newChannel, uint8_t *newRefVoltage); + + + /* Note: there is no cancel in free-running mode because you cannot tell + from a successful (or unsuccessful) cancellation whether there will + be another dataReady event. Thus you cannot tell when you can safely + reuse the ADC (short of waiting one ADC conversion period, in which + case you might as well use the result of dataReady to cancel). + */ +} diff --git a/tos/chips/m16c62p/adc/M16c62pAdcP.nc b/tos/chips/m16c62p/adc/M16c62pAdcP.nc new file mode 100755 index 00000000..ed340b9c --- /dev/null +++ b/tos/chips/m16c62p/adc/M16c62pAdcP.nc @@ -0,0 +1,220 @@ +/* $Id$ + * "Copyright (c) 2000-2003 The Regents of the University of California. + * All rights reserved. + * + * Permission to use, copy, modify, and distribute this software and its + * documentation for any purpose, without fee, and without written agreement is + * hereby granted, provided that the above copyright notice, the following + * two paragraphs and the author appear in all copies of this software. + * + * IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO ANY PARTY FOR + * DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT + * OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE UNIVERSITY OF + * CALIFORNIA HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * THE UNIVERSITY OF CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS + * ON AN "AS IS" BASIS, AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATION TO + * PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS." + * + * Copyright (c) 2002-2005 Intel Corporation + * All rights reserved. + * + * This file is distributed under the terms in the attached INTEL-LICENSE + * file. If you do not find these files, copies can be found by writing to + * Intel Research Berkeley, 2150 Shattuck Avenue, Suite 1300, Berkeley, CA, + * 94704. Attention: Intel License Inquiry. + * + * Copyright (c) 2004-2005 Crossbow Technology, Inc. All rights reserved. + * + * Permission to use, copy, modify, and distribute this software and its + * documentation for any purpose, without fee, and without written agreement is + * hereby granted, provided that the above copyright notice, the following + * two paragraphs and the author appear in all copies of this software. + * + * IN NO EVENT SHALL CROSSBOW TECHNOLOGY OR ANY OF ITS LICENSORS BE LIABLE TO + * ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL + * DAMAGES ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN + * IF CROSSBOW OR ITS LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + * + * CROSSBOW TECHNOLOGY AND ITS LICENSORS SPECIFICALLY DISCLAIM ALL WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS + * ON AN "AS IS" BASIS, AND NEITHER CROSSBOW NOR ANY LICENSOR HAS ANY + * OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR + * MODIFICATIONS. + */ + +#include "M16c62pAdc.h" + +/** + * Internal component of the M16c62p A/D HAL. + * + * @author Fan Zhang + */ + +module M16c62pAdcP +{ + provides { + interface Init; + interface AsyncStdControl; + interface M16c62pAdcSingle; + interface M16c62pAdcMultiple; + } + uses { + interface HplM16c62pAdc; + //interface M16c62pCalibrate; + } +} +implementation +{ + /* type change from uint8_t to M16c62pADCON0_t, this function is defined at m16c62phardware.h */ + DEFINE_UNION_CAST(int2ADCON0, uint8_t, M16c62pADCON0_t); // + DEFINE_UNION_CAST(int2ADCON1, uint8_t, M16c62pADCON1_t); + DEFINE_UNION_CAST(int2ADCON2, uint8_t, M16c62pADCON2_t); + command error_t Init.init() { + atomic + { + M16c62pADCON0_t adcon_0; + M16c62pADCON1_t adcon_1; + M16c62pADCON2_t adcon_2; + + adcon_0 = int2ADCON0(0x00); + adcon_0 = int2ADCON0(0x20); + adcon_0 = int2ADCON0(0x01); + + call HplM16c62pAdc.setADCON0(adcon_0); + call HplM16c62pAdc.setADCON1(adcon_1); + call HplM16c62pAdc.setADCON2(adcon_2); + } + return SUCCESS; + } + + /* We enable the A/D when start is called, and disable it when stop is + called. This drops A/D conversion latency by a factor of two (but + increases idle mode power consumption a little). + */ + async command error_t AsyncStdControl.start() { + atomic call HplM16c62pAdc.enableAdc(); + return SUCCESS; + } + + async command error_t AsyncStdControl.stop() { + atomic call HplM16c62pAdc.disableAdc(); + + return SUCCESS; + } + + /* Return TRUE if switching to 'channel' with reference voltage 'refVoltage' + will give a precise result (the first sample after changing reference + voltage or switching to/between a differential channel is imprecise) + */ + inline bool isPrecise(uint8_t admux, uint8_t channel, uint8_t refVoltage) { + return TRUE; + } + + /** + * Indicates a sample has been recorded by the ADC as the result + * of a ADC interrupt. + * + * @param data a 2 byte unsigned data value sampled by the ADC. + * @param precise if the conversion precise, FALSE if it wasn't. + */ + async event void HplM16c62pAdc.dataReady(uint16_t data) { + + /* A single sample. Disable the ADC interrupt to avoid starting + a new sample at the next "sleep" instruction. */ + call HplM16c62pAdc.disableInterruption(); + call HplM16c62pAdc.disableAdc(); + signal M16c62pAdcSingle.dataReady(data, TRUE); + + } + + /* Start sampling based on request parameters + * one-shot mode default + * refVoltage default + */ + void getData(uint8_t channel,uint8_t precision, uint8_t prescaler) { + M16c62pADCON0_t adcon0_t; + M16c62pADCON1_t adcon1_t; + M16c62pADCON2_t adcon2_t; + + if(channel < M16c62p_ADC_CHL_AN10) + { + adcon2_t.adgsel01 = 0; + } + else if((channel > M16c62p_ADC_CHL_AN7) && (channel <= M16c62p_ADC_CHL_AN17)) + { + adcon2_t.adgsel01 = 2; + channel=channel-8; + } + adcon0_t.ch012 = channel; + + adcon0_t.md01 = 0; + adcon0_t.trg = 0; + adcon0_t.adst = M16c62p_ADC_START_CONVERSION_ON; + + adcon1_t.md2 = 0; + if(precision == M16c62p_ADC_PRECISION_10BIT) // 10-bit mode + { + adcon1_t.bits = 1; + } + else + { + adcon1_t.bits = 0; + } + adcon1_t.vcut = M16c62p_ADC_ENABLE_ON; + adcon1_t.opa01 = 0; + + adcon2_t.smp = 1; // sample and hold + + if(prescaler == 0x00){adcon2_t.cks2=0;adcon1_t.cks1=0;adcon0_t.cks0=0;} // fAD/4 prescaler + else if(prescaler == 0x01){adcon2_t.cks2=0;adcon1_t.cks1=0;adcon0_t.cks0=1;} // fAD/2 prescaler + else if((prescaler == 0x02) || (prescaler == 0x03)){adcon2_t.cks2=0;adcon1_t.cks1=1;adcon0_t.cks0=0;} // fAD prescaler + else if(prescaler == 0x04){adcon2_t.cks2=1;adcon1_t.cks1=0;adcon0_t.cks0=0;} // fAD/12 prescaler + else if(prescaler == 0x05){adcon2_t.cks2=1;adcon1_t.cks1=0;adcon0_t.cks0=1;} // fAD/6 prescaler + else if((prescaler == 0x06) || (prescaler == 0x07)){adcon2_t.cks2=1;adcon1_t.cks1=1;adcon0_t.cks0=0;} // fAD/3 prescaler + + call HplM16c62pAdc.enableInterruption(); + + call HplM16c62pAdc.setADCON2(adcon2_t); + call HplM16c62pAdc.setADCON1(adcon1_t); + call HplM16c62pAdc.setADCON0(adcon0_t); + } + + async command bool M16c62pAdcSingle.getData(uint8_t channel, + uint8_t precision, uint8_t prescaler) { + atomic + { + getData(channel, precision, prescaler); + return TRUE; + } + } + + async command bool M16c62pAdcSingle.cancel() + { + /* There is no M16c62pAdcMultiple.cancel, for reasons discussed in that + interface */ + return call HplM16c62pAdc.cancel(); + } + + async command bool M16c62pAdcMultiple.getData(uint8_t channel, uint8_t precision, uint8_t prescaler) + { + atomic + { + getData(channel, precision, prescaler); + + return TRUE; + } + } + + default async event void M16c62pAdcSingle.dataReady(uint16_t data, bool precise) { + } + + default async event bool M16c62pAdcMultiple.dataReady(uint16_t data, bool precise, uint8_t channel, + uint8_t *newChannel, uint8_t *newRefVoltage) { + return FALSE; // stop conversion if we somehow end up here. + } +} diff --git a/tos/chips/m16c62p/adc/M16c62pAdcSingle.nc b/tos/chips/m16c62p/adc/M16c62pAdcSingle.nc new file mode 100755 index 00000000..83833e0a --- /dev/null +++ b/tos/chips/m16c62p/adc/M16c62pAdcSingle.nc @@ -0,0 +1,81 @@ +/// $Id$ + +/* + * Copyright (c) 2004-2005 Crossbow Technology, Inc. All rights reserved. + * + * Permission to use, copy, modify, and distribute this software and its + * documentation for any purpose, without fee, and without written agreement is + * hereby granted, provided that the above copyright notice, the following + * two paragraphs and the author appear in all copies of this software. + * + * IN NO EVENT SHALL CROSSBOW TECHNOLOGY OR ANY OF ITS LICENSORS BE LIABLE TO + * ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL + * DAMAGES ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN + * IF CROSSBOW OR ITS LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + * + * CROSSBOW TECHNOLOGY AND ITS LICENSORS SPECIFICALLY DISCLAIM ALL WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS + * ON AN "AS IS" BASIS, AND NEITHER CROSSBOW NOR ANY LICENSOR HAS ANY + * OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR + * MODIFICATIONS. + * + * Copyright (c) 2002-2005 Intel Corporation + * All rights reserved. + * + * This file is distributed under the terms in the attached INTEL-LICENSE + * file. If you do not find these files, copies can be found by writing to + * Intel Research Berkeley, 2150 Shattuck Avenue, Suite 1300, Berkeley, CA, + * 94704. Attention: Intel License Inquiry. + */ + +/** + * Hardware Abstraction Layer interface of M16c62p for acquiring + * a one-shot sampling from a channel. + * + * @author Fan Zhang + */ + +#include "M16c62pAdc.h" + +interface M16c62pAdcSingle +{ + /** + * Initiates an ADC conversion on a given channel. + * + * @param channel A/D conversion channel. + * @param refVoltage Select reference voltage for A/D conversion. See + * the M16c62p_ADC_VREF_xxx constants in M16c62pADC.h + * @param precision 8 to place A/D result in 8 bits, 10 to place it in + * the 10 bits + * @param prescaler Prescaler value for the A/D conversion clock. If you + * specify M16c62p_ADC_PRESCALE, a prescaler will be chosen that guarantees + * full precision. Other prescalers can be used to get faster conversions. + * See the M16c62p manual for details. + * @return TRUE if the conversion will be precise, FALSE if it will be + * imprecise (due to a change in refernce voltage, or switching to a + * differential input channel) + */ + async command bool getData(uint8_t channel, uint8_t precision, uint8_t prescaler); + + /** + * Indicates a sample has been recorded by the ADC as the result + * of a getData() command. + * + * @param data a 2 byte unsigned data value sampled by the ADC. + * @param precise if the conversion precise, FALSE if it wasn't. This + * values matches the result from the getData call. + */ + async event void dataReady(uint16_t data, bool precise); + + /** + * Cancel an outstanding getData operation. Use with care, to + * avoid problems with races between the dataReady event and cancel. + * @return TRUE if a conversion was in-progress or an interrupt + * was pending. dataReady will not be signaled. FALSE if the + * conversion was already complete. dataReady will be (or has + * already been) signaled. + */ + async command bool cancel(); +} diff --git a/tos/chips/m16c62p/adc/WireAdcP.nc b/tos/chips/m16c62p/adc/WireAdcP.nc new file mode 100755 index 00000000..b109519a --- /dev/null +++ b/tos/chips/m16c62p/adc/WireAdcP.nc @@ -0,0 +1,37 @@ +/* $Id$ + * Copyright (c) 2005 Intel Corporation + * All rights reserved. + * + * This file is distributed under the terms in the attached INTEL-LICENSE + * file. If you do not find these files, copies can be found by writing to + * Intel Research Berkeley, 2150 Shattuck Avenue, Suite 1300, Berkeley, CA, + * 94704. Attention: Intel License Inquiry. + */ +/** + * Support component for AdcReadClientC and AdcReadNowClientC. + * + * @author David Gay + */ + +configuration WireAdcP { + provides { + interface Read[uint8_t client]; + interface ReadNow[uint8_t client]; + } + uses { + interface M16c62pAdcConfig[uint8_t client]; + interface Resource[uint8_t client]; + } +} +implementation { + components M16c62pAdcC, AdcP, + new ArbitratedReadC(uint16_t) as ArbitrateRead; + + Read = ArbitrateRead; + ReadNow = AdcP; + Resource = ArbitrateRead.Resource; + M16c62pAdcConfig = AdcP; // provide default M16c62pAdcConfig interface + + ArbitrateRead.Service -> AdcP.Read; + AdcP.M16c62pAdcSingle -> M16c62pAdcC; +} diff --git a/tos/chips/m16c62p/adc/WireAdcStreamP.nc b/tos/chips/m16c62p/adc/WireAdcStreamP.nc new file mode 100755 index 00000000..29a52298 --- /dev/null +++ b/tos/chips/m16c62p/adc/WireAdcStreamP.nc @@ -0,0 +1,40 @@ +/* $Id$ + * Copyright (c) 2005 Intel Corporation + * All rights reserved. + * + * This file is distributed under the terms in the attached INTEL-LICENSE + * file. If you do not find these files, copies can be found by writing to + * Intel Research Berkeley, 2150 Shattuck Avenue, Suite 1300, Berkeley, CA, + * 94704. Attention: Intel License Inquiry. + */ +/** + * Support component for AdcReadStreamClientC. + * + * @author Fan Zhang + */ + +#include "Adc.h" + +configuration WireAdcStreamP { + provides interface ReadStream[uint8_t client]; + uses { + interface M16c62pAdcConfig[uint8_t client]; + interface Resource[uint8_t client]; + } +} +implementation { + components M16c62pAdcC, AdcStreamP, PlatformC, MainC, + new AlarmMicro32C(), + new ArbitratedReadStreamC(uniqueCount(UQ_ADC_READSTREAM), uint16_t) as ArbitrateReadStream; + + Resource = ArbitrateReadStream; + ReadStream = ArbitrateReadStream; + M16c62pAdcConfig = AdcStreamP; + + ArbitrateReadStream.Service -> AdcStreamP; + + AdcStreamP.Init <- MainC; + AdcStreamP.M16c62pAdcSingle -> M16c62pAdcC; + //AdcStreamP.M16c62pCalibrate -> PlatformC; + AdcStreamP.Alarm -> AlarmMicro32C; +} diff --git a/tos/chips/m16c62p/bits.h b/tos/chips/m16c62p/bits.h new file mode 100755 index 00000000..d91eb859 --- /dev/null +++ b/tos/chips/m16c62p/bits.h @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2009 Communication Group and Eislab at + * Lulea University of Technology + * + * Contact: Laurynas Riliskis, LTU + * Mail: laurynas.riliskis@ltu.se + * All rights reserved. + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * - Neither the name of Communication Group at Lulea University of Technology + * nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL STANFORD + * UNIVERSITY OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED + * OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __BITS_H__ +#define __BITS_H__ + +#define BIT0 0x1 +#define BIT1 0x2 +#define BIT2 0x4 +#define BIT3 0x8 +#define BIT4 0x10 +#define BIT5 0x20 +#define BIT6 0x40 +#define BIT7 0x80 +#define BIT8 0x100 +#define BIT9 0x200 +#define BIT10 0x400 +#define BIT11 0x800 +#define BIT12 0x1000 +#define BIT13 0x2000 +#define BIT14 0x4000 +#define BIT15 0x8000 +#define BIT16 0x10000 +#define BIT17 0x20000 +#define BIT18 0x40000 +#define BIT19 0x80000 +#define BIT20 0x100000 +#define BIT21 0x200000 +#define BIT22 0x400000 +#define BIT23 0x800000 +#define BIT24 0x1000000 +#define BIT25 0x2000000 +#define BIT26 0x4000000 +#define BIT27 0x8000000 +#define BIT28 0x10000000 +#define BIT29 0x20000000 +#define BIT30 0x40000000 +#define BIT31 0x80000000 + +#endif // __BITS_H__ + diff --git a/tos/chips/m16c62p/interrupts.h b/tos/chips/m16c62p/interrupts.h new file mode 100755 index 00000000..732152c2 --- /dev/null +++ b/tos/chips/m16c62p/interrupts.h @@ -0,0 +1,127 @@ +/* + * Copyright (c) 2009 Communication Group and Eislab at + * Lulea University of Technology + * + * Contact: Laurynas Riliskis, LTU + * Mail: laurynas.riliskis@ltu.se + * All rights reserved. + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * - Neither the name of Communication Group at Lulea University of Technology + * nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL STANFORD + * UNIVERSITY OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED + * OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + * M16C interrupt id defines. + * + * @author Per Lindgren + * @author Johan Eriksson + * @author Johan Nordlander + * @author Simon Aittamaa. + */ + +#ifndef M16C_INTERRUPTS_H_ +#define M16C_INTERRUPTS_H_ + +/* Software interrupts - bound to peripheral hardware */ + +#define M16C_BRK 0 +#define M16C_INT3 4 +#define M16C_TMRB5 5 +#define M16C_TMRB4 6 +#define M16C_UART1_BCD 6 +#define M16C_TMRB3 7 +#define M16C_UART0_BCD 7 +#define M16C_INT5 8 +#define M16C_SI_O4 8 +#define M16C_INT4 9 +#define M16C_SI_O3 9 +#define M16C_UART2_BCD 10 +#define M16C_DMA0 11 +#define M16C_DMA1 12 +#define M16C_KEY 13 +#define M16C_AD 14 +#define M16C_UART2_NACK 15 +#define M16C_UART2_ACK 16 +#define M16C_UART0_NACK 17 +#define M16C_UART0_ACK 18 +#define M16C_UART1_NACK 19 +#define M16C_UART1_ACK 20 +#define M16C_TMRA0 21 +#define M16C_TMRA1 22 +#define M16C_TMRA2 23 +#define M16C_TMRA3 24 +#define M16C_TMRA4 25 +#define M16C_TMRB0 26 +#define M16C_TMRB1 27 +#define M16C_TMRB2 28 +#define M16C_INT0 29 +#define M16C_INT1 30 +#define M16C_INT2 31 + +/* Software interrupts - not bound to peripheral hardware */ + +#define M16C_SINT0 32 +#define M16C_SINT1 33 +#define M16C_SINT2 34 +#define M16C_SINT3 35 +#define M16C_SINT4 36 +#define M16C_SINT5 37 +#define M16C_SINT6 38 +#define M16C_SINT7 39 +#define M16C_SINT8 40 +#define M16C_SINT9 41 +#define M16C_SINT10 42 +#define M16C_SINT11 43 +#define M16C_SINT12 44 +#define M16C_SINT13 45 +#define M16C_SINT14 46 +#define M16C_SINT15 47 +#define M16C_SINT16 48 +#define M16C_SINT17 49 +#define M16C_SINT18 50 +#define M16C_SINT19 51 +#define M16C_SINT20 52 +#define M16C_SINT21 53 +#define M16C_SINT22 54 +#define M16C_SINT23 55 +#define M16C_SINT24 56 +#define M16C_SINT25 57 +#define M16C_SINT26 58 +#define M16C_SINT27 59 +#define M16C_SINT28 60 +#define M16C_SINT29 61 +#define M16C_SINT30 62 +#define M16C_SINT31 63 + +/* Interrupt macro */ +#define _M16C_INTERRUPT(id) _vector_##id +#define M16C_INTERRUPT(id) \ + void __attribute__((interrupt)) _M16C_INTERRUPT(id)(void) + +#endif + + diff --git a/tos/chips/m16c62p/iom16c62p.h b/tos/chips/m16c62p/iom16c62p.h new file mode 100755 index 00000000..658bb7a5 --- /dev/null +++ b/tos/chips/m16c62p/iom16c62p.h @@ -0,0 +1,2757 @@ +/**************************************************************** +KPIT Cummins Infosystems Ltd, Pune, India. 1-April-2006. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + +*****************************************************************/ +/****************************************************************/ +/* M16C/60 62P Include File */ +/****************************************************************/ + +#ifndef __IOM16C62P_H__ +#define __IOM16C62P_H__ + +/*------------------------------------------------------ + Processor mode register 0 //0x0004 +------------------------------------------------------*/ +union st_pm0 { /* union PM0 */ + struct { /* Bit Access */ + unsigned char PM0_0:1; /* Processor mode bit 0 */ + unsigned char PM0_1:1; /* Processor mode bit 1 */ + unsigned char PM0_2:1; /* R/W mode select bit */ + unsigned char PM0_3:1; /* Software reset bit */ + unsigned char PM0_4:1; /* Multiplexed bus space select bit 0 */ + unsigned char PM0_5:1; /* Multiplexed bus space select bit 1 */ + unsigned char PM0_6:1; /* Port P40 to P43 function select bit */ + unsigned char PM0_7:1; /* BCLK output disable bit */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /* */ + +/*------------------------------------------------------ + Processor mode register 1 //0x0005 +------------------------------------------------------*/ +union st_pm1 { /* union PM1 */ + struct { /* Bit Access */ + unsigned char PM1_0:1; /* CS2 area switching bit */ + unsigned char PM1_1:1; /* Port P3_4 to P3_7 function select bit */ + unsigned char PM1_2:1; /* Watch dog timer function select bit */ + unsigned char PM1_3:1; /* Intermal reserved area expansion bit */ + unsigned char PM1_4:1; /* Memory area expansion bit */ + unsigned char PM1_5:1; /* Memory area expansion bit */ + unsigned char PM1_6:1; /* Reserved bit */ + unsigned char PM1_7:1; /* PM17 - Wait bit */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /* */ + +/*------------------------------------------------------ + System clock control register 0 //0x0006 +------------------------------------------------------*/ +union st_cm0 { /* union CM0 */ + struct { /* Bit Access */ + unsigned char CM0_0:1; /* Clock output function select bit */ + unsigned char CM0_1:1; /* Clock output function select bit */ + unsigned char CM0_2:1; /* WAIT peripheral function clock stop bit */ + unsigned char CM0_3:1; /* Xcin-Xcout drive capacity select bit*/ + unsigned char CM0_4:1; /* Port Xc select bit */ + unsigned char CM0_5:1; /* Main clock stop bit */ + unsigned char CM0_6:1; /* Main clock division select bit 0 */ + unsigned char CM0_7:1; /* System clock select bit */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /* system clock control register 0 */ + + +/*------------------------------------------------------ + System clock control register 1 //0x0007 +------------------------------------------------------*/ +union st_cm1 { /* union CM1 */ + struct { /* Bit Access */ + unsigned char CM1_0:1; /* All clock stop control bit */ + unsigned char CM1_1:1; /* Reserved bit always set to 0 */ + unsigned char :1; /* Reserved bit always set to 0 */ + unsigned char :1; /* Reserved bit always set to 0 */ + unsigned char :1; /* Reserved bit always set to 0 */ + unsigned char CM1_5:1; /* Xin-Xouts drive capacity select bit */ + unsigned char CM1_6:1; /* Main clock division select bit 1 */ + unsigned char CM1_7:1; /* Main clock division select bit 1 */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /* system clock control register 1 */ + + +/*------------------------------------------------------ + Chip select control register //0x0008 +------------------------------------------------------*/ +union st_csr { /* union CSR */ + struct { /* Bit Access */ + unsigned char CS0 :1; /* CS0~ output enable bit */ + unsigned char CS1 :1; /* CS1~ output enable bit */ + unsigned char CS2 :1; /* CS2~ output enable bit */ + unsigned char CS3 :1; /* CS3~ output enable bit */ + unsigned char CS0W:1; /* CS0~ wait bit */ + unsigned char CS1W:1; /* CS1~ wait bit */ + unsigned char CS2W:1; /* CS2~ wait bit */ + unsigned char CS3W:1; /* CS3~ wait bit */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /* Chip select control register */ + +/*------------------------------------------------------ + Address match interrupt enable register //0x0009 +------------------------------------------------------*/ +union st_aier { /* union AIER */ + struct { /* Bit Access */ + unsigned char AIER0:1; /* Address match interrupt0 enable bit*/ + unsigned char AIER1:1; /* Address match interrupt1 enable bit*/ + unsigned char :1; /* Nothing assigned */ + unsigned char :1; /* Nothing assigned */ + unsigned char :1; /* Nothing assigned */ + unsigned char :1; /* Nothing assigned */ + unsigned char :1; /* Nothing assigned */ + unsigned char :1; /* Nothing assigned */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /* Address match interrupt enable register */ + + +/*------------------------------------------------------ + Protect register //0x000A +-----------------------------------------------------*/ +union st_prcr { /* union PRCR */ + struct { /* Bit Access */ + unsigned char PRC0:1; /* Enables writing to system clock control registers 0 & 1 */ + unsigned char PRC1:1; /* Enables writing to processor mode registers 0 & 1 */ + unsigned char PRC2:1; /* Enables writing to port P9 direction register & SI/Oi control register(i=3,4)*/ + unsigned char PRC3:1; /* Enable writting to Power supply detection register 2 and Power supply down detection register */ + unsigned char :1; /* Nothing assigned */ + unsigned char :1; /* Nothing assigned */ + unsigned char :1; /* Nothing assigned */ + unsigned char :1; /* Nothing assigned */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /* Protect register */ + +/*------------------------------------------------------ + Data bank register //0x000B +------------------------------------------------------*/ +union st_dbr { /* union DBR */ + struct { /* Bit Access */ + unsigned char :1; /* Nothing assigned */ + unsigned char :1; /* Nothing assigned */ + unsigned char OFS :1; /* Offset bit */ + unsigned char BSR0:1; /* Bank select bit 0 */ + unsigned char BSR1:1; /* Bank select bit 1 */ + unsigned char BSR2:1; /* Bank select bit 2 */ + unsigned char :1; /* Nothing assigned */ + unsigned char :1; /* Nothing assigned */ + } BIT; /* */ + unsigned char BYTE; /* Data bank register */ +}; + +/*------------------------------------------------------ + Oscillation stop detection register //0x000C +------------------------------------------------------*/ +union st_cm2 { /* union CM2 */ + struct { /* Bit Access */ + unsigned char CM2_0:1; /* Oscillation stop detection bit */ + unsigned char CM2_1:1; /* Main clock switch bit */ + unsigned char CM2_2:1; /* Oscillation stop detection status */ + unsigned char CM2_3:1; /* Clock monitor bit */ + unsigned char :1; /* Nothing assigned */ + unsigned char :1; /* Nothing assigned */ + unsigned char :1; /* Nothing assigned */ + unsigned char CM2_7:1; /* Operation select bit(when an oscillation stop is detected) */ + } BIT; /* */ + unsigned char BYTE; /* Oscillation stop detection register */ +}; + +/*------------------------------------------------------ + Watchdog timer control register //0x000f +-----------------------------------------------------*/ +union st_wdc { /* union WDC */ + struct { /* Bit Access */ + unsigned char B0:1; /* High-order bit of watchdog timer */ + unsigned char B1:1; /* High-order bit of watchdog timer */ + unsigned char B2:1; /* High-order bit of watchdog timer */ + unsigned char B3:1; /* High-order bit of watchdog timer */ + unsigned char B4:1; /* High-order bit of watchdog timer */ + unsigned char WDC5:1; /* Cold start / warm start discrimination flag */ + unsigned char B6:1; /* Reserved bit, must always be 0 */ + unsigned char WDC7:1; /* Prescaler select bit */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /* Watchdog timer control register */ + +/*------------------------------------------------------ + Address match interrupt register 0 //0x0010 +-----------------------------------------------------*/ +union st_rmad0 { + struct{ + unsigned char RMAD0L; /* Address match interrupt register 0 low 8 bit */ + unsigned char RMAD0M; /* Address match interrupt register 0 mid 8 bit */ + unsigned char RMAD0H; /* Address match interrupt register 0 high 8 bit */ + unsigned char NC; /* non use */ + } BYTE; /* Byte access */ + unsigned long DWORD; /* Word Access */ +}; /* Address match interrupt register 0 32 bit */ + +/*------------------------------------------------------ + Address match interrupt register 1 //0x0014 +-----------------------------------------------------*/ +union st_rmad1 { + struct{ + unsigned char RMAD1L; /* Address match interrupt register 1 low 8 bit */ + unsigned char RMAD1M; /* Address match interrupt register 1 mid 8 bit */ + unsigned char RMAD1H; /* Address match interrupt register 1 high 8 bit */ + unsigned char NC; /* non use */ + } BYTE; /* Byte access */ + unsigned long DWORD; /* Word Access */ +}; /* Address match interrupt register 1 32 bit */ + +/*------------------------------------------------------ + Voltage Detection Register 1 //0x0019 +-----------------------------------------------------*/ +union st_vcr1 { /* union VCR1 */ + struct { /* Bit Access */ + unsigned char B0:1; /* Reserved bit,must be 0 */ + unsigned char B1:1; /* Reserved bit,must be 0 */ + unsigned char B2:1; /* Reserved bit,must be 0 */ + unsigned char VC1_3:1; /* Voltage down monitor flag */ + unsigned char B4:1; /* Reserved bit,must be 0 */ + unsigned char B5:1; /* Reserved bit,must be 0 */ + unsigned char B6:1; /* Reserved bit, must always be 0 */ + unsigned char B7:1; /* Reserved bit,must be 0 */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /* Voltage Detection Register 1 */ + +/*------------------------------------------------------ + Voltage Detection Register 2 //0x001A +-----------------------------------------------------*/ +union st_vcr2 { /* union VCR2 */ + struct { /* Bit Access */ + unsigned char B0:1; /* Reserved bit,must be 0 */ + unsigned char B1:1; /* Reserved bit,must be 0 */ + unsigned char B2:1; /* Reserved bit,must be 0 */ + unsigned char B3:1; /* Reserved bit,must be 0 */ + unsigned char B4:1; /* Reserved bit,must be 0 */ + unsigned char B5:1; /* Reserved bit,must be 0 */ + unsigned char VC2_6:1; /* Reset area monitor bit */ + unsigned char VC2_7:1; /* Voltage down monitor bit */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /* Voltage Detection Register 1 */ + +/*------------------------------------------------------ + Chip select expansion control register//0x001B +-----------------------------------------------------*/ +union st_cse { /* union CSE */ + struct { /* Bit Access */ + unsigned char CSE00W:1; /* CS0~ wait expansion bit */ + unsigned char CSE01W:1; /* CS0~ wait expansion bit */ + unsigned char CSE10W:1; /* CS1~ wait expansion bit */ + unsigned char CSE11W:1; /* CS1~ wait expansion bit */ + unsigned char CSE20W:1; /* CS2~ wait expansion bit */ + unsigned char CSE21W:1; /* CS2~ wait expansion bit */ + unsigned char CSE30W:1; /* CS3~ wait expansion bit */ + unsigned char CSE31W:1; /* CS3~ wait expansion bit */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /* Chip select expansion control register */ + +/*------------------------------------------------------ + PLL control register 0 //0x001C +-----------------------------------------------------*/ +union st_plc0 { /* union */ + struct { /* Bit Access */ + unsigned char PLC00:1; /* Programmable counter select bit */ + unsigned char PLC01:1; /* Programmable counter select bit */ + unsigned char PLC02:1; /* Programmable counter select bit */ + unsigned char :1; /* Nothing assigned */ + unsigned char :1; /* Reserved bit,set to one */ + unsigned char :1; /* Reserved bit,set to zero */ + unsigned char :1; /* Reserved bit,set to zero */ + unsigned char PLC07:1; /* Operation enable bit */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /* PLL control register 0 */ + +/*------------------------------------------------------ + Processor mode register 2 //0x001E +-----------------------------------------------------*/ +union st_pm2 { /* union */ + struct { /* Bit Access */ + unsigned char PM2_0:1; /* Specifying wait when accessing SFR at PLL operation */ + unsigned char PM2_1:1; /* System clock protective bit */ + unsigned char PM2_2:1; /* WDT count source protective bit */ + unsigned char :1; /* Reserved bit,set to zero */ + unsigned char :1; /* Reserved bit,set to zero */ + unsigned char :1; /* Nothing assigned */ + unsigned char :1; /* Nothing assigned */ + unsigned char :1; /* Nothing assigned */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /* Processor mode register 2 */ + +/*------------------------------------------------------ + Power supply down detection register //0x001F +-----------------------------------------------------*/ +union st_d4int { /* union */ + struct { /* Bit Access */ + unsigned char D40:1; /* Power supply down detection interrupt enable bit */ + unsigned char D41:1; /* STOP mode deactivation control bit */ + unsigned char D42:1; /* Power supply change detection flag */ + unsigned char D43:1; /* WDT overflow detect flag */ + unsigned char DF0:1; /* Sampling clock select bit */ + unsigned char DF1:1; /* Sampling clock select bit */ + unsigned char :1; /* Nothing assigned */ + unsigned char :1; /* Nothing assigned */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /* Power supply down detection register */ + +/*------------------------------------------------------ + DMA0 source pointer //0x0020 +-----------------------------------------------------*/ +union st_sar0 { + struct{ + unsigned char SAR01; /* DMA0 source pointer low 8 bit */ + unsigned char SAR0M; /* DMA0 source pointer mid 8 bit */ + unsigned char SAR0H; /* DMA0 source pointer high 8 bit */ + unsigned char NC; /* non use */ + } BYTE; /* Byte access */ + unsigned long DWORD; /* Word Access */ +}; /* DMA0 source pointer 32 bit */ + +/*------------------------------------------------------ + DMA1 source pointer //0x0030 +-----------------------------------------------------*/ +union st_sar1 { + struct{ + unsigned char SAR11; /* DMA1 source pointer low 8 bit */ + unsigned char SAR1M; /* DMA1 source pointer mid 8 bit */ + unsigned char SAR1H; /* DMA1 source pointer high 8 bit */ + unsigned char NC; /* non use */ + } BYTE; /* Byte access */ + unsigned long DWORD; /* Word Access */ +}; /* DMA1 source pointer 32 bit */ + +/*------------------------------------------------------ + DMA0 destination pointer //0x0024 +-----------------------------------------------------*/ +union st_dar0 { /* DMA0 destination pointer 32 bit */ + struct{ + unsigned char DAR0L; /* DMA0 destination pointer low 8 bit */ + unsigned char DAR0M; /* DMA0 destination pointer mid 8 bit */ + unsigned char DAR0H; /* DMA0 destination pointer high 8 bit */ + unsigned char NC; /* non use */ + } BYTE; /* Byte access */ + unsigned long DWORD; /* Word Access */ +}; + +/*------------------------------------------------------ + DMA1 destination pointer //0x0034 +-----------------------------------------------------*/ +union st_dar1 { /* DMA1 destination pointer 32 bit */ + struct{ + unsigned char DAR1L; /* DMA1 destination pointer low 8 bit */ + unsigned char DAR1M; /* DMA1 destination pointer mid 8 bit */ + unsigned char DAR1H; /* DMA1 destination pointer high 8 bit */ + unsigned char NC; /* non use */ + } BYTE; /* Byte access */ + unsigned long DWORD; /* Word Access */ +}; + +/*------------------------------------------------------ + DMA0 transfer counter //0x0028 +-----------------------------------------------------*/ +union st_tcr0 { /* DMA0 transfer counter 16 bit */ + struct{ + unsigned char TCR0L; /* DMA0 transfer counter low 8 bit */ + unsigned char TCR0H; /* DMA0 transfer counter high 8 bit */ + } BYTE; /* Byte access */ + unsigned short WORD; /* Word Access */ +}; + +/*------------------------------------------------------ + DMA1 transfer counter //0x0038 +-----------------------------------------------------*/ +union st_tcr1 { /* DMA1 transfer counter 16 bit */ + struct{ + unsigned char TCR1L; /* DMA1 transfer counter low 8 bit */ + unsigned char TCR1H; /* DMA1 transfer counter high 8 bit */ + } BYTE; /* Byte access */ + unsigned short WORD; /* Word Access */ +}; + +/*------------------------------------------------------ + DMA0 control register //0x002c +------------------------------------------------------*/ +union st_dm0con { /* DMA0 control register */ + struct{ + unsigned char DMBIT:1; /* Transfer unit bit select bit */ + unsigned char DMASL:1; /* Repeat transfer mode select bit */ + unsigned char DMAS :1; /* DMA request bit */ + unsigned char DMAE :1; /* DMA enable bit */ + unsigned char DSD :1; /* Source address direction select bit */ + unsigned char DAD :1; /* Destination address direction select bit */ + unsigned char :1; + unsigned char :1; + }BIT; + unsigned char BYTE; +}; + +/*------------------------------------------------------ + DMA1 control register //0x003c +------------------------------------------------------*/ +union st_dm1con { /* DMA1 control register union */ + struct{ + unsigned char DMBIT:1; /* Transfer unit bit select bit */ + unsigned char DMASL:1; /* Repeat transfer mode select bit */ + unsigned char DMAS :1; /* DMA request bit */ + unsigned char DMAE :1; /* DMA enable bit */ + unsigned char DSD :1; /* Source address direction select bit */ + unsigned char DAD :1; /* Destination address direction select bit */ + unsigned char :1; /*Nothing assigned */ + unsigned char :1; /*Nothing assigned */ + }BIT; + unsigned char BYTE; +}; + +union st_icr { /* interrupt control registers */ + struct{ + unsigned char ILVL0:1; /* Interrupt priority level select bit */ + unsigned char ILVL1:1; /* Interrupt priority level select bit */ + unsigned char ILVL2:1; /* Interrupt priority level select bit */ + unsigned char IR :1; /* Interrupt request bit */ + unsigned char POL :1; /* Polarity select bit */ + unsigned char :1; /* Reserved bit, set to 0 */ + unsigned char :1; /* Nothing assigned */ + unsigned char :1; /* Nothing assigned */ + }BIT; + unsigned char BYTE; +}; + +union st_icr1 { /* interrupt control registers */ + struct{ + unsigned char ILVL0:1; /* Interrupt priority level select bit */ + unsigned char ILVL1:1; /* Interrupt priority level select bit */ + unsigned char ILVL2:1; /* Interrupt priority level select bit */ + unsigned char IR :1; /* Interrupt request bit */ + unsigned char :1; /* Nothing assigned */ + unsigned char :1; /* Nothing assigned */ + unsigned char :1; /* Nothing assigned */ + unsigned char :1; /* Nothing assigned */ + }BIT; + unsigned char BYTE; +}; + +/*------------------------------------------------------ + bcnic //0x004a +------------------------------------------------------*/ +union st_bcnic { /* interrupt control registers*/ + struct{ + unsigned char ILVL0_BCNIC:1;/* Interrupt priority level select bit */ + unsigned char ILVL1_BCNIC:1;/* Interrupt priority level select bit */ + unsigned char ILVL2_BCNIC:1;/* Interrupt priority level select bit */ + unsigned char IR_BCNIC :1;/* Interrupt request bit */ + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }BIT; + unsigned char BYTE; +}; + +/*------------------------------------------------------ + dm0ic //0x004b +------------------------------------------------------*/ +union st_dm0ic { /* interrupt control registers*/ + struct{ + unsigned char ILVL0_DM0IC:1;/* Interrupt priority level select bit */ + unsigned char ILVL1_DM0IC:1;/* Interrupt priority level select bit */ + unsigned char ILVL2_DM0IC:1;/* Interrupt priority level select bit */ + unsigned char IR_DM0IC :1;/* Interrupt request bit */ + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }BIT; + unsigned char BYTE; +}; + +/*------------------------------------------------------ + Flash identification register //0x01b4 +------------------------------------------------------*/ +union st_fidr { /* Flash identification register */ + struct{ + unsigned char FIDR0:1; /* Flash identification value */ + unsigned char FIDR1:1; /* Flash identification value */ + unsigned char :1; /* Nothing assigned */ + unsigned char :1; /* Nothing assigned */ + unsigned char :1; /* Nothing assigned */ + unsigned char :1; /* Nothing assigned */ + unsigned char :1; /* Nothing assigned */ + unsigned char :1; /* Nothing assigned */ + }BIT; + unsigned char BYTE; +}; + +/*------------------------------------------------------ + Flash memory control register 1 //0x01b5 +------------------------------------------------------*/ +union st_fmr1 { /* Flash identification register */ + struct{ + unsigned char :1; /* Reserved bit */ + unsigned char FMR11:1; /* EW1 mode select bit */ + unsigned char :1; /* Reserved bit */ + unsigned char :1; /* Reserved bit */ + unsigned char :1; /* Reserved bit */ + unsigned char :1; /* Reserved bit */ + unsigned char FMR16:1; /* Lock bit status flag */ + unsigned char :1; /* Reserved bit */ + }BIT; + unsigned char BYTE; +}; + +/*------------------------------------------------------ + Flash memory control register 0 //0x01b7 +------------------------------------------------------*/ +union st_fmr0 { /* Flash identification register */ + struct{ + unsigned char FMR00:1; /* RY/BY~ status flag */ + unsigned char FMR01:1; /* EW0 mode select bit */ + unsigned char FMR02:1; /* Lock bit disable bit */ + unsigned char FMSTP:1; /* Flash memory stop bit */ + unsigned char :1; /* Reserved bit */ + unsigned char FMR05:1; /* User ROM area select bit */ + unsigned char FMR06:1; /* Program status flag */ + unsigned char FMR07:1; /* Erase status flag */ + }BIT; + unsigned char BYTE; +}; + +/*------------------------------------------------------ + Address match interrupt register 2 //0x01b8 +-----------------------------------------------------*/ +union st_rmad2 { + struct{ + unsigned char RMAD2L; /* Address match interrupt register 2 low 8 bit */ + unsigned char RMAD2M; /* Address match interrupt register 2 mid 8 bit */ + unsigned char RMAD2H; /* Address match interrupt register 2 high 8 bit */ + unsigned char NC; /* non use */ + } BYTE; /* Byte access */ + unsigned long DWORD; /* Word Access */ +}; /* Address match interrupt register 2 32 bit */ + + +/*------------------------------------------------------ + Address match interrupt enable register 2 //0x01bb +------------------------------------------------------*/ +union st_aier2 { /* Address match interrupt enable register 2 */ + struct{ + unsigned char AIER20:1; /* Address match interrupt 2 enable bit */ + unsigned char AIER21:1; /* Address match interrupt 3 enable bit */ + unsigned char :1; /* Nothing assigned */ + unsigned char :1; /* Nothing assigned */ + unsigned char :1; /* Nothing assigned */ + unsigned char :1; /* Nothing assigned */ + unsigned char :1; /* Nothing assigned */ + unsigned char :1; /* Nothing assigned */ + }BIT; + unsigned char BYTE; +}; + +/*------------------------------------------------------ + Address match interrupt register 3 //0x01bc +-----------------------------------------------------*/ +union st_rmad3 { + struct{ + unsigned char RMAD3L; /* Address match interrupt register 3 low 8 bit */ + unsigned char RMAD3M; /* Address match interrupt register 3 mid 8 bit */ + unsigned char RMAD3H; /* Address match interrupt register 3 high 8 bit */ + unsigned char NC; /* non use */ + } BYTE; /* Byte access */ + unsigned long DWORD; /* Word Access */ +}; /* Address match interrupt register 3 32 bit */ + +/*------------------------------------------------------ + Peripheral clock select register //0x025e +------------------------------------------------------*/ +union st_pclkr { /* Peripheral clock select register */ + struct{ + unsigned char PCLK0 :1; /* TimerA,B clock select bit */ + unsigned char PCLK1 :1; /* SI/O clock select bit */ + unsigned char :1; /* Reserved bit,set to 0 */ + unsigned char :1; /* Reserved bit,set to 0 */ + unsigned char :1; /* Reserved bit,set to 0 */ + unsigned char :1; /* Reserved bit,set to 0 */ + unsigned char :1; /* Reserved bit,set to 0 */ + unsigned char :1; /* Reserved bit,set to 0 */ + }BIT; + unsigned char BYTE; +}; + +/*------------------------------------------------------ + Timer B3,4,5 Count start flag //0x0340 +------------------------------------------------------*/ +union st_tbsr { /* union tbsr */ + struct { /* Bit Access */ + unsigned char :1; /* Nothing Assigned */ + unsigned char :1; /* Nothing Assigned */ + unsigned char :1; /* Nothing Assigned */ + unsigned char :1; /* Nothing Assigned */ + unsigned char :1; /* Nothing Assigned */ + unsigned char TB3S:1; /* Timer B3 count start flag */ + unsigned char TB4S:1; /* Timer B4 count start flag */ + unsigned char TB5S:1; /* Timer B5 count start flag */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /* Timer B3,4,5 Count start flag */ + +/*------------------------------------------------------ + Three-phase PWM control regester 0 //0x0348 +------------------------------------------------------*/ +union st_invc0 { /* union invc0 */ + struct { /* Bit Access */ + unsigned char INV00:1;/* Effective interrupt output polarity select bit */ + unsigned char INV01:1;/* Effective interrupt output specification bit */ + unsigned char INV02:1;/* Mode select bit */ + unsigned char INV03:1;/* Output control bit */ + unsigned char INV04:1;/* Positive and negative phases concurrent L output disable function enable bit */ + unsigned char INV05:1;/* Positive and negative phases concurrent L output detect flag */ + unsigned char INV06:1;/* Modulation mode select bit */ + unsigned char INV07:1;/* Software trigger bit */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /* */ + +/*------------------------------------------------------ + Three-phase PWM control regester 1 //0x0349 +------------------------------------------------------*/ +union st_invc1 { /* union invc1 */ + struct { /* Bit Access */ + unsigned char INV10:1;/* Timer Ai start trigger signal select bit */ + unsigned char INV11:1;/* Timer A1-1,A2-1,A4-1 control bit */ + unsigned char INV12:1;/* Short circuit timer count source select bit*/ + unsigned char :1;/* Nothing Assigned */ + unsigned char :1;/* Reserved bit (always 0) */ + unsigned char :1;/* Nothing Assigned */ + unsigned char :1;/* Nothing Assigned */ + unsigned char :1;/* Nothing Assigned */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /* */ + +/*------------------------------------------------------ + Three-phase output buffer register 0 //0x034a +------------------------------------------------------*/ +union st_idb0 { /* union idb0 */ + struct { /* Bit Access */ + unsigned char DU0 :1;/* U phase output buffer 0 */ + unsigned char DUB0:1;/* U~ phase output buffer 0 */ + unsigned char DV0 :1;/* V phase output buffer 0 */ + unsigned char DVB0:1;/* V~ phase output buffer 0 */ + unsigned char DW0 :1;/* W phase output buffer 0 */ + unsigned char DWB0:1;/* W~ phase output buffer 0 */ + unsigned char :1;/* Nothing Assigned */ + unsigned char :1;/* Nothing Assigned */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /* */ + +/*------------------------------------------------------ + Three-phase output buffer register 1 //0x034b +------------------------------------------------------*/ +union st_idb1 { /* union idb1 */ + struct { /* Bit Access */ + unsigned char DU1 :1;/* U phase output buffer 1 */ + unsigned char DUB1:1;/* U~ phase output buffer 1 */ + unsigned char DV1 :1;/* V phase output buffer 1 */ + unsigned char DVB1:1;/* V~ phase output buffer 1 */ + unsigned char DW1 :1;/* W phase output buffer 1 */ + unsigned char DWB1:1;/* W~ phase output buffer 1 */ + unsigned char :1;/* Nothing Assigned */ + unsigned char :1;/* Nothing Assigned */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /* */ + +/*---------------------------------------------------------------------------------- + Timer mode registers //0x035b,0x035c,0x035d,0x0396, + 0x0397,0x0398,0x0399,0x039a,0x039b,0x039c +---------------------------------------------------------------------------------*/ +union st_tmr { /* union tmr */ + struct { /* Bit Access */ + unsigned char TMOD0:1; /* Operation mode select bit */ + unsigned char TMOD1:1; /* Operation mode select bit */ + unsigned char MR0 :1; /* Pulse output function select bit */ + unsigned char MR1 :1; /* External trigger select bit */ + unsigned char MR2 :1; /* Trigger select bit */ + unsigned char MR3 :1; /* Must always be "0" in one-shot timer*/ + unsigned char TCK0 :1; /* Count source select bit */ + unsigned char TCK1 :1; /* Count source select bit */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; + +/*------------------------------------------------------ + Interrupt request cause select register 2 //0x035e +------------------------------------------------------*/ +union st_ifsr2a { /* union ifsr2a */ + struct { /* Bit Access */ + unsigned char :1; /* Nothing assigned */ + unsigned char :1; /* Nothing assigned */ + unsigned char :1; /* Nothing assigned */ + unsigned char :1; /* Nothing assigned */ + unsigned char :1; /* Nothing assigned */ + unsigned char :1; /* Nothing assigned */ + unsigned char IFSR26 :1; /* Interrupt request cause select bit */ + unsigned char IFSR27 :1; /* Interrupt request cause select bit */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; + +/*------------------------------------------------------ +Interrupt request cause select register //0x035f +-----------------------------------------------------*/ +union st_ifsr { /* union IFSR */ + struct { /* Bit Access */ + unsigned char IFSR0:1; /* INT0~ interrupt polarity switching bit */ + unsigned char IFSR1:1; /* INT1~ interrupt polarity switching bit */ + unsigned char IFSR2:1; /* INT2~ interrupt polarity switching bit */ + unsigned char IFSR3:1; /* INT3~ interrupt polarity switching bit */ + unsigned char IFSR4:1; /* INT4~ interrupt polarity switching bit */ + unsigned char IFSR5:1; /* INT5~ interrupt polarity switching bit */ + unsigned char IFSR6:1; /* Interrupt request cause select bit */ + unsigned char IFSR7:1; /* Interrupt request cause select bit */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /* */ + +/*------------------------------------------------------ + SI/O4 control registers //0x0360 +------------------------------------------------------*/ +union st_s4c { /* union S4C */ + struct { /* Bit Access */ + unsigned char SM40:1; /* Internal synchronous clock select bit */ + unsigned char SM41:1; /* Internal synchronous clock select bit */ + unsigned char SM42:1; /* Sout4 output disable bit */ + unsigned char SM43:1; /* SI/O4 port select bit */ + unsigned char SM44:1; /* CLK polarity select bit */ + unsigned char SM45:1; /* Transfer direction select bit */ + unsigned char SM46:1; /* Synchronous clock select bit */ + unsigned char SM47:1; /* Sout4 initial value set bit */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; + +/*------------------------------------------------------ + SI/O3 control registers //0x0362 +------------------------------------------------------*/ +union st_s3c { /* union S3C */ + struct { /* Bit Access */ + unsigned char SM30:1; /* Internal synchronous clock select bit */ + unsigned char SM31:1; /* Internal synchronous clock select bit */ + unsigned char SM32:1; /* Sout3 output disable bit */ + unsigned char SM33:1; /* SI/O3 port select bit */ + unsigned char SM34:1; /* CLK polarity select bit */ + unsigned char SM35:1; /* Transfer direction select bit */ + unsigned char SM36:1; /* Synchronous clock select bit */ + unsigned char SM37:1; /* Sout3 initial value set bit */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /* */ + +/*------------------------------------------------------ + UART0 special mode register 4 //0x036c +------------------------------------------------------*/ +union st_u0smr4 { /* union u0smr4 */ + struct { /* Bit Access */ + unsigned char STAREQ :1; /* Start condition generate bit */ + unsigned char RSTAREQ:1; /* Restart condition generate bit */ + unsigned char STPREQ :1; /* Stop condition generate bit */ + unsigned char STSPSEL:1; /* SCL,SDA output select bit */ + unsigned char ACKD :1; /* ACK data bit */ + unsigned char ACKC :1; /* ACK data output enable bit */ + unsigned char SCLHI :1; /* SCL output stop enable bit */ + unsigned char SWC9 :1; /* Final bit L hold enable bit */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /* */ + +/*------------------------------------------------------ + UART0 special mode register 3 //0x036d +------------------------------------------------------*/ +union st_u0smr3 { /* union u0smr3 */ + struct { /* Bit Access */ + unsigned char :1; /* Nothing is assigned */ + unsigned char CKPH :1; /* Clock phase set bit */ + unsigned char :1; /* Nothing is assigned */ + unsigned char NODC :1; /* Clock output set bit */ + unsigned char :1; /* Nothing is assigned */ + unsigned char DL0 :1; /* SDA0(TxD0) digital delay setup bit */ + unsigned char DL1 :1; /* SDA0(TxD0) digital delay setup bit */ + unsigned char DL2 :1; /* SDA0(TxD0) digital delay setup bit */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /* */ + +/*------------------------------------------------------ + UART0 special mode register 2 //0x036e +------------------------------------------------------*/ +union st_u0smr2 { /* union u0smr2 */ + struct { /* Bit Access */ + unsigned char IICM2 :1; /* IIC mode selection bit 2 */ + unsigned char CSC :1; /* Clock-synchronous bit */ + unsigned char SWC :1; /* SCL wait output bit */ + unsigned char ALS :1; /* SDA output stop bit */ + unsigned char STAC :1; /* UART0 initialization bit */ + unsigned char SWC2 :1; /* SCL wait output bit 2 */ + unsigned char SDHI :1; /* SDA output disable bit */ + unsigned char :1; /* Nothing is assigned */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /* */ + +/*------------------------------------------------------ + UART0 special mode register //0x036f +------------------------------------------------------*/ +union st_u0smr { /* union u0smr */ + struct { /* Bit Access */ + unsigned char IICM:1; /* IIC mode selection bit */ + unsigned char ABC :1; /* Arbitration lost detecting flag control bit */ + unsigned char BBS :1; /* Bus busy flag */ + unsigned char :1; /* Reserved bit,set to 0 */ + unsigned char ABSC:1; /* Bus collision detect sampling clock select bit */ + unsigned char ACSE:1; /* Auto clear function select bit of transmit enable bit */ + unsigned char SSS :1; /* Transmit start condition select bit */ + unsigned char :1; /* Nothing is assigned */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /* */ + +/*------------------------------------------------------ + UART1 special mode register 4 //0x0370 +------------------------------------------------------*/ +union st_u1smr4 { /* union u1smr4 */ + struct { /* Bit Access */ + unsigned char STAREQ:1; /* Start condition generate bit */ + unsigned char RSTARE:1; /* Restart condition generate bit */ + unsigned char STPREQ:1; /* Stop condition generate bit */ + unsigned char STSPSE:1; /* SCL,SDA output select bit */ + unsigned char ACKD :1; /* ACK data bit */ + unsigned char ACKC :1; /* ACK data output enable bit */ + unsigned char SCLHI :1; /* SCL output stop enable bit */ + unsigned char SWC9 :1; /* Final bit L hold enable bit */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /* */ + +/*------------------------------------------------------ + UART1 special mode register 3 //0x0371 +------------------------------------------------------*/ +union st_u1smr3 { /* union u1smr3 */ + struct { /* Bit Access */ + unsigned char :1; /* Nothing is assigned */ + unsigned char CKPH :1; /* Clock phase set bit */ + unsigned char :1; /* Nothing is assigned */ + unsigned char NODC :1; /* Clock output set bit */ + unsigned char :1; /* Nothing is assigned */ + unsigned char DL0 :1; /* SDA1(TxD1) digital delay setup bit */ + unsigned char DL1 :1; /* SDA1(TxD1) digital delay setup bit */ + unsigned char DL2 :1; /* SDA1(TxD1) digital delay setup bit */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /* */ + +/*------------------------------------------------------ + UART1 special mode register 2 //0x0372 +------------------------------------------------------*/ +union st_u1smr2 { /* union u1smr2 */ + struct { /* Bit Access */ + unsigned char IICM2 :1; /* IIC mode selection bit 2 */ + unsigned char CSC :1; /* Clock-synchronous bit */ + unsigned char SWC :1; /* SCL wait output bit */ + unsigned char ALS :1; /* SDA output stop bit */ + unsigned char STAC :1; /* UART0 initialization bit */ + unsigned char SWC2 :1; /* SCL wait output bit 2 */ + unsigned char SDHI :1; /* SDA output disable bit */ + unsigned char :1; /* Nothing is assigned */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /* */ + +/*------------------------------------------------------ + UART1 special mode register //0x0373 +------------------------------------------------------*/ +union st_u1smr { /* union u1smr */ + struct { /* Bit Access */ + unsigned char IICM:1; /* IIC mode selection bit */ + unsigned char ABC :1; /* Arbitration lost detecting flag control bit */ + unsigned char BBS :1; /* Bus busy flag */ + unsigned char :1; /* Reserved bit,set to 0 */ + unsigned char ABSC:1; /* Bus collision detect sampling clock select bit */ + unsigned char ACSE:1; /* Auto clear function select bit of transmit enable bit */ + unsigned char SSS :1; /* Transmit start condition select bit */ + unsigned char :1; /* Nothing is assigned */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /* */ + +/*------------------------------------------------------ + UART2 special mode register 4 //0x0374 +------------------------------------------------------*/ +union st_u2smr4 { /* union u1smr4 */ + struct { /* Bit Access */ + unsigned char STAREQ:1; /* Start condition generate bit */ + unsigned char RSTARE:1; /* Restart condition generate bit */ + unsigned char STPREQ:1; /* Stop condition generate bit */ + unsigned char STSPSE:1; /* SCL,SDA output select bit */ + unsigned char ACKD :1; /* ACK data bit */ + unsigned char ACKC :1; /* ACK data output enable bit */ + unsigned char SCLHI :1; /* SCL output stop enable bit */ + unsigned char SWC9 :1; /* Final bit L hold enable bit */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /* */ + +/*------------------------------------------------------ + UART2 special mode register 3 //0x0375 +------------------------------------------------------*/ +union st_u2smr3 { /* union U2SMR3 */ + struct { /* Bit Access */ + unsigned char :1; /* Nothing is assigned */ + unsigned char CKPH :1; /* Clock phase set bit */ + unsigned char :1; /* Nothing is assigned */ + unsigned char NODC :1; /* Clock output set bit */ + unsigned char :1; /* Nothing is assigned */ + unsigned char DL0 :1; /* SDA digital delay setup bit */ + unsigned char DL1 :1; /* SDA digital delay setup bit */ + unsigned char DL2 :1; /* SDA digital delay setup bit */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /* */ + +/*------------------------------------------------------ + UART2 special mode register 2 //0x0376 +------------------------------------------------------*/ +union st_u2smr2 { /* union U2SMR2 */ + struct { /* Bit Access */ + unsigned char IICM2:1; /* IIC mode selection bit 2 */ + unsigned char CSC :1; /* Clock-synchronous bit */ + unsigned char SWC :1; /* SCL wait output bit */ + unsigned char ALS :1; /* SDA output stop bit */ + unsigned char STAC :1; /* UART2 initialization bit */ + unsigned char SWC2 :1; /* SCL wait output bit 2 */ + unsigned char SDHI :1; /* SDA output disable bit */ + unsigned char :1; /* Nothing is assigned */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /* */ + +/*------------------------------------------------------ + UART2 special mode register //0x0377 +------------------------------------------------------*/ +union st_u2smr { /* union U2SMR */ + struct { /* Bit Access */ + unsigned char IICM :1; /* IIC mode selection bit */ + unsigned char ABC :1; /* Arbitration lost detecting flag control bit */ + unsigned char BBS :1; /* Reserved bit,set to 0 */ + unsigned char :1; /* SCLL sync output enable bit */ + unsigned char ABSCS:1; /* Bus collision detect sampling clock select bit */ + unsigned char ACSE :1; /* Auto clear function select bit of transmit enable bit */ + unsigned char SSS :1; /* Transmit start condition select bit */ + unsigned char :1; /* Nothing is assigned */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /* */ + +/*------------------------------------------------------ + UART2 transmit/receive mode register //0x0378 +------------------------------------------------------*/ +union st_u2mr { /* union U2MR */ + struct { /* Bit Access */ + unsigned char SMD0_U2MR :1; /* Serial I/O mode select bit */ + unsigned char SMD1_U2MR :1; /* Serial I/O mode select bit */ + unsigned char SMD2_U2MR :1; /* Serial I/O mode select bit */ + unsigned char CKDIR_U2MR:1; /* Internal/external clock select bit */ + unsigned char STPS_U2MR :1; /* Stop bit length select bit */ + unsigned char PRY_U2MR :1; /* Odd/even parity select bit */ + unsigned char PRYE_U2MR :1; /* Parity enable bit */ + unsigned char IOPOL_U2MR:1; /* TxD RxD I/O polarity reverse bit */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; + +/*------------------------------------------------------ + UART2 Transmit buffer register 16 bit //0x037a +------------------------------------------------------*/ +union st_u2tb { /* UART2 Transmit buffer register 16 bit ; Use "MOV" instruction when writing to this register. */ + struct{ + unsigned char U2TBL; /* UART2 Transmit buffer register low 8 bit */ + unsigned char U2TBH; /* UART2 Transmit buffer register high 8 bit */ + } BYTE; /* Byte access */ + unsigned short WORD; /* Word Access */ +}; + +/*------------------------------------------------------ + UART2 transmit/receive control register 0//0x037c +------------------------------------------------------*/ +union st_u2c0 { /* union U2C0 */ + struct { /* Bit Access */ + unsigned char CLK0 :1; /* BRG count source select bit */ + unsigned char CLK1 :1; /* BRG count source select bit */ + unsigned char CRS :1; /* CTS~/RTS~ function select bit */ + unsigned char TXEPT:1; /* Transmit register empty flag */ + unsigned char CRD :1; /* CTS~/RTS~ disable bit */ + unsigned char :1; /* Nothing Assigned */ + unsigned char CKPOL:1; /* CLK polarity select bit */ + unsigned char UFORM:1; /* Transfer format select bit */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /* UART2 transmit/receive control register 0*/ + +/*------------------------------------------------------ + UART2 transmit/receive control register 1 //0x037d +-----------------------------------------------------*/ +union st_u2c1 { /* union U2C1 */ + struct { /* Bit Access */ + unsigned char TE_U2C1:1; /* Transmit enable bit */ + unsigned char TI_U2C1:1; /* Transmit buffer empty flag */ + unsigned char RE_U2C1:1; /* Receive enable bit */ + unsigned char RI_U2C1:1; /* Receive complete flag */ + unsigned char U2IRS :1; /* UART2 transmit interrupt cause select bit*/ + unsigned char U2RRM :1; /* UART2 continuous receive mode enable bit */ + unsigned char U2LCH :1; /* Data logic select bit */ + unsigned char U2ERE :1; /* Error signal output enable bit */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /*UART2 transmit/receive control register 1 */ + +/*------------------------------------------------------ + UART2 receive buffer registers //0x037e +------------------------------------------------------*/ +union st_u2rb { /* UART2 receive buffer register */ + struct { /* Bit Access */ + unsigned char :1; /* Receive data */ + unsigned char :1; /* Receive data */ + unsigned char :1; /* Receive data */ + unsigned char :1; /* Receive data */ + unsigned char :1; /* Receive data */ + unsigned char :1; /* Receive data */ + unsigned char :1; /* Receive data */ + unsigned char :1; /* Receive data */ + unsigned char :1; /* Receive data */ + unsigned char :1; /* Nothing assigned */ + unsigned char :1; /* Nothing assigned */ + unsigned char ABT_U2RB:1; /* Arbitration lost detecting flag */ + unsigned char OER_U2RB:1; /* Overrun error flag */ + unsigned char FER_U2RB:1; /* Framing error flag */ + unsigned char PER_U2RB:1; /* Parity error flag */ + unsigned char SUM_U2RB:1; /* Error sum flag */ + }BIT; + struct{ + unsigned char U2RBL; /* Low 8 bit */ + unsigned char U2RBH; /* High 8 bit */ + }BYTE; + unsigned short WORD; +}; + +/*------------------------------------------------------ + Count start flag //0x0380 +------------------------------------------------------*/ +union st_tabsr { /* union TABSR */ + struct { /* Bit Access */ + unsigned char TA0S:1; /* Timer A0 count start flag */ + unsigned char TA1S:1; /* Timer A1 count start flag */ + unsigned char TA2S:1; /* Timer A2 count start flag */ + unsigned char TA3S:1; /* Timer A3 count start flag */ + unsigned char TA4S:1; /* Timer A4 count start flag */ + unsigned char TB0S:1; /* Timer B0 count start flag */ + unsigned char TB1S:1; /* Timer B1 count start flag */ + unsigned char TB2S:1; /* Timer B2 count start flag */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /*UART2 transmit/receive control register 1 */ + +/*------------------------------------------------------ + Clock prescaler reset flag //0x0381 +------------------------------------------------------*/ +union st_cpsrf { /* union CPSRF */ +struct { /* Bit Access */ + unsigned char :1; /* */ + unsigned char :1; /* */ + unsigned char :1; /* */ + unsigned char :1; /* */ + unsigned char :1; /* */ + unsigned char :1; /* */ + unsigned char :1; /* */ + unsigned char CPSR:1; /* Clock prescaler reset flag */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /* Watchdog timer start register */ + +/*------------------------------------------------------ + One-shot start flag //0x0382 +------------------------------------------------------*/ +union st_onsf { /* union ONSF */ + struct { /* Bit Access */ + unsigned char TA0OS:1; /* Timer A0 one-shot start flag */ + unsigned char TA1OS:1; /* Timer A1 one-shot start flag */ + unsigned char TA2OS:1; /* Timer A2 one-shot start flag */ + unsigned char TA3OS:1; /* Timer A3 one-shot start flag */ + unsigned char TA4OS:1; /* Timer A4 one-shot start flag */ + unsigned char TAZIE:1; /* Z phase input enable bit */ + unsigned char TA0TGL:1; /* Timer A0 event/trigger select bit */ + unsigned char TA0TGH:1; /* Timer A0 event/trigger select bit */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /*UART2 transmit/receive control register 1 */ + +/*------------------------------------------------------ + Trigger select register //0x0383 +------------------------------------------------------*/ +union st_trgsr { /* union TRGSR */ + struct { /* Bit Access */ + unsigned char TA1TGL:1; /* Timer A1 event/trigger select bit */ + unsigned char TA1TGH:1; /* Timer A1 event/trigger select bit */ + unsigned char TA2TGL:1; /* Timer A2 event/trigger select bit */ + unsigned char TA2TGH:1; /* Timer A2 event/trigger select bit */ + unsigned char TA3TGL:1; /* Timer A3 event/trigger select bit */ + unsigned char TA3TGH:1; /* Timer A3 event/trigger select bit */ + unsigned char TA4TGL:1; /* Timer A4 event/trigger select bit */ + unsigned char TA4TGH:1; /* Timer A4 event/trigger select bit */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /*UART2 transmit/receive control register 1 */ + +/*------------------------------------------------------ + Timer B2 special mode register //0x039e +------------------------------------------------------*/ +union st_tb2sc { /* union tb2sc */ + struct { /* Bit Access */ + unsigned char PWCON :1; /* Timer B2 reload timing switching bit */ + unsigned char IVPCR1:1; /* Three phase output port NMI control bit 1 */ + unsigned char :1; /* Nothing is assigned */ + unsigned char :1; /* Nothing is assigned */ + unsigned char :1; /* Nothing is assigned */ + unsigned char :1; /* Nothing is assigned */ + unsigned char :1; /* Nothing is assigned */ + unsigned char :1; /* Nothing is assigned */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /*UART2 transmit/receive control register 1 */ + +/*------------------------------------------------------ + UART0 transmit/receive mode register //0x03a0 +------------------------------------------------------*/ +union st_u0mr { /* union U0MR */ + struct { /* Bit Access */ + unsigned char SMD0_U0MR :1; /* Serial I/O mode select bit */ + unsigned char SMD1_U0MR :1; /* Serial I/O mode select bit */ + unsigned char SMD2_U0MR :1; /* Serial I/O mode select bit */ + unsigned char CKDIR_U0MR:1; /* Internal/external clock select bit */ + unsigned char STPS_U0MR :1; /* Stop bit length select bit */ + unsigned char PRY_U0MR :1; /* Odd/even parity select bit */ + unsigned char PRYE_U0MR :1; /* Parity enable bit */ + unsigned char IOPOL_U0MR :1; /* TxD,RxD I/O polarity reverse bit */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; + +/*------------------------------------------------------ + UART0 transmit/receive mode register //0x03a2 +------------------------------------------------------*/ +union st_u0tb { /* UART0 Transmit buffer register 16 bit ; Use "MOV" instruction when writing to this register. */ + struct{ + unsigned char U0TBL; /* UART0 Transmit buffer register low 8 bit */ + unsigned char U0TBH; /* UART0 Transmit buffer register high 8 bit */ + } BYTE; /* Byte access */ + unsigned short WORD; /* Word Access */ +}; + +/*------------------------------------------------------ + UARTi transmit/receive control register 0 //0x03a4 +------------------------------------------------------*/ +union st_u0c0 { /* union U0C0 */ + struct { /* Bit Access */ + unsigned char CLK0 :1; /* BRG count source select bit */ + unsigned char CLK1 :1; /* BRG count source select bit */ + unsigned char CRS :1; /* CTS~/RTS~ function select bit */ + unsigned char TXEPT:1; /* Transmit register empty flag */ + unsigned char CRD :1; /* CTS~/RTS~ disable bit */ + unsigned char NCH :1; /* Data output select bit */ + unsigned char CKPOL:1; /* CLK polarity select bit */ + unsigned char UFORM:1; /* Transfer format select bit */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /*UARTi transmit/receive control register 0 */ + +/*------------------------------------------------------ + UART0 transmit/receive control register 1 //0x03a5 +------------------------------------------------------*/ +union st_u0c1 { /* union U0C1 */ + struct { /* Bit Access */ + unsigned char TE :1; /* Transmit enable bit */ + unsigned char TI :1; /* Transmit buffer empty flag */ + unsigned char RE :1; /* Receive enable bit */ + unsigned char RI :1; /* Receive complete flag */ + unsigned char :1; /* Nothing Assigned */ + unsigned char :1; /* Nothing Assigned */ + unsigned char U0LCH :1; /* Data logic select bit */ + unsigned char U0ERE :1; /* Error signal output enable bit */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /*UART0 transmit/receive control register 1 */ + +/*------------------------------------------------------ + UART0 receive buffer register //0x03a6 +------------------------------------------------------*/ +union st_u0rb { /* UART0 receive buffer register */ + struct { /* Bit Access */ + unsigned char :1; /* Receive data */ + unsigned char :1; /* Receive data */ + unsigned char :1; /* Receive data */ + unsigned char :1; /* Receive data */ + unsigned char :1; /* Receive data */ + unsigned char :1; /* Receive data */ + unsigned char :1; /* Receive data */ + unsigned char :1; /* Receive data */ + unsigned char :1; /* Receive data */ + unsigned char :1; /* Nothing assigned */ + unsigned char :1; /* Nothing assigned */ + unsigned char ABT_U0RB:1; /* Arbitration lost detecting flag */ + unsigned char OER_U0RB:1; /* Overrun error flag */ + unsigned char FER_U0RB:1; /* Framing error flag */ + unsigned char PER_U0RB:1; /* Parity error flag */ + unsigned char SUM_U0RB:1; /* Error sum flag */ + }BIT; + struct{ + unsigned char U0RBL; /* Low 8 bit */ + unsigned char U0RBH; /* High 8 bit */ + }BYTE; + unsigned short WORD; +}; + +/*------------------------------------------------------ + UART1 transmit/receive mode register //0x03a8 +------------------------------------------------------*/ +union st_u1mr { /* union U1MR */ + struct { /* Bit Access */ + unsigned char SMD0_U1MR :1; /* Serial I/O mode select bit */ + unsigned char SMD1_U1MR :1; /* Serial I/O mode select bit */ + unsigned char SMD2_U1MR :1; /* Serial I/O mode select bit */ + unsigned char CKDIR_U1MR :1; /* Internal/external clock select bit */ + unsigned char STPS_U1MR :1; /* Stop bit length select bit */ + unsigned char PRY_U1MR :1; /* Odd/even parity select bit */ + unsigned char PRYE_U1MR :1; /* Parity enable bit */ + unsigned char IOPOL_U1MR :1; /* TxD,RxD I/O polarity reverse bit */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; + +/*------------------------------------------------------ + UART1 transmit buffer register //0x03aa +------------------------------------------------------*/ +union st_u1tb { /* UART1 Transmit buffer register 16 bit ; Use "MOV" instruction when writing to this register. */ + struct{ + unsigned char U1TBL; /* UART1 Transmit buffer register low 8 bit */ + unsigned char U1TBH; /* UART1 Transmit buffer register high 8 bit */ + } BYTE; /* Byte access */ + unsigned short WORD; /* Word Access */ +}; + +/*------------------------------------------------------ + UART1 transmit/receive control register 0 //0x03ac +------------------------------------------------------*/ +union st_u1c0 { /* union UCR */ + struct { /* Bit Access */ + unsigned char CLK0 :1; /* BRG count source select bit */ + unsigned char CLK1 :1; /* BRG count source select bit */ + unsigned char CRS :1; /* CTS~/RTS~ function select bit */ + unsigned char TXEPT:1; /* Transmit register empty flag */ + unsigned char CRD :1; /* CTS~/RTS~ disable bit */ + unsigned char NCH :1; /* Data output select bit */ + unsigned char CKPOL:1; /* CLK polarity select bit */ + unsigned char UFORM:1; /* Transfer format select bit */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /*UARTi transmit/receive control register 0 */ + +/*------------------------------------------------------ + UART1 transmit/receive control register 1 //0x03ad +------------------------------------------------------*/ +union st_u1c1 { /* union U1C1 */ + struct { /* Bit Access */ + unsigned char TE:1; /* Transmit enable bit */ + unsigned char TI:1; /* Transmit buffer empty flag */ + unsigned char RE:1; /* Receive enable bit */ + unsigned char RI:1; /* Receive complete flag */ + unsigned char :1; /* */ + unsigned char :1; /* */ + unsigned char :1; /* */ + unsigned char :1; /* */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /*UART1 transmit/receive control register 1 */ + +/*------------------------------------------------------ + UART1 receive buffer register //0x03ae +------------------------------------------------------*/ +union st_u1rb { /* UART1 receive buffer register */ + struct { /* Bit Access */ + unsigned char :1; /* Receive data */ + unsigned char :1; /* Receive data */ + unsigned char :1; /* Receive data */ + unsigned char :1; /* Receive data */ + unsigned char :1; /* Receive data */ + unsigned char :1; /* Receive data */ + unsigned char :1; /* Receive data */ + unsigned char :1; /* Receive data */ + unsigned char :1; /* Receive data */ + unsigned char :1; /* Nothing assigned */ + unsigned char :1; /* Nothing assigned */ + unsigned char ABT_U1RB:1; /* Arbitration lost detecting flag */ + unsigned char OER_U1RB:1; /* Overrun error flag */ + unsigned char FER_U1RB:1; /* Framing error flag */ + unsigned char PER_U1RB:1; /* Parity error flag */ + unsigned char SUM_U1RB:1; /* Error sum flag */ + }BIT; + struct{ + unsigned char U1RBL; /* Low 8 bit */ + unsigned char U1RBH; /* High 8 bit */ + }BYTE; + unsigned short WORD; +}; + +/*------------------------------------------------------ + UART transmit/receive control register 2 //0x03b0 +------------------------------------------------------*/ +union st_ucon { /* union UCON */ + struct { /* Bit Access */ + unsigned char U0IRS :1; /* UART0 transmit interrupt cause select bit*/ + unsigned char U1IRS :1; /* UART1 transmit interrupt cause select bit*/ + unsigned char U0RRM :1; /* UART0 continuous receive mode enable bit */ + unsigned char U1RRM :1; /* UART1 continuous receive mode enable bit */ + unsigned char CLKMD0:1; /* CLK/CLKS select bit 0 */ + unsigned char CLKMD1:1; /* CLK/CLKS select bit 1 */ + unsigned char RCSP :1; /* Separate CTS~/RTS~ bit */ + unsigned char :1; /* */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /*UART transmit/receive control register 2 */ + +/*------------------------------------------------------ + DMA0 request cause select register //0x03b8 +------------------------------------------------------*/ +union st_dm0sl { /* DMAi request cause select registers */ + struct{ + unsigned char DSEL0:1;/* DMA request cause select bit */ + unsigned char DSEL1:1;/* DMA request cause select bit */ + unsigned char DSEL2:1;/* DMA request cause select bit */ + unsigned char DSEL3:1;/* DMA request cause select bit */ + unsigned char :1; + unsigned char :1; + unsigned char DMS :1;/* DMA request cause expansion bit */ + unsigned char DSR :1;/* Software DMA request bit */ + }BIT; + unsigned char BYTE; +}; + +/*------------------------------------------------------ + DMA1 request cause select register //0x03ba +------------------------------------------------------*/ +union st_dm1sl { /* DMAi request cause select registers */ + struct{ + unsigned char DSEL0:1; /* DMA request cause select bit */ + unsigned char DSEL1:1; /* DMA request cause select bit */ + unsigned char DSEL2:1; /* DMA request cause select bit */ + unsigned char DSEL3:1; /* DMA request cause select bit */ + unsigned char :1; + unsigned char :1; + unsigned char DMS :1; /* DMA request cause expansion bit */ + unsigned char DSR :1; /* Software DMA request bit */ + }BIT; + unsigned char BYTE; +}; + +/*------------------------------------------------------ + CRC data register //0x03bc +------------------------------------------------------*/ +union st_crcd { /* CRC data register 16 bit */ + struct{ + unsigned char CRCDL; /* CRC data register low 8 bit */ + unsigned char CRCDH; /* CRC data register high 8 bit */ + } BYTE; /* Byte access */ + unsigned short WORD; /* Word Access */ +}; + +/*------------------------------------------------------ + A/D register 0 //0x03c0 +------------------------------------------------------*/ +union st_ad0 { /* A/D register 0 16 bit */ + struct{ + unsigned char AD0L; /* A/D register 0 low 8 bit */ + unsigned char AD0H; /* A/D register 0 high 8 bit */ + }BYTE; /* Byte access */ + unsigned short WORD; /* Word Access */ +}; + +/*------------------------------------------------------ + A/D register 1 //0x03c2 +------------------------------------------------------*/ + union st_ad1 { /* A/D register 1 16 bit */ + struct{ + unsigned char AD1L; /* A/D register 1 low 8 bit */ + unsigned char AD1H; /* A/D register 1 high 8 bit */ + } BYTE; /* Byte access */ + unsigned short WORD; /* Word Access */ +}; + +/*------------------------------------------------------ + A/D register 2 //0x03c4 +------------------------------------------------------*/ +union st_ad2 { /* A/D register 2 16 bit */ + struct{ + unsigned char AD2L; /* A/D register 2 low 8 bit */ + unsigned char AD2H; /* A/D register 2 high 8 bit */ + } BYTE; /* Byte access */ + unsigned short WORD; /* Word Access */ +}; + +/*------------------------------------------------------ + A/D register 3 //0x03c6 +------------------------------------------------------*/ +union st_ad3 { /* A/D register 3 16 bit */ + struct{ + unsigned char AD3L; /* A/D register 3 low 8 bit */ + unsigned char AD3H; /* A/D register 3 high 8 bit */ + } BYTE; /* Byte access */ + unsigned short WORD; /* Word Access */ +}; + +/*------------------------------------------------------ + A/D register 4 //0x03c8 +------------------------------------------------------*/ +union st_ad4 { /* A/D register 4 16 bit */ + struct{ + unsigned char AD4L; /* A/D register 4 low 8 bit */ + unsigned char AD4H; /* A/D register 4 high 8 bit */ + } BYTE; /* Byte access */ + unsigned short WORD; /* Word Access */ +}; + +/*------------------------------------------------------ + A/D register 5 //0x03ca +------------------------------------------------------*/ +union st_ad5 { /* A/D register 5 16 bit */ + struct{ + unsigned char AD5L; /* A/D register 5 low 8 bit */ + unsigned char AD5H; /* A/D register 5 high 8 bit */ + } BYTE; /* Byte access */ + unsigned short WORD; /* Word Access */ +}; + +/*------------------------------------------------------ + A/D register 6 //0x03cc +------------------------------------------------------*/ +union st_ad6 { /* A/D register 6 16 bit */ + struct{ + unsigned char AD6L; /* A/D register 6 low 8 bit */ + unsigned char AD6H; /* A/D register 6 high 8 bit */ + } BYTE; /* Byte access */ + unsigned short WORD; /* Word Access */ + }; + +/*------------------------------------------------------ + A/D register 7 //0x03ce +------------------------------------------------------*/ +union st_ad7 { /* A/D register 7 16 bit */ + struct{ + unsigned char AD7L; /* A/D register 7 low 8 bit */ + unsigned char AD7H; /* A/D register 7 high 8 bit */ + } BYTE; /* Byte access */ + unsigned short WORD; /* Word Access */ + }; + +/*------------------------------------------------------ + A/D control register 2 //0x03d4 +------------------------------------------------------*/ +union st_adcon2 { /* union ADCON2 */ + struct { /* Bit Access */ + unsigned char SMP :1; /* A/D conversion method select bit */ + unsigned char ADGSEL0 :1; /* Reserved bit (Always set to 0 ) */ + unsigned char ADGSEL1 :1; /* Reserved bit (Always set to 0 ) */ + unsigned char :1; /* Reserved bit (Always set to 0 ) */ + unsigned char CKS2 :1; /* Nothing Assigned. */ + unsigned char :1; /* Nothing Assigned. */ + unsigned char :1; /* Nothing Assigned. */ + unsigned char :1; /* Nothing Assigned. */ + } BIT; + unsigned char BYTE; /* Byte Access */ +}; + +/*------------------------------------------------------ + A/D control register 0 //0x03d6 +------------------------------------------------------*/ +union st_adcon0 { /* union ADCON0 */ + struct { /* Bit Access */ + unsigned char CH0 :1; /* Analog input pin select bit */ + unsigned char CH1 :1; /* Analog input pin select bit */ + unsigned char CH2 :1; /* Analog input pin select bit */ + unsigned char MD0 :1; /* A/D operation mode select bit 0 */ + unsigned char MD1 :1; /* A/D operation mode select bit 0 */ + unsigned char TRG :1; /* Trigger select bit */ + unsigned char ADST:1; /* A/D conversion start flag */ + unsigned char CKS0:1; /* Frequency select bit 0 */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /*A/D control register 0 */ + + +/*------------------------------------------------------ + A/D control register 1 //0x03d7 +------------------------------------------------------*/ +union st_adcon1 { /* union ADCON1 */ + struct { /* Bit Access */ + unsigned char SCAN0:1; /* A/D sweep pin select bit */ + unsigned char SCAN1:1; /* A/D sweep pin select bit */ + unsigned char MD2 :1; /* A/D operation mode select bit 1 */ + unsigned char BITS :1; /* 8/10-bit mode select bit */ + unsigned char CKS1 :1; /* Frequency select bit 1 */ + unsigned char VCUT :1; /* Vref connect bit */ + unsigned char OPA0 :1; /* External op-amp connection mode bit */ + unsigned char OPA1 :1; /* External op-amp connection mode bit */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /*A-D control register 1 */ + + +/*------------------------------------------------------ + D/A control register //0x03dc +------------------------------------------------------*/ +union st_dacon{ /* union DACON */ + struct { /* Bit Access */ + unsigned char DA0E :1; /* D/A0 output enable bit */ + unsigned char DA1E :1; /* D/A1 output enable bit */ + unsigned char :1; /* Nothing Assigned */ + unsigned char :1; /* Nothing Assigned */ + unsigned char :1; /* Nothing Assigned */ + unsigned char :1; /* Nothing Assigned */ + unsigned char :1; /* Nothing Assigned */ + unsigned char :1; /* Nothing Assigned */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /* D/A control register */ + +/*------------------------------------------------------ + Port P14 control register //0x03de +------------------------------------------------------*/ +union st_pc14{ /* union pc14 */ + struct { /* Bit Access */ + unsigned char P140 :1; /* Port P14_0 register */ + unsigned char P141 :1; /* Port P14_1 register */ + unsigned char :1; /* Nothing Assigned */ + unsigned char :1; /* Nothing Assigned */ + unsigned char pd140:1; /* Port P14_0 direction register */ + unsigned char pd141:1; /* Port P14_1 direction register */ + unsigned char :1; /* Nothing Assigned */ + unsigned char :1; /* Nothing Assigned */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /* Port P14 control register */ + +/*------------------------------------------------------ + Pull-up control register 3 //0x03df +------------------------------------------------------*/ +union st_pur3{ /* union pur3 */ + struct { /* Bit Access */ + unsigned char PU30:1; /* P11_0 to P11_3 pull-up */ + unsigned char PU31:1; /* P11_4 to P11_7 pull-up */ + unsigned char PU32:1; /* P12_0 to P12_3 pull-up */ + unsigned char PU33:1; /* P12_4 to P12_7 pull-up */ + unsigned char PU34:1; /* P13_0 to P13_3 pull-up */ + unsigned char PU35:1; /* P13_4 to P13_7 pull-up */ + unsigned char PU36:1; /* P14_0,P14_1 pull-up */ + unsigned char PU37:1; /* P11 to P14 effective bit */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /* Pull-up control register 3 */ + +/*------------------------------------------------------ + Port P0 register //0x03e0 +------------------------------------------------------*/ +union st_p0 { /* union P0 */ + struct { /* Bit Access */ + unsigned char P0_0:1; /* Port P00 register */ + unsigned char P0_1:1; /* Port P01 register */ + unsigned char P0_2:1; /* Port P02 register */ + unsigned char P0_3:1; /* Port P03 register */ + unsigned char P0_4:1; /* Port P04 register */ + unsigned char P0_5:1; /* Port P05 register */ + unsigned char P0_6:1; /* Port P06 register */ + unsigned char P0_7:1; /* Port P07 register */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /* */ + +/*------------------------------------------------------ + Port P1 register //0x03e1 +------------------------------------------------------*/ +union st_p1 { /* union P1 */ + struct { /* Bit Access */ + unsigned char P1_0:1;/* Port P10 register */ + unsigned char P1_1:1;/* Port P11 register */ + unsigned char P1_2:1;/* Port P12 register */ + unsigned char P1_3:1;/* Port P13 register */ + unsigned char P1_4:1;/* Port P14 register */ + unsigned char P1_5:1;/* Port P15 register */ + unsigned char P1_6:1;/* Port P16 register */ + unsigned char P1_7:1;/* Port P17 register */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /* */ + +/*------------------------------------------------------ + Port P0 direction register //0x03e2 +------------------------------------------------------*/ +union st_pd0 { /* union PD0 */ + struct { /* Bit Access */ + unsigned char PD0_0:1;/* Port P00 direction register */ + unsigned char PD0_1:1;/* Port P01 direction register */ + unsigned char PD0_2:1;/* Port P02 direction register */ + unsigned char PD0_3:1;/* Port P03 direction register */ + unsigned char PD0_4:1;/* Port P04 direction register */ + unsigned char PD0_5:1;/* Port P05 direction register */ + unsigned char PD0_6:1;/* Port P06 direction register */ + unsigned char PD0_7:1;/* Port P07 direction register */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /* */ + + +/*------------------------------------------------------ + Port P1 direction register //0x03e3 +------------------------------------------------------*/ +union st_pd1 { /* union PD1 */ + struct { /* Bit Access */ + unsigned char PD1_0:1;/* Port P10 direction register */ + unsigned char PD1_1:1;/* Port P11 direction register */ + unsigned char PD1_2:1;/* Port P12 direction register */ + unsigned char PD1_3:1;/* Port P13 direction register */ + unsigned char PD1_4:1;/* Port P14 direction register */ + unsigned char PD1_5:1;/* Port P15 direction register */ + unsigned char PD1_6:1;/* Port P16 direction register */ + unsigned char PD1_7:1;/* Port P17 direction register */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /* */ + +/*------------------------------------------------------ + Port P2 register //0x03e4 +------------------------------------------------------*/ +union st_p2 { /* union P2 */ + struct { /* Bit Access */ + unsigned char P2_0:1;/* Port P20 register */ + unsigned char P2_1:1;/* Port P21 register */ + unsigned char P2_2:1;/* Port P22 register */ + unsigned char P2_3:1;/* Port P23 register */ + unsigned char P2_4:1;/* Port P24 register */ + unsigned char P2_5:1;/* Port P25 register */ + unsigned char P2_6:1;/* Port P26 register */ + unsigned char P2_7:1;/* Port P27 register */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /* */ + +/*------------------------------------------------------ + Port P3 register //0x03e5 +------------------------------------------------------*/ +union st_p3 { /* union P3 */ + struct { /* Bit Access */ + unsigned char P3_0:1;/* Port P30 register */ + unsigned char P3_1:1;/* Port P31 register */ + unsigned char P3_2:1;/* Port P32 register */ + unsigned char P3_3:1;/* Port P33 register */ + unsigned char P3_4:1;/* Port P34 register */ + unsigned char P3_5:1;/* Port P35 register */ + unsigned char P3_6:1;/* Port P36 register */ + unsigned char P3_7:1;/* Port P37 register */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /* */ + +/*------------------------------------------------------ + Port P2 direction register //0x03e6 +------------------------------------------------------*/ +union st_pd2 { /* union PD2 */ + struct { /* Bit Access */ + unsigned char PD2_0:1;/* Port P20 direction register */ + unsigned char PD2_1:1;/* Port P21 direction register */ + unsigned char PD2_2:1;/* Port P22 direction register */ + unsigned char PD2_3:1;/* Port P23 direction register */ + unsigned char PD2_4:1;/* Port P24 direction register */ + unsigned char PD2_5:1;/* Port P25 direction register */ + unsigned char PD2_6:1;/* Port P26 direction register */ + unsigned char PD2_7:1;/* Port P27 direction register */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /* */ + + +/*------------------------------------------------------ + Port P3 direction register //0x03e7 +------------------------------------------------------*/ +union st_pd3 { /* union PD3 */ + struct { /* Bit Access */ + unsigned char PD3_0:1;/* Port P30 direction register */ + unsigned char PD3_1:1;/* Port P31 direction register */ + unsigned char PD3_2:1;/* Port P32 direction register */ + unsigned char PD3_3:1;/* Port P33 direction register */ + unsigned char PD3_4:1;/* Port P34 direction register */ + unsigned char PD3_5:1;/* Port P35 direction register */ + unsigned char PD3_6:1;/* Port P36 direction register */ + unsigned char PD3_7:1;/* Port P37 direction register */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /* */ + +/*------------------------------------------------------ + Port P4 register //0x03e8 +------------------------------------------------------*/ +union st_p4 { /* union P4 */ + struct { /* Bit Access */ + unsigned char P4_0:1;/* Port P40 register */ + unsigned char P4_1:1;/* Port P41 register */ + unsigned char P4_2:1;/* Port P42 register */ + unsigned char P4_3:1;/* Port P43 register */ + unsigned char P4_4:1;/* Port P44 register */ + unsigned char P4_5:1;/* Port P45 register */ + unsigned char P4_6:1;/* Port P46 register */ + unsigned char P4_7:1;/* Port P47 register */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /* */ + +/*------------------------------------------------------ + Port P5 register //0x03e9 +------------------------------------------------------*/ +union st_p5 { /* union P5 */ + struct { /* Bit Access */ + unsigned char P5_0:1;/* Port P50 register */ + unsigned char P5_1:1;/* Port P51 register */ + unsigned char P5_2:1;/* Port P52 register */ + unsigned char P5_3:1;/* Port P53 register */ + unsigned char P5_4:1;/* Port P54 register */ + unsigned char P5_5:1;/* Port P55 register */ + unsigned char P5_6:1;/* Port P56 register */ + unsigned char P5_7:1;/* Port P57 register */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /* */ + + +/*------------------------------------------------------ + Port P4 direction register //0x03ea +------------------------------------------------------*/ +union st_pd4 { /* union PD4 */ + struct { /* Bit Access */ + unsigned char PD4_0:1;/* Port P40 direction register */ + unsigned char PD4_1:1;/* Port P41 direction register */ + unsigned char PD4_2:1;/* Port P42 direction register */ + unsigned char PD4_3:1;/* Port P43 direction register */ + unsigned char PD4_4:1;/* Port P44 direction register */ + unsigned char PD4_5:1;/* Port P45 direction register */ + unsigned char PD4_6:1;/* Port P46 direction register */ + unsigned char PD4_7:1;/* Port P47 direction register */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /* */ + + + +/*------------------------------------------------------ + Port P5 direction register //0x03eb +------------------------------------------------------*/ +union st_pd5 { /* union PD5 */ + struct { /* Bit Access */ + unsigned char PD5_0:1;/* Port P50 direction register */ + unsigned char PD5_1:1;/* Port P51 direction register */ + unsigned char PD5_2:1;/* Port P52 direction register */ + unsigned char PD5_3:1;/* Port P53 direction register */ + unsigned char PD5_4:1;/* Port P54 direction register */ + unsigned char PD5_5:1;/* Port P55 direction register */ + unsigned char PD5_6:1;/* Port P56 direction register */ + unsigned char PD5_7:1;/* Port P57 direction register */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /* */ + +/*------------------------------------------------------ + Port P6 register //0x03ec +------------------------------------------------------*/ +union st_p6 { /* union P6 */ + struct { /* Bit Access */ + unsigned char P6_0:1;/* Port P60 register */ + unsigned char P6_1:1;/* Port P61 register */ + unsigned char P6_2:1;/* Port P62 register */ + unsigned char P6_3:1;/* Port P63 register */ + unsigned char P6_4:1;/* Port P64 register */ + unsigned char P6_5:1;/* Port P65 register */ + unsigned char P6_6:1;/* Port P66 register */ + unsigned char P6_7:1;/* Port P67 register */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /* */ + +/*------------------------------------------------------ + Port P7 register //0x03ed +------------------------------------------------------*/ +union st_p7 { /* union P7 */ + struct { /* Bit Access */ + unsigned char P7_0:1;/* Port P70 register */ + unsigned char P7_1:1;/* Port P71 register */ + unsigned char P7_2:1;/* Port P72 register */ + unsigned char P7_3:1;/* Port P73 register */ + unsigned char P7_4:1;/* Port P74 register */ + unsigned char P7_5:1;/* Port P75 register */ + unsigned char P7_6:1;/* Port P76 register */ + unsigned char P7_7:1;/* Port P77 register */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /* */ + + +/*------------------------------------------------------ + Port P6 direction register //0x03ee +------------------------------------------------------*/ +union st_pd6 { /* union PD6 */ + struct { /* Bit Access */ + unsigned char PD6_0:1;/* Port P60 direction register */ + unsigned char PD6_1:1;/* Port P61 direction register */ + unsigned char PD6_2:1;/* Port P62 direction register */ + unsigned char PD6_3:1;/* Port P63 direction register */ + unsigned char PD6_4:1;/* Port P64 direction register */ + unsigned char PD6_5:1;/* Port P65 direction register */ + unsigned char PD6_6:1;/* Port P66 direction register */ + unsigned char PD6_7:1;/* Port P67 direction register */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /* */ + + +/*------------------------------------------------------ + Port P7 direction register //0x03ef +------------------------------------------------------*/ +union st_pd7 { /* union PD7 */ + struct { /* Bit Access */ + unsigned char PD7_0:1;/* Port P70 direction register */ + unsigned char PD7_1:1;/* Port P71 direction register */ + unsigned char PD7_2:1;/* Port P72 direction register */ + unsigned char PD7_3:1;/* Port P73 direction register */ + unsigned char PD7_4:1;/* Port P74 direction register */ + unsigned char PD7_5:1;/* Port P75 direction register */ + unsigned char PD7_6:1;/* Port P76 direction register */ + unsigned char PD7_7:1;/* Port P77 direction register */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /* */ + +/*------------------------------------------------------ + Port P8 register //0x03f0 +------------------------------------------------------*/ +union st_p8 { /* union P8 */ + struct { /* Bit Access */ + unsigned char P8_0:1;/* Port P80 register */ + unsigned char P8_1:1;/* Port P81 register */ + unsigned char P8_2:1;/* Port P82 register */ + unsigned char P8_3:1;/* Port P83 register */ + unsigned char P8_4:1;/* Port P84 register */ + unsigned char P8_5:1;/* Port P85 register */ + unsigned char P8_6:1;/* Port P86 register */ + unsigned char P8_7:1;/* Port P87 register */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /* */ + +/*------------------------------------------------------ + Port P9 register //0x03f1 +------------------------------------------------------*/ +union st_p9 { /* union P9 */ + struct { /* Bit Access */ + unsigned char P9_0:1;/* Port P90 register */ + unsigned char P9_1:1;/* Port P91 register */ + unsigned char P9_2:1;/* Port P92 register */ + unsigned char P9_3:1;/* Port P93 register */ + unsigned char P9_4:1;/* Port P94 register */ + unsigned char P9_5:1;/* Port P95 register */ + unsigned char P9_6:1;/* Port P96 register */ + unsigned char P9_7:1;/* Port P97 register */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /* */ + +/*------------------------------------------------------ + Port P8 direction register //0x03f2 +------------------------------------------------------*/ +union st_pd8 { /* union PD8 */ + struct { /* Bit Access */ + unsigned char PD8_0:1;/* Port P80 direction register */ + unsigned char PD8_1:1;/* Port P81 direction register */ + unsigned char PD8_2:1;/* Port P82 direction register */ + unsigned char PD8_3:1;/* Port P83 direction register */ + unsigned char PD8_4:1;/* Port P84 direction register */ + unsigned char :1;/* Nothing assigned */ + unsigned char PD8_6:1;/* Port P86 direction register */ + unsigned char PD8_7:1;/* Port P87 direction register */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /* */ + + +/*------------------------------------------------------ + Port P9 direction register //0x03f3 +------------------------------------------------------*/ +union st_pd9 { /* union PD9 */ + struct { /* Bit Access */ + unsigned char PD9_0:1;/* Port P90 direction register */ + unsigned char PD9_1:1;/* Port P91 direction register */ + unsigned char PD9_2:1;/* Port P92 direction register */ + unsigned char PD9_3:1;/* Port P93 direction register */ + unsigned char PD9_4:1;/* Port P94 direction register */ + unsigned char PD9_5:1;/* Port P95 direction register */ + unsigned char PD9_6:1;/* Port P96 direction register */ + unsigned char PD9_7:1;/* Port P97 direction register */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /* */ + +/*------------------------------------------------------ + Port P10 register //0x03f4 +------------------------------------------------------*/ +union st_p10 { /* union P10 */ + struct { /* Bit Access */ + unsigned char P10_0:1;/* Port P100 register */ + unsigned char P10_1:1;/* Port P101 register */ + unsigned char P10_2:1;/* Port P102 register */ + unsigned char P10_3:1;/* Port P103 register */ + unsigned char P10_4:1;/* Port P104 register */ + unsigned char P10_5:1;/* Port P105 register */ + unsigned char P10_6:1;/* Port P106 register */ + unsigned char P10_7:1;/* Port P107 register */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /* */ + +/*------------------------------------------------------ + Port P11 register //0x03f5 +------------------------------------------------------*/ +union st_p11 { /* union P11 */ + struct { /* Bit Access */ + unsigned char P11_0:1;/* Port P110 register */ + unsigned char P11_1:1;/* Port P111 register */ + unsigned char P11_2:1;/* Port P112 register */ + unsigned char P11_3:1;/* Port P113 register */ + unsigned char P11_4:1;/* Port P114 register */ + unsigned char P11_5:1;/* Port P115 register */ + unsigned char P11_6:1;/* Port P116 register */ + unsigned char P11_7:1;/* Port P117 register */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /* */ + +/*------------------------------------------------------ + Port P10 direction register //0x03f6 +------------------------------------------------------*/ +union st_pd10 { /* union PD10 */ + struct { /* Bit Access */ + unsigned char PD10_0:1;/* Port P100 direction register */ + unsigned char PD10_1:1;/* Port P101 direction register */ + unsigned char PD10_2:1;/* Port P102 direction register */ + unsigned char PD10_3:1;/* Port P103 direction register */ + unsigned char PD10_4:1;/* Port P104 direction register */ + unsigned char PD10_5:1;/* Port P105 direction register */ + unsigned char PD10_6:1;/* Port P106 direction register */ + unsigned char PD10_7:1;/* Port P107 direction register */ + } BIT; /* */ + char BYTE; /* Byte Access */ +}; /* */ + +/*------------------------------------------------------ + Port P11 direction register //0x03f7 +------------------------------------------------------*/ +union st_pd11 { /* union PD11 */ + struct { /* Bit Access */ + unsigned char PD11_0:1;/* Port P110 direction register */ + unsigned char PD11_1:1;/* Port P111 direction register */ + unsigned char PD11_2:1;/* Port P112 direction register */ + unsigned char PD11_3:1;/* Port P113 direction register */ + unsigned char PD11_4:1;/* Port P114 direction register */ + unsigned char PD11_5:1;/* Port P115 direction register */ + unsigned char PD11_6:1;/* Port P116 direction register */ + unsigned char PD11_7:1;/* Port P117 direction register */ + } BIT; /* */ + char BYTE; /* Byte Access */ +}; /* */ + +/*------------------------------------------------------ + Port P12 register //0x03f8 +------------------------------------------------------*/ +union st_p12 { /* union P12 */ + struct { /* Bit Access */ + unsigned char P12_0:1;/* Port P120 register */ + unsigned char P12_1:1;/* Port P121 register */ + unsigned char P12_2:1;/* Port P122 register */ + unsigned char P12_3:1;/* Port P123 register */ + unsigned char P12_4:1;/* Port P124 register */ + unsigned char P12_5:1;/* Port P125 register */ + unsigned char P12_6:1;/* Port P126 register */ + unsigned char P12_7:1;/* Port P127 register */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /* */ + +/*------------------------------------------------------ + Port P13 register //0x03f9 +------------------------------------------------------*/ +union st_p13 { /* union P13 */ + struct { /* Bit Access */ + unsigned char P13_0:1;/* Port P130 register */ + unsigned char P13_1:1;/* Port P131 register */ + unsigned char P13_2:1;/* Port P132 register */ + unsigned char P13_3:1;/* Port P133 register */ + unsigned char P13_4:1;/* Port P134 register */ + unsigned char P13_5:1;/* Port P135 register */ + unsigned char P13_6:1;/* Port P136 register */ + unsigned char P13_7:1;/* Port P137 register */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /* */ + +/*------------------------------------------------------ + Port P12 direction register //0x03fa +------------------------------------------------------*/ +union st_pd12 { /* union PD12 */ + struct { /* Bit Access */ + unsigned char PD12_0:1;/* Port P120 direction register */ + unsigned char PD12_1:1;/* Port P121 direction register */ + unsigned char PD12_2:1;/* Port P122 direction register */ + unsigned char PD12_3:1;/* Port P123 direction register */ + unsigned char PD12_4:1;/* Port P124 direction register */ + unsigned char PD12_5:1;/* Port P125 direction register */ + unsigned char PD12_6:1;/* Port P126 direction register */ + unsigned char PD12_7:1;/* Port P127 direction register */ + } BIT; /* */ + char BYTE; /* Byte Access */ +}; /* */ + +/*------------------------------------------------------ + Port P13 direction register //0x03fb +------------------------------------------------------*/ +union st_pd13 { /* union PD13 */ + struct { /* Bit Access */ + unsigned char PD13_0:1;/* Port P130 direction register */ + unsigned char PD13_1:1;/* Port P131 direction register */ + unsigned char PD13_2:1;/* Port P132 direction register */ + unsigned char PD13_3:1;/* Port P133 direction register */ + unsigned char PD13_4:1;/* Port P134 direction register */ + unsigned char PD13_5:1;/* Port P135 direction register */ + unsigned char PD13_6:1;/* Port P136 direction register */ + unsigned char PD13_7:1;/* Port P137 direction register */ + } BIT; /* */ + char BYTE; /* Byte Access */ +}; /* */ + +/*------------------------------------------------------ + Pull-up control register 0 //0x03fc +------------------------------------------------------*/ +union st_pur0 { /* union PUR0 */ + struct { /* Bit Access */ + unsigned char PU00:1;/* P00 to P03 pull-up */ + unsigned char PU01:1;/* P04 to P07 pull-up */ + unsigned char PU02:1;/* P10 to P13 pull-up */ + unsigned char PU03:1;/* P14 to P17 pull-up */ + unsigned char PU04:1;/* P20 to P23 pull-up */ + unsigned char PU05:1;/* P24 to P27 pull-up */ + unsigned char PU06:1;/* P30 to P33 pull-up */ + unsigned char PU07:1;/* P34 to P37 pull-up */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /* */ + +/*------------------------------------------------------ + Pull-up control register 1 //0x03fd +------------------------------------------------------*/ +union st_pur1 { /* union PUR1 */ + struct { /* Bit Access */ + unsigned char PU10:1;/* P40 to P43 pull-up */ + unsigned char PU11:1;/* P44 to P47 pull-up */ + unsigned char PU12:1;/* P50 to P53 pull-up */ + unsigned char PU13:1;/* P54 to P57 pull-up */ + unsigned char PU14:1;/* P60 to P63 pull-up */ + unsigned char PU15:1;/* P64 to P67 pull-up */ + unsigned char PU16:1;/* P70 to P73 pull-up (Except P70,P71 ; P70,P71 -> N-channel open drain ports)*/ + unsigned char PU17:1;/* P74 to P77 pull-up */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /* */ + +/*------------------------------------------------------ + Pull-up control register 2 //0x03fe +------------------------------------------------------*/ +union st_pur2 { /* union PUR2 */ + struct { /* Bit Access */ + unsigned char PU20:1;/* P80 to P83 pull-up */ + unsigned char PU21:1;/* P84 to P87 pull-up (Except P85) */ + unsigned char PU22:1;/* P90 to P93 pull-up */ + unsigned char PU23:1;/* P94 to P97 pull-up */ + unsigned char PU24:1;/* P100 to P103 pull-up */ + unsigned char PU25:1;/* P104 to P107 pull-up */ + unsigned char :1;/* Nothing assigned */ + unsigned char :1;/* Nothing assigned */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /* */ + +/*------------------------------------------------------ + Port control register //0x03ff +------------------------------------------------------*/ +union st_pcr { /* union PCR2 */ + struct { /* Bit Access */ + unsigned char PCR0:1;/* Port P1 control register */ + unsigned char :1;/* Nothing assigned */ + unsigned char :1;/* Nothing assigned */ + unsigned char :1;/* Nothing assigned */ + unsigned char :1;/* Nothing assigned */ + unsigned char :1;/* Nothing assigned */ + unsigned char :1;/* Nothing assigned */ + unsigned char :1;/* Nothing assigned */ + } BIT; /* */ + unsigned char BYTE; /* Byte Access */ +}; /* */ + + + + +/* Processor mode register 0 */ +#define PM0 (*(volatile union st_pm0 *)(0x0004)) + +/* Processor mode register 1 */ +#define PM1 (*(volatile union st_pm1 *)(0x0005)) + +/* System clock control register 0 */ +#define CM0 (*(volatile union st_cm0 *)(0x0006)) + +/* System clock control register 1 */ +#define CM1 (*(volatile union st_cm1 *)(0x0007)) + +/* Chip select control register */ +#define CSR (*(volatile union st_csr *)(0x0008)) + +/* Address match interrupt enable register */ +#define AIER (*(volatile union st_aier *)(0x0009)) + +/* Protect register */ +#define PRCR (*(volatile union st_prcr *)(0x000A)) + +/* Data bank register */ +#define DBR (*(volatile union st_dbr *)(0x000B)) + +/* Oscillation stop detection register */ +#define CM2 (*(volatile union st_cm2 *)(0x000C)) + +/* Watchdog timer start register */ +#define WDTS (*(volatile char *)(0x000E)) + +/* Watchdog timer control register */ +#define WDC (*(volatile union st_wdc *)(0x000F)) + +/* Address match interrupt register 0 */ +#define RMAD0 (*(volatile union st_rmad0 *)(0x0010)) + +/* Address match interrupt register 1 */ +#define RMAD1 (*(volatile union st_rmad1 *)(0x0014)) + +/* Voltage detection register 1 */ +#define VCR1 (*(volatile union st_vcr1 *)(0x0019)) + +/* Voltage detection register 2 */ +#define VCR2 (*(volatile union st_vcr2 *)(0x001A)) + +/* Chip select expansion control register */ +#define CSE (*(volatile union st_cse *)(0x001B)) + +/* PLC control register 0 */ +#define PLC0 (*(volatile union st_plc0 *)(0x001C)) + +/* Processor mode register 2 */ +#define PM2 (*(volatile union st_pm2 *)(0x001E)) + +/* Power supply down detection register */ +#define D4INT (*(volatile union st_d4int *)(0x001F)) + +/* DMA0 source pointer */ +#define SAR0 (*(volatile union st_sar0 *)(0x0020)) + +/* DMA0 destination pointer */ +#define DAR0 (*(volatile union st_dar0 *)(0x0024)) + +/* DMA0 transfer counter */ +#define TCR0 (*(volatile union st_tcr0 *)(0x0028)) + + /* DMA0 control register */ +#define DM0CON (*(volatile union st_dm0con *)(0x002C)) + +/* DMA1 source pointer */ +#define SAR1 (*(volatile union st_sar1 *)(0x0030)) + +/* DMA1 destination pointer */ +#define DAR1 (*(volatile union st_dar1 *)(0x0034)) + + /* DMA1 transfer counter */ +#define TCR1 (*(volatile union st_tcr1 *)(0x0038)) + +/* DMA1 control register */ +#define DM1CON (*(volatile union st_dm1con *)(0x003c)) + + +/* INT3~ interrupt control register */ +#define INT3IC (*(volatile union st_icr *)(0x0044)) + +/* Timer B5 interrupt control register */ +#define TB5IC (*(volatile union st_icr1 *)(0x0045)) + +/* Timer B4 interrupt control register */ +#define TB4IC (*(volatile union st_icr1 *)(0x0046)) + +/* Timer B3 interrupt control register */ +#define TB3IC (*(volatile union st_icr1 *)(0x0047)) + +/* UART1 BUS collision detection interrupt control register */ +#define U1BCNIC (*(volatile union st_icr1 *)(0x0046)) + +/* UART0 BUS collision detection interrupt control register */ +#define U0BCNIC (*(volatile union st_icr1 *)(0x0047)) + +/* SI/O4 interrupt control register */ +#define S4IC (*(volatile union st_icr *)(0x0048)) + +/* SI/O3 interrupt control register */ +#define S3IC (*(volatile union st_icr *)(0x0049)) + +/* INT5~ interrupt control register */ +#define INT5IC (*(volatile union st_icr *)(0x0048)) + +/* INT4~ interrupt control register */ +#define INT4IC (*(volatile union st_icr *)(0x0049)) + +/* Bus collision detection interrupt control register */ +#define BCNIC (*(volatile union st_bcnic *)(0x004a)) + +/* DMA0 interrupt control register */ +#define DM0IC (*(volatile union st_dm0ic *)(0x004b)) + +/* DMA1 interrupt control register */ +#define DM1IC (*(volatile union st_icr1 *)(0x004c)) + +/* Key input interrupt control register */ +#define KUPIC (*(volatile union st_icr1 *)(0x004D)) + +/* A/D conversion interrupt control register */ +#define ADIC (*(volatile union st_icr1 *)(0x004E)) + +/* UART2 transmit interrupt control register */ +#define S2TIC (*(volatile union st_icr1 *)(0x004F)) + +/* UART2 receive interrupt control register */ +#define S2RIC (*(volatile union st_icr1 *)(0x0050)) + +/* UART0 transmit interrupt control register */ +#define S0TIC (*(volatile union st_icr1 *)(0x0051)) + +/* UART0 receive interrupt control register */ +#define S0RIC (*(volatile union st_icr1 *)(0x0052)) + +/* UART1 transmit interrupt control register */ +#define S1TIC (*(volatile union st_icr1 *)(0x0053)) + +/* UART1 receive interrupt control register */ +#define S1RIC (*(volatile union st_icr1 *)(0x0054)) + +/* Timer A0 interrupt control register */ +#define TA0IC (*(volatile union st_icr1 *)(0x0055)) + +/* Timer A1 interrupt control register */ +#define TA1IC (*(volatile union st_icr1 *)(0x0056)) + +/* Timer A2 interrupt control register */ +#define TA2IC (*(volatile union st_icr1 *)(0x0057)) + +/* Timer A3 interrupt control register */ +#define TA3IC (*(volatile union st_icr1 *)(0x0058)) + +/* Timer A4 interrupt control register */ +#define TA4IC (*(volatile union st_icr1 *)(0x0059)) + +/* Timer B0 interrupt control register */ +#define TB0IC (*(volatile union st_icr1 *)(0x005A)) + +/* Timer B1 interrupt control register */ +#define TB1IC (*(volatile union st_icr1 *)(0x005B)) + +/* Timer B2 interrupt control register */ +#define TB2IC (*(volatile union st_icr1 *)(0x005C)) + +/* INT0~ interrupt control register */ +#define INT0IC (*(volatile union st_icr *)(0x005D)) + +/* INT1~ interrupt control register */ +#define INT1IC (*(volatile union st_icr *)(0x005E)) + +/* INT2~ interrupt control register */ +#define INT2IC (*(volatile union st_icr *)(0x005F)) + +/* Flash identification register */ +#define FIDR (*(volatile union st_fidr *)(0x01b4)) + +/* Flash memory control register 1 */ +#define FMR1 (*(volatile union st_fmr1 *)(0x01b5)) + +/* Flash memory control register 0 */ +#define FMR0 (*(volatile union st_fmr0 *)(0x01b7)) + +/* Address match interrupt register 2 */ +#define RMAD2 (*(volatile union st_rmad2 *)(0x01b8)) + +/* Address match interrupt enable register 2 */ +#define AIER2 (*(volatile union st_aier2 *)(0x01bb)) + +/* Address match interrupt register 3 */ +#define RMAD3 (*(volatile union st_rmad3 *)(0x01bc)) + +/* Peripheral clock select register */ +#define PCLKR (*(volatile union st_pclkr *)(0x025e)) + +/* Timer B3,4,5 count start flag */ +#define TBSR (*(volatile union st_tbsr *)(0x0340)) + + +/******************************************************** +* declare SFR short * +********************************************************/ +/*-------------------------------------------------------- + Timer registers : Read and write data in 16-bit units. +--------------------------------------------------------*/ + +/* Timer A1-1 register */ +#define TA1_1 (*(volatile unsigned short *)(0x0342)) + +/* Timer A2-1 register */ +#define TA2_1 (*(volatile unsigned short *)(0x0344)) + +/* Timer A4-1 register */ +#define TA4_1 (*(volatile unsigned short *)(0x0346)) + +/* Three-phase PWM control regester 0 */ +#define INVC0 (*(volatile union st_invc0 *)(0x0348)) + + /* Three-phase PWM control register 1 */ +#define INVC1 (*(volatile union st_invc1 *)(0x0349)) + +/* Three-phase output buffer register 0 */ +#define IDB0 (*(volatile union st_idb0 *)(0x034a)) + +/* Three-phase output buffer register 1 */ +#define IDB1 (*(volatile union st_idb1 *)(0x034b)) + +/*------------------------------------------------------ + Dead time timer ; Use "MOV" instruction when writing to this register. +------------------------------------------------------*/ +/* Dead time timer */ +#define DTT (*(volatile unsigned char *)(0x034c)) + +/*------------------------------------------------------------------ + Timer B2 interrupt occurrences frequency set counter + ; Use "MOV" instruction when writing to this register. +-------------------------------------------------------------------*/ +/* Timer B2 interrupt occurrences frequency set counter */ +#define ICTB2 (*(volatile unsigned char *)(0x034d)) + + +/* Timer B3 register */ +#define TB3 (*(volatile unsigned short *)(0x0350)) + +/* Timer B4 register */ +#define TB4 (*(volatile unsigned short *)(0x0352)) + +/* Timer B5 register */ +#define TB5 (*(volatile unsigned short *)(0x0354)) + +/* Timer B3 mode register */ +#define TB3MR (*(volatile union st_tmr *)(0x035b)) + +/* Timer B4 mode register */ +#define TB4MR (*(volatile union st_tmr *)(0x035c)) + +/* Timer B5 mode register */ +#define TB5MR (*(volatile union st_tmr *)(0x035d)) + +/* Interrupt request cause select register 2 */ +#define IFSR2A (*(volatile union st_ifsr2a *)(0x035e)) + +/* Interrupt cause select register */ +#define IFSR (*(volatile union st_ifsr *)(0x035f)) + +/* SI/O3i transmit/receive register (i=3,4)*/ +#define S3TRR (*(volatile unsigned char *)(0x0360)) + +/* SI/O3 control register */ +#define S3C (*(volatile union st_s3c *)(0x0362)) + + +/* SI/O3 bit rate generator (Use "MOV" instruction when writing to these registers)*/ +#define S3BRG (*(volatile unsigned char *)(0x0363)) + + +/* SI/O4 transmit/receive register */ +#define S4TRR (*(volatile unsigned char *)(0x0364)) + +/* SI/O4 control register */ +#define S4C (*(volatile union st_s4c *)(0x0366)) + +/* SI/O4 bit rate generator */ +#define S4BRG (*(volatile unsigned char *)(0x0367)) + +/* UART0 special mode register 4 */ +#define U0SMR4 (*(volatile union st_u0smr4 *)(0x036c)) + +/* UART0 special mode register 3 */ +#define U0SMR3 (*(volatile union st_u0smr3 *)(0x036d)) + + +/* UART0 special mode register 2 */ +#define U0SMR2 (*(volatile union st_u0smr2 *)(0x036e)) + +/* UART0 special mode register */ +#define U0SMR (*(volatile union st_u0smr *)(0x036f)) + +/* UART1 special mode register 4 */ +#define U1SMR4 (*(volatile union st_u1smr4 *)(0x0370)) + +/* UART1 special mode register 3 */ +#define U1SMR3 (*(volatile union st_u1smr3 *)(0x0371)) + +/* UART1 special mode register 2 */ +#define U1SMR2 (*(volatile union st_u1smr2 *)(0x0372)) + +/* UART1 special mode register */ +#define U1SMR (*(volatile union st_u1smr *)(0x0373)) + +/* UART2 special mode register 4 */ +#define U2SMR4 (*(volatile union st_u2smr4 *)(0x0374)) + +/* UART2 special mode register 3 */ +#define U2SMR3 (*(volatile union st_u2smr3 *)(0x0375)) + + +/* UART2 special mode register 2 */ +#define U2SMR2 (*(volatile union st_u2smr2 *)(0x0376)) + +/* UART2 special mode register */ +#define U2SMR (*(volatile union st_u2smr *)(0x0377)) + +/* UART2 transmit/receive mode register */ +#define U2MR (*(volatile union st_u2mr *)(0x0378)) + +/* UART2 bit rate generator */ +#define U2BRG (*(volatile unsigned char *)(0x0379)) + +/* UART2 transmit buffer register */ +#define U2TB (*(volatile union st_u2tb *)(0x037a)) + +/* UART2 transmit/receive control register 0 */ +//#pragma ADDRESS u2c0_addr 037cH +#define U2C0 (*(volatile union st_u2c0 *)(0x037c)) + +/* UART2 transmit/receive control register 1 */ +#define U2C1 (*(volatile union st_u2c1 *)(0x037d)) + +/* UART2 receive buffer register */ +#define U2RB (*(volatile union st_u2rb *)(0x037e)) + +/* Count start flag */ +#define TABSR (*(volatile union st_tabsr *)(0x0380)) + +/* Clock prescaler reset flag */ +#define CPSRF (*(volatile union st_cpsrf *)(0x0381)) + + +/* One-shot start flag */ +#define ONSF (*(volatile union st_onsf *)(0x0382)) + + +/* Trigger select register */ +#define TRGSR (*(volatile union st_trgsr *)(0x0383)) + + +/* Up/down flag (Use "MOV" instruction when writing to this register.)*/ +#define UDF (*(volatile unsigned char *)(0x0384)) + +/* Timer A0 register */ +#define TA0 (*(volatile unsigned short *)(0x0386)) + +/* Timer A1 register */ +#define TA1 (*(volatile unsigned short *)(0x0388)) + +/* Timer A2 register */ +#define TA2 (*(volatile unsigned short *)(0x038a)) + +/* Timer A3 register */ +#define TA3 (*(volatile unsigned short *)(0x038c)) + +/* Timer A4 register */ +#define TA4 (*(volatile unsigned short *)(0x038e)) + +/* Timer B0 register */ +#define TB0 (*(volatile unsigned short *)(0x0390)) + +/* Timer B1 register */ +#define TB1 (*(volatile unsigned short *)(0x0392)) + +/* Timer B2 register */ +#define TB2 (*(volatile unsigned short *)(0x0394)) + + + + /* Timer A0 mode register */ +#define TA0MR (*(volatile union st_tmr *)(0x0396)) + +/* Timer A1 mode register */ +#define TA1MR (*(volatile union st_tmr *)(0x0397)) + +/* Timer A2 mode register */ +#define TA2MR (*(volatile union st_tmr *)(0x0398)) + +/* Timer A3 mode register */ +#define TA3MR (*(volatile union st_tmr *)(0x0399)) + +/* Timer A4 mode register */ +#define TA4MR (*(volatile union st_tmr *)(0x039A)) + +/* Timer B0 mode register */ +#define TB0MR (*(volatile union st_tmr *)(0x039b)) + +/* Timer B1 mode register */ +#define TB1MR (*(volatile union st_tmr *)(0x039c)) + +/* Timer B2 mode register */ +#define TB2MR (*(volatile union st_tmr *)(0x039d)) + +/* Timer B2 special mode register */ +#define TB2SC (*(volatile union st_tb2sc *)(0x039e)) + +/* UART0 transmit/receive mode register */ +#define U0MR (*(volatile union st_u0mr *)(0x03a0)) + +/* UART0 bit rate generator (Use "MOV" instruction when writing to these registers.)*/ +#define U0BRG (*(volatile unsigned char *)(0x03a1)) + +/* UART0 transmit buffer register */ +#define U0TB (*(volatile union st_u0tb *)(0x03a2)) + +/* UART0 transmit/receive control register 0 */ +#define U0C0 (*(volatile union st_u0c0 *)(0x03a4)) + + /* UART0 transmit/receive control register 1 */ +#define U0C1 (*(volatile union st_u0c1 *)(0x03a5)) + +/* UART0 receive buffer register */ +#define U0RB (*(volatile union st_u0rb *)(0x03a6)) + +/* UART1 transmit/receive mode register */ +#define U1MR (*(volatile union st_u1mr *)(0x03a8)) + +/* UART1 bit rate generator */ +#define U1BRG (*(volatile unsigned char *)(0x03a9)) + + /* UART1 transmit buffer register */ +#define U1TB (*(volatile union st_u1tb *)(0x03aa)) + +/* UART1 transmit/receive control register 0 */ +#define U1C0 (*(volatile union st_u1c0 *)(0x03ac)) + + /* UART1 transmit/receive control register 1 */ +#define U1C1 (*(volatile union st_u1c1 *)(0x03ad)) + + /* UART1 receive buffer register */ +#define U1RB (*(volatile union st_u1rb *)(0x03ae)) + +/* UART transmit/receive control register 2 */ +#define UCON (*(volatile union st_ucon *)(0x03b0)) + +/* DMA0 cause select register */ +#define DM0SL (*(volatile union st_dm0sl *)(0x03b8)) + +/* DMA1 cause select register */ +#define DM1SL (*(volatile union st_dm1sl *)(0x03ba)) + +/* CRC data register */ +#define CRCD (*(volatile union st_crcd *)(0x03bc)) + +/* CRC input register */ +#define CRCIN (*(volatile unsigned char *)(0x03be)) + +/* A/D register 0 */ +#define AD0 (*(volatile union st_ad0 *)(0x03c0)) + +/* A/D register 1 */ +#define AD1 (*(volatile union st_ad1 *)(0x03c2)) + +/* A/D register 2 */ +#define AD2 (*(volatile union st_ad2 *)(0x03c4)) + +/* A/D register 3 */ +#define AD3 (*(volatile union st_ad3 *)(0x03c6)) + +/* A/D register 4 */ +#define AD4 (*(volatile union st_ad4 *)(0x03c8)) + +/* A/D register 5 */ +#define AD5 (*(volatile union st_ad5 *)(0x03ca)) + +/* A/D register 6 */ +#define AD6 (*(volatile union st_ad6 *)(0x03cc)) + + /* A/D register 7 */ +#define AD7 (*(volatile union st_ad7 *)(0x03ce)) + +/* A/D control register 2 */ +#define ADCON2 (*(volatile union st_adcon2 *)(0x03d4)) + +/* A/D control register 0 */ +#define ADCON0 (*(volatile union st_adcon0 *)(0x03d6)) + +/* A/D control register 1 */ +#define ADCON1 (*(volatile union st_adcon1 *)(0x03d7)) + +/* D/A register 0 */ +#define DA0 (*(volatile unsigned char *)(0x03d8)) + +/* D/A register 1 */ +#define DA1 (*(volatile unsigned char *)(0x03da)) + +/* D/A control register */ +#define DACON (*(volatile union st_dacon *)(0x03dc)) + +/* Port P14 control register */ +#define PC14 (*(volatile union st_pc14 *)(0x03de)) + +/* Pull-up control register 3 */ +#define PUR3 (*(volatile union st_pur3 *)(0x03df)) + + +/* Port P0 register */ +#define P0 (*(volatile union st_p0 *)(0x03e0)) + +/* Port P1 register */ +#define P1 (*(volatile union st_p1 *)(0x03e1)) + +/* Port P0 direction register */ +#define PD0 (*(volatile union st_pd0 *)(0x03e2)) + +/* Port P1 direction register */ +#define PD1 (*(volatile union st_pd1 *)(0x03e3)) + +/* Port P2 register */ +#define P2 (*(volatile union st_p2 *)(0x03e4)) + +/* Port P3 register */ +#define P3 (*(volatile union st_p3 *)(0x03e5)) + +/* Port P2 direction register */ +#define PD2 (*(volatile union st_pd2 *)(0x03e6)) + +/* Port P3 direction register */ +#define PD3 (*(volatile union st_pd3 *)(0x03e7)) + + + /* Port P4 register */ +#define P4 (*(volatile union st_p4 *)(0x03e8)) + +/* Port P5 register */ +#define P5 (*(volatile union st_p5 *)(0x03e9)) + +/* Port P4 direction register */ +#define PD4 (*(volatile union st_pd4 *)(0x03ea)) + +/* Port P5 direction register */ +#define PD5 (*(volatile union st_pd5 *)(0x03eb)) + +/* Port P6 register */ +#define P6 (*(volatile union st_p6 *)(0x03ec)) + +/* Port P7 register */ +#define P7 (*(volatile union st_p7 *)(0x03ed)) + +/* Port P6 direction register */ +#define PD6 (*(volatile union st_pd6 *)(0x03ee)) + +/* Port P7 direction register */ +#define PD7 (*(volatile union st_pd7 *)(0x03ef)) + +/* Port P8 register */ +#define P8 (*(volatile union st_p8 *)(0x03f0)) + +/* Port P9 register */ +#define P9 (*(volatile union st_p9 *)(0x03f1)) + +/* Port P8 direction register */ +#define PD8 (*(volatile union st_pd8 *)(0x03f2)) + +/* Port P9 direction register */ +#define PD9 (*(volatile union st_pd9 *)(0x03f3)) + +/* Port P10 register */ +#define P10 (*(volatile union st_p10 *)(0x03f4)) + +/* Port P11 register */ +#define P11 (*(volatile union st_p11 *)(0x03f5)) + +/* Port P10 direction register */ +#define PD10 (*(volatile union st_pd10 *)(0x03f6)) + +/* Port P11 direction register */ +#define PD11 (*(volatile union st_pd11 *)(0x03f7)) + +/* Port P12 register */ +#define P12 (*(volatile union st_p12 *)(0x03f8)) + +/* Port P13 register */ +#define P13 (*(volatile union st_p13 *)(0x03f9)) + +/* Port P12 direction register */ +#define PD12 (*(volatile union st_pd12 *)(0x03fa)) + +/* Port P13 direction register */ +#define PD13 (*(volatile union st_pd13 *)(0x03f7)) + + /* Pull-up control register 0 */ +#define PUR0 (*(volatile union st_pur0 *)(0x03fc)) + +/* Pull-up control register 1 */ +#define PUR1 (*(volatile union st_pur1 *)(0x03fd)) + + /* Pull-up control register 2 */ +#define PUR2 (*(volatile union st_pur2 *)(0x03fe)) + +/* Port control register */ +#define PCR (*(volatile union st_pcr *)(0x03ff)) + + +#endif /* __IOM16C62P_H__ */ + diff --git a/tos/chips/m16c62p/m16c62phardware.h b/tos/chips/m16c62p/m16c62phardware.h new file mode 100755 index 00000000..1603d661 --- /dev/null +++ b/tos/chips/m16c62p/m16c62phardware.h @@ -0,0 +1,150 @@ +/* + * Copyright (c) 2009 Communication Group and Eislab at + * Lulea University of Technology + * + * Contact: Laurynas Riliskis, LTU + * Mail: laurynas.riliskis@ltu.se + * All rights reserved. + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * - Neither the name of Communication Group at Lulea University of Technology + * nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL STANFORD + * UNIVERSITY OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED + * OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + * Some M16c/62p needed macros and defines. + * + * @author Henrik Makitaavola + * @author Fan Zhang + */ + +#ifndef __M16C62PHARDWARE_H__ +#define __M16C62PHARDWARE_H__ + +#include "interrupts.h" +#include "iom16c62p.h" +#include "bits.h" + +#define true 1 +#define false 0 + +//Bit operators using bit number +#define _BV(bit) (1 << bit) +#define SET_BIT(port, bit) ((port) |= _BV(bit)) +#define CLR_BIT(port, bit) ((port) &= ~_BV(bit)) +#define READ_BIT(port, bit) (((port) & _BV(bit)) != 0) +#define FLIP_BIT(port, bit) ((port) ^= _BV(bit)) +#define WRITE_BIT(port, bit, value) \ + if (value) SET_BIT((port), (bit)); \ + else CLR_BIT((port), (bit)) + +// Bit operators using bit flag mask +#define SET_FLAG(port, flag) ((port) |= (flag)) +#define CLR_FLAG(port, flag) ((port) &= ~(flag)) +#define READ_FLAG(port, flag) ((port) & (flag)) + +// We need slightly different defs than M16C_INTERRUPT +// for interrupt handlers. +#define M16C_INTERRUPT_HANDLER(id) \ + M16C_INTERRUPT(id) @atomic_hwevent() @C() + +// The mov instruction should be used when clearing the interrupt flag. +// More information can be found in the manual for the MCU. +inline void clear_interrupt(uint16_t interrupt_addr) +{ + atomic + { + uint8_t tmp = (*TCAST(volatile uint8_t* ONE, interrupt_addr)); + CLR_BIT(tmp, 3); + asm("mov.w %[interrupt_addr], a0\n\t" + "mov.b %[tmp], [a0]" + : + : [tmp] "r" (tmp) , [interrupt_addr] "r" (interrupt_addr) + : "a0"); + } +} + +typedef uint8_t mcu_power_t @combine("ecombine"); + +mcu_power_t mcombine(mcu_power_t m1, mcu_power_t m2) +{ + return (m1 < m2) ? m1: m2; +} + +enum +{ + M16C62P_POWER_WAIT = 1, + M16C62P_POWER_STOP = 2, +}; + +inline void __nesc_enable_interrupt(void) { asm("fset i"); } +inline void __nesc_disable_interrupt(void) { asm("fclr i"); } + +// Macro to create union casting functions. +#define DEFINE_UNION_CAST(func_name, from_type, to_type) \ + to_type func_name(from_type x_type) { \ + union {from_type f_type; to_type t_type;} c_type = {f_type:x_type}; return c_type.t_type; } + +typedef uint16_t __nesc_atomic_t; + +#ifndef NESC_BUILD_BINARY +/** + * Start atomic section. + */ +inline __nesc_atomic_t __nesc_atomic_start(void) @spontaneous() +{ + __nesc_atomic_t result; + // Disable interrupts + __nesc_disable_interrupt(); + // Save the flag register (FLG) + asm volatile ("stc flg, %0": "=r"(result): : "%flg"); + asm volatile("" : : : "memory"); // ensure atomic section effect visibility + return result; +} + +/** + * End atomic section. + */ +inline void __nesc_atomic_end(__nesc_atomic_t original_FLG) @spontaneous() +{ + // Restore the flag register (FLG) + asm volatile("" : : : "memory"); // ensure atomic section effect visibility + asm volatile ("ldc %0, flg": : "r"(original_FLG): "%flg"); +} +#endif + +// If the platform doesnt have defined any main crystal speed it will +// get a default value of 16MHz +#ifndef MAIN_CRYSTAL_SPEED +#define MAIN_CRYSTAL_SPEED 16 /*MHZ*/ +#endif + +// If the PLL_MULTIPLIER is not defined it will be default to M16C62P_PLL_2. +#ifndef PLL_MULTIPLIER +#define PLL_MULTIPLIER M16C62P_PLL_2 +#endif + +#endif // __M16C62PHARDWARE_H__ -- 2.39.2