* (c) 2002 by Steve Udnerwood <steveu@coppice.org>
* Originally based in part on work by Texas Instruments Inc.
*
- * $Id: dma.h,v 1.7 2007/07/11 17:38:19 coppice Exp $
+ * $Id: dma.h,v 1.8 2008/11/07 08:28:40 sb-sf Exp $
*/
-/* Switches: none */
+/* Switches:
+
+__MSP430_HAS_DMAIV__ - if the device has a DMAIV register
+__MSP430_HAS_DMA_3__ - if module has 16-bit address registers
+__MSP430_HAS_DMAX_3__ - if module has 20-bit address registers (430X core)
+
+ */
#define DMACTL0_ 0x0122 /* DMA module control 0 */
sfrw(DMACTL0,DMACTL0_);
#define DMACTL1_ 0x0124 /* DMA module control 1 */
sfrw(DMACTL1, DMACTL1_);
+#if defined(__MSP430_HAS_DMAIV__)
+#define DMAIV_ 0x0126 /* DMA module interrupt vector word */
+sfrw(DMAIV, DMAIV_);
+#endif
#if defined(__MSP430_HAS_DMA_3__)
#define DMA0CTL_ 0x01E0 /* DMA channel 0 control */
sfrw(DMA2SZ, DMA2SZ_);
#endif
-#define SREF_0 (0<<4)
-#define SREF_1 (1<<4)
-#define SREF_2 (2<<4)
-#define SREF_3 (3<<4)
-#define SREF_4 (4<<4)
-#define SREF_5 (5<<4)
-#define SREF_6 (6<<4)
-#define SREF_7 (7<<4)
-#define EOS 0x80
-
#define DMA0TSEL0 0x0001 /* DMA channel 0 transfer select bit 0 */
#define DMA0TSEL1 0x0002 /* DMA channel 0 transfer select bit 1 */
#define DMA0TSEL2 0x0004 /* DMA channel 0 transfer select bit 2 */