]> oss.titaniummirror.com Git - tinyos-2.x.git/commit
Add a BusyWait interface for controlling SHT1X timing requirements.
authorsmckown <smckown@4bc1554a-c7f2-4f65-a403-e0be01f0239c>
Tue, 16 Sep 2008 14:17:50 +0000 (14:17 +0000)
committerR. Steve McKown <rsmckown@gmail.com>
Fri, 7 May 2010 19:49:19 +0000 (13:49 -0600)
commit4122e4dfb28f7b5e72c9dd1c401e19d93ca82820
tree4e6d7c745af362a37bc73e750aeaeb4860c5ea4c
parent4ef669e6eea48bc320936d45f2fdb8a2d6d5190b
Add a BusyWait interface for controlling SHT1X timing requirements.

The default implementation, which does nothing, is probably suitable for all
processors running at about 10 MHz or less.  Implement a platform specific
version to enforce the 5 us timing requirements as per the data sheet.
tos/chips/sht11/SensirionBusyWaitC.nc [new file with mode: 0644]
tos/chips/sht11/SensirionSht11LogicP.nc
tos/platforms/telosa/chips/sht11/HalSensirionSht11C.nc
tos/sensorboards/im2sb/HalSensirionSht11C.nc