]> oss.titaniummirror.com Git - tinyos-2.x.git/commit
Add a BusyWait interface for controlling SHT1X timing requirements.
authorsmckown <smckown@4bc1554a-c7f2-4f65-a403-e0be01f0239c>
Tue, 16 Sep 2008 14:17:50 +0000 (14:17 +0000)
committerR. Steve McKown <rsmckown@gmail.com>
Mon, 7 Dec 2009 17:56:28 +0000 (10:56 -0700)
commitd158cb94a6e8e7d805b26533d8ec7f3353e2f423
treefed74df930e1347ab44dd82da17992f5dcab295a
parent831e26ff1228d174240fa75b07a8f5ac912ee837
Add a BusyWait interface for controlling SHT1X timing requirements.

The default implementation, which does nothing, is probably suitable for all
processors running at about 10 MHz or less.  Implement a platform specific
version to enforce the 5 us timing requirements as per the data sheet.
tos/chips/sht11/SensirionBusyWaitC.nc [new file with mode: 0644]
tos/chips/sht11/SensirionSht11LogicP.nc
tos/platforms/telosa/chips/sht11/HalSensirionSht11C.nc
tos/sensorboards/im2sb/HalSensirionSht11C.nc