]> oss.titaniummirror.com Git - tinyos-2.x.git/commit
Proper support for the new basic_clock+ peripheral. Default UART baud rate is
authorsmckown <smckown@4bc1554a-c7f2-4f65-a403-e0be01f0239c>
Tue, 9 Sep 2008 04:35:28 +0000 (04:35 +0000)
committerR. Steve McKown <rsmckown@gmail.com>
Tue, 1 Dec 2009 03:00:51 +0000 (20:00 -0700)
commitea919e632db754746366a851e66c6d04c3959a93
tree47d291716a9ac35e67c920a5a8b5d077876c9cbb
parentb83aa91d0424245008bc68cecceac8b12efda682
Proper support for the new basic_clock+ peripheral.  Default UART baud rate is
115200, 8 data bits, no parity, 1 stop bit.  tmicore overrides the default MCLK
setting of 4MHz (binary) in favor of 8MHz (binary).  The updated clock init
code ensures SMCLK is 1MHz (binary) when DCOCLK is 1MHz, 2MHz, 4MHz or 8MHz.
tos/chips/msp430/clock2/Msp430ClockP.nc [new file with mode: 0644]
tos/chips/msp430/usci/Msp430UartP.nc
tos/platforms/tmicore/MoteClockP.nc