Add a BusyWait interface for controlling SHT1X timing requirements.

The default implementation, which does nothing, is probably suitable for all
processors running at about 10 MHz or less.  Implement a platform specific
version to enforce the 5 us timing requirements as per the data sheet.

diff --git a/tos/chips/sht11/SensirionBusyWaitC.nc b/tos/chips/sht11/SensirionBusyWaitC.nc
new file mode 100644 (file)
index 0000000..d4f51e8
--- /dev/null
+++ b/tos/chips/sht11/SensirionBusyWaitC.nc
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2008, Titanium Mirror, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * - Redistributions of source code must retain the above copyright notice,
+ *   this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - Neither the name of Titanium Mirror, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from
+ *   this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+ * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * This BusyWait interface is solely designed for use in providing the
+ * necessary 5us timing when bit-banging the SHT1X sensibus clock pin in
+ * SensirionSht11LogicP, which only calls BusyWait.wait() with an argument of
+ * 5 (us).  For most microprocessors running at under 10MHz, the implementation
+ * need do nothing to achieve the required timing.  This default implementation
+ * is designed for such platforms.  Platforms using higher performance
+ * microprocessors may need to override this component with a platform-specific
+ * one to provide the necessary wait time.
+ *
+ * @author R. Steve McKown <rsmckown@gmail.com>
+ */
+
+module SensirionBusyWaitC {
+  provides interface BusyWait<TMicro, uint8_t>;
+}
+implementation {
+  async command void BusyWait.wait(uint8_t us) {}
+}

diff --git a/tos/chips/sht11/SensirionSht11LogicP.nc b/tos/chips/sht11/SensirionSht11LogicP.nc
index ce4aa6ca68f7f46bfb54696af6d250853abdb7b4..f3f02697b0737b2d783a9422d8f1ca767849ee13 100644 (file)
--- a/tos/chips/sht11/SensirionSht11LogicP.nc
+++ b/tos/chips/sht11/SensirionSht11LogicP.nc
@@ -57,6 +57,7 @@ generic module SensirionSht11LogicP() {
   uses interface GeneralIO as CLOCK;
   uses interface GpioInterrupt as InterruptDATA;
 
+  uses interface BusyWait<TMicro, uint8_t>;
   uses interface Timer<TMilli>;
 
   uses interface Leds;
@@ -240,11 +241,17 @@ implementation {
     call DATA.makeOutput();
     call DATA.set();
     call CLOCK.clr();
+    call BusyWait.wait(5);
     call CLOCK.set();
+    call BusyWait.wait(5);
     call DATA.clr();
+    call BusyWait.wait(5);
     call CLOCK.clr();
+    call BusyWait.wait(5);
     call CLOCK.set();
+    call BusyWait.wait(5);
     call DATA.set();
+    call BusyWait.wait(5);
     call CLOCK.clr();
   }
 
@@ -261,6 +268,7 @@ implementation {
        call DATA.clr();
       byte = byte << 1;
       call CLOCK.set();
+      call BusyWait.wait(5);
       call CLOCK.clr();
     }
   }
@@ -373,6 +381,7 @@ implementation {
     call DATA.makeOutput();
     call DATA.clr();
     call CLOCK.set();
+    call BusyWait.wait(5);
     call CLOCK.clr();
     call DATA.makeInput();
     call DATA.set();
@@ -382,6 +391,7 @@ implementation {
     call DATA.makeOutput();
     call DATA.set();
     call CLOCK.set();
+    call BusyWait.wait(5);
     call CLOCK.clr();
   }
 

diff --git a/tos/platforms/telosa/chips/sht11/HalSensirionSht11C.nc b/tos/platforms/telosa/chips/sht11/HalSensirionSht11C.nc
index 4714067ed456872b2ecd01715e802ad467625927..06e729a53648df88083363879ca1849bf1bb3316 100644 (file)
--- a/tos/platforms/telosa/chips/sht11/HalSensirionSht11C.nc
+++ b/tos/platforms/telosa/chips/sht11/HalSensirionSht11C.nc
@@ -54,6 +54,9 @@ implementation {
   SensirionSht11LogicP.CLOCK -> HplSensirionSht11C.SCK;
   SensirionSht11LogicP.InterruptDATA -> HplSensirionSht11C.InterruptDATA;
   
+  components SensirionBusyWaitC;
+  SensirionSht11LogicP.BusyWait -> SensirionBusyWaitC;
+
   components new TimerMilliC();
   SensirionSht11LogicP.Timer -> TimerMilliC;
 

diff --git a/tos/sensorboards/im2sb/HalSensirionSht11C.nc b/tos/sensorboards/im2sb/HalSensirionSht11C.nc
index 34edc15b247fc65c017d2436bbceb532a755b3e3..38599ca464f3fe6224485ef674d6febf1e2d0a30 100644 (file)
--- a/tos/sensorboards/im2sb/HalSensirionSht11C.nc
+++ b/tos/sensorboards/im2sb/HalSensirionSht11C.nc
@@ -57,6 +57,8 @@ implementation {
   SensirionSht11LogicP.CLOCK -> HplSensirionSht11C.SCK;
   SensirionSht11LogicP.InterruptDATA -> HplSensirionSht11C.InterruptDATA;
 
+  components SensirionBusyWaitC;
+  SensirionSht11LogicP.BusyWait -> SensirionBusyWaitC;
   
   components new TimerMilliC();
   SensirionSht11LogicP.Timer -> TimerMilliC;