From: R. Steve McKown <rsmckown@gmail.com>
Date: Mon, 2 Aug 2010 20:25:37 +0000 (-0600)
Subject: Interrupts.tx() signal is only relevant when UartStream.send() pending.
X-Git-Tag: release/2.1.1-4.4~16
X-Git-Url: https://oss.titaniummirror.com/gitweb/?p=tinyos-2.x.git;a=commitdiff_plain;h=2fc550ecfc8fb03f258b5a692c8e7e90793aced2

Interrupts.tx() signal is only relevant when UartStream.send() pending.
---

diff --git a/tos/chips/msp430/usci/Msp430UartP.nc b/tos/chips/msp430/usci/Msp430UartP.nc
index 72df1df0..cdc08089 100644
--- a/tos/chips/msp430/usci/Msp430UartP.nc
+++ b/tos/chips/msp430/usci/Msp430UartP.nc
@@ -158,16 +158,18 @@ implementation {
     /* FIXME: this can cause an arbitrarily long ISR, if m_slen is large.
      * But depending on timing, we may always only write 1 byte.
      */
-    while (!call Registers.getIfgTx()); /* in case interleaved UB.send */
-    while (m_slen && call Registers.getIfgTx()) {
-      call Registers.setTxbuf(*m_sbuf);
-      if (--m_slen)
-	m_sbuf++;
-    }
-    if (m_slen == 0) {
-      call Registers.clrIeTx();
-      m_sobuf = 0;
-      signal UartStream.sendDone(m_sobuf, m_solen, SUCCESS);
+    if (m_sobuf) {
+      while (!call Registers.getIfgTx()); /* in case interleaved UB.send */
+      while (m_slen && call Registers.getIfgTx()) {
+	call Registers.setTxbuf(*m_sbuf);
+	if (--m_slen)
+	  m_sbuf++;
+      }
+      if (m_slen == 0) {
+	call Registers.clrIeTx();
+	m_sobuf = 0;
+	signal UartStream.sendDone(m_sobuf, m_solen, SUCCESS);
+      }
     }
   }