From 406725454a6e1d497656961c78230c7fadb5d889 Mon Sep 17 00:00:00 2001 From: sallai Date: Mon, 7 Jul 2008 19:52:52 +0000 Subject: [PATCH] added safe tinyos annotations --- tos/chips/atm1281/McuSleepC.nc | 28 +++--- tos/chips/atm1281/adc/Atm128AdcP.nc | 52 +++++------ tos/chips/atm1281/adc/HplAtm128AdcP.nc | 70 +++++++------- tos/chips/atm1281/atm128hardware.h | 24 ++--- tos/chips/atm1281/timer/Atm1281AlarmAsyncP.nc | 24 ++--- tos/chips/atm1281/timer/HplAtm1281Timer1P.nc | 88 +++++++++--------- .../atm1281/timer/HplAtm1281Timer2AsyncP.nc | 92 +++++++++---------- tos/chips/atm1281/timer/HplAtm1281Timer3P.nc | 88 +++++++++--------- 8 files changed, 233 insertions(+), 233 deletions(-) diff --git a/tos/chips/atm1281/McuSleepC.nc b/tos/chips/atm1281/McuSleepC.nc index e375c9c6..ad4a4ab0 100644 --- a/tos/chips/atm1281/McuSleepC.nc +++ b/tos/chips/atm1281/McuSleepC.nc @@ -8,13 +8,13 @@ * agreement is hereby granted, provided that the above copyright * notice, the following two paragraphs and the author appear in all * copies of this software. - * + * * IN NO EVENT SHALL STANFORD UNIVERSITY BE LIABLE TO ANY PARTY FOR * DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES * ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN * IF STANFORD UNIVERSITY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH * DAMAGE. - * + * * STANFORD UNIVERSITY SPECIFICALLY DISCLAIMS ANY WARRANTIES, * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE @@ -31,12 +31,12 @@ * documentation for any purpose, without fee, and without written agreement is * hereby granted, provided that the above copyright notice, the following * two paragraphs and the author appear in all copies of this software. - * + * * IN NO EVENT SHALL THE VANDERBILT UNIVERSITY BE LIABLE TO ANY PARTY FOR * DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT * OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE VANDERBILT * UNIVERSITY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * * THE VANDERBILT UNIVERSITY SPECIFICALLY DISCLAIMS ANY WARRANTIES, * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS @@ -60,7 +60,7 @@ * @date October 30, 2007 */ -module McuSleepC { +module McuSleepC @safe() { provides { interface McuSleep; interface McuPowerState; @@ -84,25 +84,25 @@ implementation { (1 << SM1) | (1 << SM0), (1 << SM2) | (1 << SM1), (1 << SM1)}; - + mcu_power_t getPowerState() { // Note: we go to sleep even if timer 0, 1, 3, 4, or 5's overflow // interrupt is enabled - this allows using timers 0, 1 and 3 as TinyOS // "Alarm"s while still having power management. (see TEP102 Appendix C) // Input capture and output compare for timer 4 and 5 are not functional - // on the atm1281. + // on the atm1281. // Are there any input capture or output compare interrupts enabled - // for timers 0, 1 or 3? + // for timers 0, 1 or 3? if ( TIMSK0 & (1 << OCIE0A | 1 << OCIE0B ) || TIMSK1 & (1 << ICIE1 | 1 << OCIE1A | 1 << OCIE1B | 1 << OCIE1C) || TIMSK3 & (1 << ICIE3 | 1 << OCIE3A | 1 << OCIE3B | 1 << OCIE3C) ) { return ATM128_POWER_IDLE; - } + } // SPI (Radio stack) - else if (bit_is_set(SPCR, SPIE)) { + else if (bit_is_set(SPCR, SPIE)) { return ATM128_POWER_IDLE; } // UARTs are active @@ -115,9 +115,9 @@ implementation { // I2C (Two-wire) is active else if (bit_is_set(TWCR, TWEN)){ return ATM128_POWER_IDLE; - } + } // ADC is enabled - else if (bit_is_set(ADCSRA, ADEN)) { + else if (bit_is_set(ADCSRA, ADEN)) { return ATM128_POWER_ADC_NR; } else { @@ -130,11 +130,11 @@ implementation { powerState = mcombine(getPowerState(), call McuPowerOverride.lowestState()); SMCR = - (SMCR & 0xf0) | 1 << SE | read_uint8_t(&atm128PowerBits[powerState]); + (SMCR & 0xf0) | 1 << SE | read_uint8_t(&atm128PowerBits[powerState]); sei(); asm volatile ("sleep"); cli(); - + CLR_BIT(SMCR, SE); } diff --git a/tos/chips/atm1281/adc/Atm128AdcP.nc b/tos/chips/atm1281/adc/Atm128AdcP.nc index 1dae8ac3..08db4f72 100644 --- a/tos/chips/atm1281/adc/Atm128AdcP.nc +++ b/tos/chips/atm1281/adc/Atm128AdcP.nc @@ -1,17 +1,17 @@ /* $Id$ - * "Copyright (c) 2000-2003 The Regents of the University of California. + * "Copyright (c) 2000-2003 The Regents of the University of California. * All rights reserved. * * Permission to use, copy, modify, and distribute this software and its * documentation for any purpose, without fee, and without written agreement is * hereby granted, provided that the above copyright notice, the following * two paragraphs and the author appear in all copies of this software. - * + * * IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO ANY PARTY FOR * DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT * OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE UNIVERSITY OF * CALIFORNIA HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * * THE UNIVERSITY OF CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES, * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS @@ -21,9 +21,9 @@ * Copyright (c) 2002-2005 Intel Corporation * All rights reserved. * - * This file is distributed under the terms in the attached INTEL-LICENSE + * This file is distributed under the terms in the attached INTEL-LICENSE * file. If you do not find these files, copies can be found by writing to - * Intel Research Berkeley, 2150 Shattuck Avenue, Suite 1300, Berkeley, CA, + * Intel Research Berkeley, 2150 Shattuck Avenue, Suite 1300, Berkeley, CA, * 94704. Attention: Intel License Inquiry. * * Copyright (c) 2004-2005 Crossbow Technology, Inc. All rights reserved. @@ -32,18 +32,18 @@ * documentation for any purpose, without fee, and without written agreement is * hereby granted, provided that the above copyright notice, the following * two paragraphs and the author appear in all copies of this software. - * - * IN NO EVENT SHALL CROSSBOW TECHNOLOGY OR ANY OF ITS LICENSORS BE LIABLE TO - * ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL + * + * IN NO EVENT SHALL CROSSBOW TECHNOLOGY OR ANY OF ITS LICENSORS BE LIABLE TO + * ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL * DAMAGES ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN - * IF CROSSBOW OR ITS LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. + * IF CROSSBOW OR ITS LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. * * CROSSBOW TECHNOLOGY AND ITS LICENSORS SPECIFICALLY DISCLAIM ALL WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY - * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS - * ON AN "AS IS" BASIS, AND NEITHER CROSSBOW NOR ANY LICENSOR HAS ANY - * OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS + * ON AN "AS IS" BASIS, AND NEITHER CROSSBOW NOR ANY LICENSOR HAS ANY + * OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR * MODIFICATIONS. * * Copyright (c) 2007, Vanderbilt University @@ -53,12 +53,12 @@ * documentation for any purpose, without fee, and without written agreement is * hereby granted, provided that the above copyright notice, the following * two paragraphs and the author appear in all copies of this software. - * + * * IN NO EVENT SHALL THE VANDERBILT UNIVERSITY BE LIABLE TO ANY PARTY FOR * DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT * OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE VANDERBILT * UNIVERSITY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * * THE VANDERBILT UNIVERSITY SPECIFICALLY DISCLAIMS ANY WARRANTIES, * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS @@ -81,7 +81,7 @@ * @author Janos Sallai */ -module Atm128AdcP +module Atm128AdcP @safe() { provides { interface Init; @@ -95,24 +95,24 @@ module Atm128AdcP } } implementation -{ +{ /* State for the current and next (multiple-sampling only) conversion */ struct { bool multiple : 1; /* single and multiple-sampling mode */ bool precise : 1; /* is this result going to be precise? */ uint8_t channel : 5; /* what channel did this sample come from? */ } f, nextF; - + command error_t Init.init() { atomic { Atm128Adcsra_t adcsr; adcsr.aden = ATM128_ADC_ENABLE_OFF; - adcsr.adsc = ATM128_ADC_START_CONVERSION_OFF; - adcsr.adate= ATM128_ADC_FREE_RUNNING_OFF; - adcsr.adif = ATM128_ADC_INT_FLAG_OFF; - adcsr.adie = ATM128_ADC_INT_ENABLE_OFF; + adcsr.adsc = ATM128_ADC_START_CONVERSION_OFF; + adcsr.adate= ATM128_ADC_FREE_RUNNING_OFF; + adcsr.adif = ATM128_ADC_INT_FLAG_OFF; + adcsr.adie = ATM128_ADC_INT_ENABLE_OFF; adcsr.adps = ATM128_ADC_PRESCALE_2; call HplAtm128Adc.setAdcsra(adcsr); } @@ -121,7 +121,7 @@ implementation /* We enable the A/D when start is called, and disable it when stop is called. This drops A/D conversion latency by a factor of two (but - increases idle mode power consumption a little). + increases idle mode power consumption a little). */ async command error_t AsyncStdControl.start() { atomic call HplAtm128Adc.enableAdc(); @@ -147,7 +147,7 @@ implementation bool precise, multiple; uint8_t channel; - atomic + atomic { channel = f.channel; precise = f.precise; @@ -174,7 +174,7 @@ implementation uint8_t nextChannel, nextVoltage; Atm128Admux_t admux; - atomic + atomic { admux = call HplAtm128Adc.getAdmux(); nextVoltage = admux.refs; diff --git a/tos/chips/atm1281/adc/HplAtm128AdcP.nc b/tos/chips/atm1281/adc/HplAtm128AdcP.nc index ec886718..0a3dc828 100644 --- a/tos/chips/atm1281/adc/HplAtm128AdcP.nc +++ b/tos/chips/atm1281/adc/HplAtm128AdcP.nc @@ -6,19 +6,19 @@ * documentation for any purpose, without fee, and without written agreement is * hereby granted, provided that the above copyright notice, the following * two paragraphs and the author appear in all copies of this software. - * - * IN NO EVENT SHALL CROSSBOW TECHNOLOGY OR ANY OF ITS LICENSORS BE LIABLE TO - * ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL + * + * IN NO EVENT SHALL CROSSBOW TECHNOLOGY OR ANY OF ITS LICENSORS BE LIABLE TO + * ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL * DAMAGES ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN - * IF CROSSBOW OR ITS LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. + * IF CROSSBOW OR ITS LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. * * CROSSBOW TECHNOLOGY AND ITS LICENSORS SPECIFICALLY DISCLAIM ALL WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY - * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS - * ON AN "AS IS" BASIS, AND NEITHER CROSSBOW NOR ANY LICENSOR HAS ANY - * OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR - * MODIFICATIONS. + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS + * ON AN "AS IS" BASIS, AND NEITHER CROSSBOW NOR ANY LICENSOR HAS ANY + * OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR + * MODIFICATIONS. */ /* @@ -29,12 +29,12 @@ * documentation for any purpose, without fee, and without written agreement is * hereby granted, provided that the above copyright notice, the following * two paragraphs and the author appear in all copies of this software. - * + * * IN NO EVENT SHALL THE VANDERBILT UNIVERSITY BE LIABLE TO ANY PARTY FOR * DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT * OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE VANDERBILT * UNIVERSITY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * * THE VANDERBILT UNIVERSITY SPECIFICALLY DISCLAIMS ANY WARRANTIES, * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS @@ -55,35 +55,35 @@ * @author Janos Sallai */ -module HplAtm128AdcP { +module HplAtm128AdcP @safe() { provides interface HplAtm128Adc; uses interface McuPowerState; } implementation { //=== Direct read of HW registers. ================================= - async command Atm128Admux_t HplAtm128Adc.getAdmux() { - return *(Atm128Admux_t*)&ADMUX; + async command Atm128Admux_t HplAtm128Adc.getAdmux() { + return *(Atm128Admux_t*)&ADMUX; } - async command Atm128Adcsra_t HplAtm128Adc.getAdcsra() { - return *(Atm128Adcsra_t*)&ADCSRA; + async command Atm128Adcsra_t HplAtm128Adc.getAdcsra() { + return *(Atm128Adcsra_t*)&ADCSRA; } - async command uint16_t HplAtm128Adc.getValue() { - return ADC; + async command uint16_t HplAtm128Adc.getValue() { + return ADC; } DEFINE_UNION_CAST(Admux2int, Atm128Admux_t, uint8_t); DEFINE_UNION_CAST(Adcsra2int, Atm128Adcsra_t, uint8_t); //=== Direct write of HW registers. ================================ - async command void HplAtm128Adc.setAdmux( Atm128Admux_t x ) { - ADMUX = Admux2int(x); + async command void HplAtm128Adc.setAdmux( Atm128Admux_t x ) { + ADMUX = Admux2int(x); } - async command void HplAtm128Adc.setAdcsra( Atm128Adcsra_t x ) { - ADCSRA = Adcsra2int(x); + async command void HplAtm128Adc.setAdcsra( Atm128Adcsra_t x ) { + ADCSRA = Adcsra2int(x); } async command void HplAtm128Adc.setPrescaler(uint8_t scale){ - Atm128Adcsra_t current_val = call HplAtm128Adc.getAdcsra(); + Atm128Adcsra_t current_val = call HplAtm128Adc.getAdcsra(); current_val.adif = FALSE; current_val.adps = scale; call HplAtm128Adc.setAdcsra(current_val); @@ -92,17 +92,17 @@ implementation { // Individual bit manipulation. These all clear any pending A/D interrupt. // It's not clear these are that useful... async command void HplAtm128Adc.enableAdc() { - SET_BIT(ADCSRA, ADEN); + SET_BIT(ADCSRA, ADEN); call McuPowerState.update(); } async command void HplAtm128Adc.disableAdc() { - CLR_BIT(ADCSRA, ADEN); + CLR_BIT(ADCSRA, ADEN); call McuPowerState.update(); } async command void HplAtm128Adc.enableInterruption() { SET_BIT(ADCSRA, ADIE); } async command void HplAtm128Adc.disableInterruption() { CLR_BIT(ADCSRA, ADIE); } - async command void HplAtm128Adc.setContinuous() { - ((Atm128Adcsrb_t*)&ADCSRB)->adts = 0; + async command void HplAtm128Adc.setContinuous() { + ((Atm128Adcsrb_t*)&ADCSRB)->adts = 0; SET_BIT(ADCSRA, ADATE); } async command void HplAtm128Adc.setSingle() { CLR_BIT(ADCSRA, ADATE); } @@ -111,29 +111,29 @@ implementation { /* A/D status checks */ - async command bool HplAtm128Adc.isEnabled() { - return (call HplAtm128Adc.getAdcsra()).aden; + async command bool HplAtm128Adc.isEnabled() { + return (call HplAtm128Adc.getAdcsra()).aden; } async command bool HplAtm128Adc.isStarted() { - return (call HplAtm128Adc.getAdcsra()).adsc; + return (call HplAtm128Adc.getAdcsra()).adsc; } - + async command bool HplAtm128Adc.isComplete() { - return (call HplAtm128Adc.getAdcsra()).adif; + return (call HplAtm128Adc.getAdcsra()).adif; } /* A/D interrupt handlers. Signals dataReady event with interrupts enabled */ AVR_ATOMIC_HANDLER(SIG_ADC) { uint16_t data = call HplAtm128Adc.getValue(); - + __nesc_enable_interrupt(); signal HplAtm128Adc.dataReady(data); } default async event void HplAtm128Adc.dataReady(uint16_t done) { } - async command bool HplAtm128Adc.cancel() { + async command bool HplAtm128Adc.cancel() { /* This is tricky */ atomic { diff --git a/tos/chips/atm1281/atm128hardware.h b/tos/chips/atm1281/atm128hardware.h index 2e52a8fb..56ef6d10 100644 --- a/tos/chips/atm1281/atm128hardware.h +++ b/tos/chips/atm1281/atm128hardware.h @@ -1,4 +1,4 @@ -/* +/* * IMPORTANT: READ BEFORE DOWNLOADING, COPYING, INSTALLING OR USING. By * downloading, copying, installing or using the software you agree to * this license. If you do not agree to this license, do not download, @@ -6,7 +6,7 @@ * * Copyright (c) 2004-2005 Crossbow Technology, Inc. * Copyright (c) 2002-2003 Intel Corporation. - * Copyright (c) 2000-2003 The Regents of the University of California. + * Copyright (c) 2000-2003 The Regents of the University of California. * All rights reserved. * * Permission to use, copy, modify, and distribute this software and its @@ -39,12 +39,12 @@ * documentation for any purpose, without fee, and without written agreement is * hereby granted, provided that the above copyright notice, the following * two paragraphs and the author appear in all copies of this software. - * + * * IN NO EVENT SHALL THE VANDERBILT UNIVERSITY BE LIABLE TO ANY PARTY FOR * DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT * OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE VANDERBILT * UNIVERSITY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * * THE VANDERBILT UNIVERSITY SPECIFICALLY DISCLAIMS ANY WARRANTIES, * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS @@ -102,11 +102,11 @@ #define READ_FLAG(port, flag) ((port) & (flag)) /* Enables interrupts. */ -inline void __nesc_enable_interrupt() { +inline void __nesc_enable_interrupt() @safe() { sei(); } /* Disables all interrupts. */ -inline void __nesc_disable_interrupt() { +inline void __nesc_disable_interrupt() @safe() { cli(); } @@ -122,8 +122,8 @@ void __nesc_atomic_end(__nesc_atomic_t original_SREG); though. */ /* Saves current interrupt mask state and disables interrupts. */ -inline __nesc_atomic_t -__nesc_atomic_start(void) @spontaneous() +inline __nesc_atomic_t +__nesc_atomic_start(void) @spontaneous() @safe() { __nesc_atomic_t result = SREG; __nesc_disable_interrupt(); @@ -132,8 +132,8 @@ __nesc_atomic_start(void) @spontaneous() } /* Restores interrupt mask to original state. */ -inline void -__nesc_atomic_end(__nesc_atomic_t original_SREG) @spontaneous() +inline void +__nesc_atomic_end(__nesc_atomic_t original_SREG) @spontaneous() @safe() { asm volatile("" : : : "memory"); /* ensure atomic section effect visibility */ SREG = original_SREG; @@ -150,11 +150,11 @@ enum { ATM128_POWER_EXT_STANDBY = 2, ATM128_POWER_SAVE = 3, ATM128_POWER_STANDBY = 4, - ATM128_POWER_DOWN = 5, + ATM128_POWER_DOWN = 5, }; /* Combine function. */ -mcu_power_t mcombine(mcu_power_t m1, mcu_power_t m2) { +mcu_power_t mcombine(mcu_power_t m1, mcu_power_t m2) @safe() { return (m1 < m2)? m1: m2; } diff --git a/tos/chips/atm1281/timer/Atm1281AlarmAsyncP.nc b/tos/chips/atm1281/timer/Atm1281AlarmAsyncP.nc index 7dd543b6..927eea79 100644 --- a/tos/chips/atm1281/timer/Atm1281AlarmAsyncP.nc +++ b/tos/chips/atm1281/timer/Atm1281AlarmAsyncP.nc @@ -3,9 +3,9 @@ * Copyright (c) 2007 Intel Corporation * All rights reserved. * - * This file is distributed under the terms in the attached INTEL-LICENSE + * This file is distributed under the terms in the attached INTEL-LICENSE * file. If you do not find these files, copies can be found by writing to - * Intel Research Berkeley, 2150 Shattuck Avenue, Suite 1300, Berkeley, CA, + * Intel Research Berkeley, 2150 Shattuck Avenue, Suite 1300, Berkeley, CA, * 94704. Attention: Intel License Inquiry. */ @@ -17,12 +17,12 @@ * documentation for any purpose, without fee, and without written agreement is * hereby granted, provided that the above copyright notice, the following * two paragraphs and the author appear in all copies of this software. - * + * * IN NO EVENT SHALL THE VANDERBILT UNIVERSITY BE LIABLE TO ANY PARTY FOR * DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT * OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE VANDERBILT * UNIVERSITY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * * THE VANDERBILT UNIVERSITY SPECIFICALLY DISCLAIMS ANY WARRANTIES, * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS @@ -30,13 +30,13 @@ * PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. * */ - + /** * Build a 32-bit alarm and counter from the atmega1281's 8-bit timer 2 * in asynchronous mode. Attempting to use the generic Atm128AlarmC * component and the generic timer components runs into problems * apparently related to letting timer 2 overflow. - * + * * So, instead, this version (inspired by the 1.x code and a remark from * Martin Turon) directly builds a 32-bit alarm and counter on top of timer 2 * and never lets timer 2 overflow. @@ -44,7 +44,7 @@ * @author David Gay * @author Janos Sallai */ -generic module Atm1281AlarmAsyncP(typedef precision, int divider) { +generic module Atm1281AlarmAsyncP(typedef precision, int divider) @safe() { provides { interface Init; interface Alarm; @@ -80,7 +80,7 @@ implementation { Atm128_TCCR2A_t x; Atm128_TCCR2B_t y; - + call TimerAsync.setTimer2Asynchronous(); x.flat = 0; x.bits.wgm21 = 1; /* We use the clear-on-compare mode */ @@ -95,7 +95,7 @@ implementation return SUCCESS; } - /* Set compare register for timer 2 to n. But increment n by 1 if TCNT2 + /* Set compare register for timer 2 to n. But increment n by 1 if TCNT2 reaches this value before we can set the compare register. */ void setOcr2A(uint8_t n) { @@ -103,7 +103,7 @@ implementation ; if (n == call Timer.get()) n++; - /* Support for overflow. Force interrupt at wrap around value. + /* Support for overflow. Force interrupt at wrap around value. This does not cause a backwards-in-time value as we do this every time we set OCR2A. */ if (base + n + 1 < base) @@ -183,7 +183,7 @@ implementation setInterrupt(); if (overflowed) signal Counter.overflow(); - } + } async command uint32_t Counter.get() { uint32_t now; @@ -212,7 +212,7 @@ implementation !(base + call Compare.get() + 1); } - async command void Counter.clearOverflow() { + async command void Counter.clearOverflow() { atomic if (call Counter.isOverflowPending()) { diff --git a/tos/chips/atm1281/timer/HplAtm1281Timer1P.nc b/tos/chips/atm1281/timer/HplAtm1281Timer1P.nc index 0f6b4389..efc4868d 100644 --- a/tos/chips/atm1281/timer/HplAtm1281Timer1P.nc +++ b/tos/chips/atm1281/timer/HplAtm1281Timer1P.nc @@ -6,18 +6,18 @@ * documentation for any purpose, without fee, and without written agreement is * hereby granted, provided that the above copyright notice, the following * two paragraphs and the author appear in all copies of this software. - * - * IN NO EVENT SHALL CROSSBOW TECHNOLOGY OR ANY OF ITS LICENSORS BE LIABLE TO - * ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL + * + * IN NO EVENT SHALL CROSSBOW TECHNOLOGY OR ANY OF ITS LICENSORS BE LIABLE TO + * ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL * DAMAGES ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN - * IF CROSSBOW OR ITS LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. + * IF CROSSBOW OR ITS LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. * * CROSSBOW TECHNOLOGY AND ITS LICENSORS SPECIFICALLY DISCLAIM ALL WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY - * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS - * ON AN "AS IS" BASIS, AND NEITHER CROSSBOW NOR ANY LICENSOR HAS ANY - * OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS + * ON AN "AS IS" BASIS, AND NEITHER CROSSBOW NOR ANY LICENSOR HAS ANY + * OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR * MODIFICATIONS. */ @@ -29,12 +29,12 @@ * documentation for any purpose, without fee, and without written agreement is * hereby granted, provided that the above copyright notice, the following * two paragraphs and the author appear in all copies of this software. - * + * * IN NO EVENT SHALL THE VANDERBILT UNIVERSITY BE LIABLE TO ANY PARTY FOR * DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT * OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE VANDERBILT * UNIVERSITY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * * THE VANDERBILT UNIVERSITY SPECIFICALLY DISCLAIMS ANY WARRANTIES, * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS @@ -52,7 +52,7 @@ #include -module HplAtm1281Timer1P +module HplAtm1281Timer1P @safe() { provides { // 16-bit Timers @@ -79,56 +79,56 @@ implementation async command void Timer.off() { call Timer.setScale(AVR_CLOCK_OFF); } //=== Write a new timer scale. ======================================== - async command void Timer.setScale(uint8_t s) { + async command void Timer.setScale(uint8_t s) { Atm128_TCCRB_t x = (Atm128_TCCRB_t) call TimerCtrl.getControlB(); x.bits.cs = s; - call TimerCtrl.setControlB(x.flat); + call TimerCtrl.setControlB(x.flat); } //=== Read the control registers. ===================================== - async command uint8_t TimerCtrl.getControlA() { - return TCCR1A; + async command uint8_t TimerCtrl.getControlA() { + return TCCR1A; } - async command uint8_t TimerCtrl.getControlB() { - return TCCR1B; + async command uint8_t TimerCtrl.getControlB() { + return TCCR1B; } - async command uint8_t TimerCtrl.getControlC() { - return TCCR1C; + async command uint8_t TimerCtrl.getControlC() { + return TCCR1C; } //=== Write the control registers. ==================================== - async command void TimerCtrl.setControlA( uint8_t x ) { - TCCR1A = x; + async command void TimerCtrl.setControlA( uint8_t x ) { + TCCR1A = x; } - async command void TimerCtrl.setControlB( uint8_t x ) { - TCCR1B = x; + async command void TimerCtrl.setControlB( uint8_t x ) { + TCCR1B = x; } - async command void TimerCtrl.setControlC( uint8_t x ) { - TCCR1C = x; + async command void TimerCtrl.setControlC( uint8_t x ) { + TCCR1C = x; } //=== Read the interrupt mask. ===================================== - async command uint8_t TimerCtrl.getInterruptMask() { - return TIMSK1; + async command uint8_t TimerCtrl.getInterruptMask() { + return TIMSK1; } //=== Write the interrupt mask. ==================================== - async command void TimerCtrl.setInterruptMask( uint8_t x ) { - TIMSK1 = x; + async command void TimerCtrl.setInterruptMask( uint8_t x ) { + TIMSK1 = x; } //=== Read the interrupt flags. ===================================== - async command uint8_t TimerCtrl.getInterruptFlag() { - return TIFR1; + async command uint8_t TimerCtrl.getInterruptFlag() { + return TIFR1; } //=== Write the interrupt flags. ==================================== - async command void TimerCtrl.setInterruptFlag( uint8_t x ) { - TIFR1 = x; + async command void TimerCtrl.setInterruptFlag( uint8_t x ) { + TIFR1 = x; } //=== Capture 16-bit implementation. =================================== @@ -153,20 +153,20 @@ implementation async command void CompareB.stop() { CLR_BIT(TIMSK1,OCIE1B); } async command void CompareC.stop() { CLR_BIT(TIMSK1,OCIE1C); } - async command bool Timer.test() { - return ((Atm128_TIFR_t)call TimerCtrl.getInterruptFlag()).bits.tov; + async command bool Timer.test() { + return ((Atm128_TIFR_t)call TimerCtrl.getInterruptFlag()).bits.tov; } - async command bool Capture.test() { - return ((Atm128_TIFR_t)call TimerCtrl.getInterruptFlag()).bits.icf; + async command bool Capture.test() { + return ((Atm128_TIFR_t)call TimerCtrl.getInterruptFlag()).bits.icf; } - async command bool CompareA.test() { - return ((Atm128_TIFR_t)call TimerCtrl.getInterruptFlag()).bits.ocfa; + async command bool CompareA.test() { + return ((Atm128_TIFR_t)call TimerCtrl.getInterruptFlag()).bits.ocfa; } - async command bool CompareB.test() { - return ((Atm128_TIFR_t)call TimerCtrl.getInterruptFlag()).bits.ocfb; + async command bool CompareB.test() { + return ((Atm128_TIFR_t)call TimerCtrl.getInterruptFlag()).bits.ocfb; } - async command bool CompareC.test() { - return ((Atm128_TIFR_t)call TimerCtrl.getInterruptFlag()).bits.ocfc; + async command bool CompareC.test() { + return ((Atm128_TIFR_t)call TimerCtrl.getInterruptFlag()).bits.ocfc; } async command bool Timer.isOn() { diff --git a/tos/chips/atm1281/timer/HplAtm1281Timer2AsyncP.nc b/tos/chips/atm1281/timer/HplAtm1281Timer2AsyncP.nc index b4b3623b..fa7d8b20 100644 --- a/tos/chips/atm1281/timer/HplAtm1281Timer2AsyncP.nc +++ b/tos/chips/atm1281/timer/HplAtm1281Timer2AsyncP.nc @@ -5,18 +5,18 @@ * documentation for any purpose, without fee, and without written agreement is * hereby granted, provided that the above copyright notice, the following * two paragraphs and the author appear in all copies of this software. - * - * IN NO EVENT SHALL CROSSBOW TECHNOLOGY OR ANY OF ITS LICENSORS BE LIABLE TO - * ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL + * + * IN NO EVENT SHALL CROSSBOW TECHNOLOGY OR ANY OF ITS LICENSORS BE LIABLE TO + * ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL * DAMAGES ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN - * IF CROSSBOW OR ITS LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. + * IF CROSSBOW OR ITS LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. * * CROSSBOW TECHNOLOGY AND ITS LICENSORS SPECIFICALLY DISCLAIM ALL WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY - * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS - * ON AN "AS IS" BASIS, AND NEITHER CROSSBOW NOR ANY LICENSOR HAS ANY - * OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS + * ON AN "AS IS" BASIS, AND NEITHER CROSSBOW NOR ANY LICENSOR HAS ANY + * OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR * MODIFICATIONS. */ @@ -28,12 +28,12 @@ * documentation for any purpose, without fee, and without written agreement is * hereby granted, provided that the above copyright notice, the following * two paragraphs and the author appear in all copies of this software. - * + * * IN NO EVENT SHALL THE VANDERBILT UNIVERSITY BE LIABLE TO ANY PARTY FOR * DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT * OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE VANDERBILT * UNIVERSITY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * * THE VANDERBILT UNIVERSITY SPECIFICALLY DISCLAIMS ANY WARRANTIES, * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS @@ -55,7 +55,7 @@ #include -module HplAtm1281Timer2AsyncP +module HplAtm1281Timer2AsyncP @safe() { provides { // 8-bit Timers @@ -92,52 +92,52 @@ implementation async command void Timer.off() { call Timer.setScale(AVR_CLOCK_OFF); } //=== Write a new timer scale. ======================================== - async command void Timer.setScale(uint8_t s) { + async command void Timer.setScale(uint8_t s) { Atm128_TCCR2B_t x = (Atm128_TCCR2B_t) call TimerCtrl.getControlB(); x.bits.cs = s; - call TimerCtrl.setControlB(x.flat); + call TimerCtrl.setControlB(x.flat); } //=== Read the control registers. ===================================== - async command uint8_t TimerCtrl.getControlA() { - return TCCR2A; + async command uint8_t TimerCtrl.getControlA() { + return TCCR2A; } - async command uint8_t TimerCtrl.getControlB() { - return TCCR2B; + async command uint8_t TimerCtrl.getControlB() { + return TCCR2B; } //=== Write the control registers. ==================================== - async command void TimerCtrl.setControlA( uint8_t x ) { + async command void TimerCtrl.setControlA( uint8_t x ) { while (ASSR & 1 << TCR2AUB) ; - TCCR2A = ((Atm128_TCCR2A_t)x).flat; + TCCR2A = ((Atm128_TCCR2A_t)x).flat; } - async command void TimerCtrl.setControlB( uint8_t x ) { + async command void TimerCtrl.setControlB( uint8_t x ) { while (ASSR & 1 << TCR2BUB) ; - TCCR2B = ((Atm128_TCCR2B_t)x).flat; + TCCR2B = ((Atm128_TCCR2B_t)x).flat; } //=== Read the interrupt mask. ===================================== - async command uint8_t TimerCtrl.getInterruptMask() { - return TIMSK2; + async command uint8_t TimerCtrl.getInterruptMask() { + return TIMSK2; } //=== Write the interrupt mask. ==================================== - async command void TimerCtrl.setInterruptMask( uint8_t x ) { - TIMSK2 = x; + async command void TimerCtrl.setInterruptMask( uint8_t x ) { + TIMSK2 = x; } //=== Read the interrupt flags. ===================================== - async command uint8_t TimerCtrl.getInterruptFlag() { - return TIFR2; + async command uint8_t TimerCtrl.getInterruptFlag() { + return TIFR2; } //=== Write the interrupt flags. ==================================== - async command void TimerCtrl.setInterruptFlag( uint8_t x ) { - TIFR2 = x; + async command void TimerCtrl.setInterruptFlag( uint8_t x ) { + TIFR2 = x; } //=== Timer 8-bit implementation. ==================================== @@ -146,37 +146,37 @@ implementation async command void Timer.stop() { CLR_BIT(TIMSK2, TOIE2); } bool overflowed() { - return ((Atm128_TIFR2_t)call TimerCtrl.getInterruptFlag()).bits.tov; + return ((Atm128_TIFR2_t)call TimerCtrl.getInterruptFlag()).bits.tov; } - async command bool Timer.test() { + async command bool Timer.test() { return overflowed(); } - - async command bool Timer.isOn() { - return ((Atm128_TIMSK2_t)call TimerCtrl.getInterruptMask()).bits.toie; + + async command bool Timer.isOn() { + return ((Atm128_TIMSK2_t)call TimerCtrl.getInterruptMask()).bits.toie; } - + async command void Compare.reset() { TIFR2 = 1 << OCF2A; } async command void Compare.start() { SET_BIT(TIMSK2,OCIE2A); } async command void Compare.stop() { CLR_BIT(TIMSK2,OCIE2A); } - async command bool Compare.test() { - return ((Atm128_TIFR2_t)call TimerCtrl.getInterruptFlag()).bits.ocfa; + async command bool Compare.test() { + return ((Atm128_TIFR2_t)call TimerCtrl.getInterruptFlag()).bits.ocfa; } - async command bool Compare.isOn() { - return ((Atm128_TIMSK2_t)call TimerCtrl.getInterruptMask()).bits.ociea; + async command bool Compare.isOn() { + return ((Atm128_TIMSK2_t)call TimerCtrl.getInterruptMask()).bits.ociea; } //=== Read the compare registers. ===================================== async command uint8_t Compare.get(){ return OCR2A; } //=== Write the compare registers. ==================================== - async command void Compare.set(uint8_t t) { + async command void Compare.set(uint8_t t) { atomic { while (ASSR & 1 << OCR2AUB) ; - OCR2A = t; + OCR2A = t; } } @@ -195,11 +195,11 @@ implementation * is needed. If the timer is not running it returns POWER_DOWN. * Please refer to TEP 112 and the atm128 datasheet for details. */ - + async command mcu_power_t McuPowerOverride.lowestState() { uint8_t diff; // We need to make sure that the sleep wakeup latency will not - // cause us to miss a timer. POWER_SAVE + // cause us to miss a timer. POWER_SAVE if (TIMSK2 & (1 << OCIE2A | 1 << TOIE2)) { // need to wait for timer 2 updates propagate before sleeping // (we don't need to worry about reentering sleep mode too early, @@ -209,7 +209,7 @@ implementation ; diff = OCR2A - TCNT2; if (diff < EXT_STANDBY_T0_THRESHOLD || - TCNT2 > 256 - EXT_STANDBY_T0_THRESHOLD) + TCNT2 > 256 - EXT_STANDBY_T0_THRESHOLD) return ATM128_POWER_EXT_STANDBY; return ATM128_POWER_SAVE; } @@ -222,7 +222,7 @@ implementation AVR_ATOMIC_HANDLER(SIG_OUTPUT_COMPARE2A) { stabiliseTimer2(); // __nesc_enable_interrupt(); - + signal Compare.fired(); } diff --git a/tos/chips/atm1281/timer/HplAtm1281Timer3P.nc b/tos/chips/atm1281/timer/HplAtm1281Timer3P.nc index 9f25ec6e..e0612fef 100644 --- a/tos/chips/atm1281/timer/HplAtm1281Timer3P.nc +++ b/tos/chips/atm1281/timer/HplAtm1281Timer3P.nc @@ -6,18 +6,18 @@ * documentation for any purpose, without fee, and without written agreement is * hereby granted, provided that the above copyright notice, the following * two paragraphs and the author appear in all copies of this software. - * - * IN NO EVENT SHALL CROSSBOW TECHNOLOGY OR ANY OF ITS LICENSORS BE LIABLE TO - * ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL + * + * IN NO EVENT SHALL CROSSBOW TECHNOLOGY OR ANY OF ITS LICENSORS BE LIABLE TO + * ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL * DAMAGES ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN - * IF CROSSBOW OR ITS LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. + * IF CROSSBOW OR ITS LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. * * CROSSBOW TECHNOLOGY AND ITS LICENSORS SPECIFICALLY DISCLAIM ALL WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY - * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS - * ON AN "AS IS" BASIS, AND NEITHER CROSSBOW NOR ANY LICENSOR HAS ANY - * OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS + * ON AN "AS IS" BASIS, AND NEITHER CROSSBOW NOR ANY LICENSOR HAS ANY + * OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR * MODIFICATIONS. */ @@ -29,12 +29,12 @@ * documentation for any purpose, without fee, and without written agreement is * hereby granted, provided that the above copyright notice, the following * two paragraphs and the author appear in all copies of this software. - * + * * IN NO EVENT SHALL THE VANDERBILT UNIVERSITY BE LIABLE TO ANY PARTY FOR * DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT * OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE VANDERBILT * UNIVERSITY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * * THE VANDERBILT UNIVERSITY SPECIFICALLY DISCLAIMS ANY WARRANTIES, * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS @@ -52,7 +52,7 @@ #include -module HplAtm1281Timer3P +module HplAtm1281Timer3P @safe() { provides { // 16-bit Timers @@ -79,56 +79,56 @@ implementation async command void Timer.off() { call Timer.setScale(AVR_CLOCK_OFF); } //=== Write a new timer scale. ======================================== - async command void Timer.setScale(uint8_t s) { + async command void Timer.setScale(uint8_t s) { Atm128_TCCRB_t x = (Atm128_TCCRB_t) call TimerCtrl.getControlB(); x.bits.cs = s; - call TimerCtrl.setControlB(x.flat); + call TimerCtrl.setControlB(x.flat); } //=== Read the control registers. ===================================== - async command uint8_t TimerCtrl.getControlA() { - return TCCR3A; + async command uint8_t TimerCtrl.getControlA() { + return TCCR3A; } - async command uint8_t TimerCtrl.getControlB() { - return TCCR3B; + async command uint8_t TimerCtrl.getControlB() { + return TCCR3B; } - async command uint8_t TimerCtrl.getControlC() { - return TCCR3C; + async command uint8_t TimerCtrl.getControlC() { + return TCCR3C; } //=== Write the control registers. ==================================== - async command void TimerCtrl.setControlA( uint8_t x ) { - TCCR3A = x; + async command void TimerCtrl.setControlA( uint8_t x ) { + TCCR3A = x; } - async command void TimerCtrl.setControlB( uint8_t x ) { - TCCR3B = x; + async command void TimerCtrl.setControlB( uint8_t x ) { + TCCR3B = x; } - async command void TimerCtrl.setControlC( uint8_t x ) { - TCCR3C = x; + async command void TimerCtrl.setControlC( uint8_t x ) { + TCCR3C = x; } //=== Read the interrupt mask. ===================================== - async command uint8_t TimerCtrl.getInterruptMask() { - return TIMSK3; + async command uint8_t TimerCtrl.getInterruptMask() { + return TIMSK3; } //=== Write the interrupt mask. ==================================== - async command void TimerCtrl.setInterruptMask( uint8_t x ) { - TIMSK3 = x; + async command void TimerCtrl.setInterruptMask( uint8_t x ) { + TIMSK3 = x; } //=== Read the interrupt flags. ===================================== - async command uint8_t TimerCtrl.getInterruptFlag() { - return TIFR3; + async command uint8_t TimerCtrl.getInterruptFlag() { + return TIFR3; } //=== Write the interrupt flags. ==================================== - async command void TimerCtrl.setInterruptFlag( uint8_t x ) { - TIFR3 = x; + async command void TimerCtrl.setInterruptFlag( uint8_t x ) { + TIFR3 = x; } //=== Capture 16-bit implementation. =================================== @@ -153,20 +153,20 @@ implementation async command void CompareB.stop() { CLR_BIT(TIMSK3,OCIE3B); } async command void CompareC.stop() { CLR_BIT(TIMSK3,OCIE3C); } - async command bool Timer.test() { - return ((Atm128_TIFR_t)call TimerCtrl.getInterruptFlag()).bits.tov; + async command bool Timer.test() { + return ((Atm128_TIFR_t)call TimerCtrl.getInterruptFlag()).bits.tov; } - async command bool Capture.test() { - return ((Atm128_TIFR_t)call TimerCtrl.getInterruptFlag()).bits.icf; + async command bool Capture.test() { + return ((Atm128_TIFR_t)call TimerCtrl.getInterruptFlag()).bits.icf; } - async command bool CompareA.test() { - return ((Atm128_TIFR_t)call TimerCtrl.getInterruptFlag()).bits.ocfa; + async command bool CompareA.test() { + return ((Atm128_TIFR_t)call TimerCtrl.getInterruptFlag()).bits.ocfa; } - async command bool CompareB.test() { - return ((Atm128_TIFR_t)call TimerCtrl.getInterruptFlag()).bits.ocfb; + async command bool CompareB.test() { + return ((Atm128_TIFR_t)call TimerCtrl.getInterruptFlag()).bits.ocfb; } - async command bool CompareC.test() { - return ((Atm128_TIFR_t)call TimerCtrl.getInterruptFlag()).bits.ocfc; + async command bool CompareC.test() { + return ((Atm128_TIFR_t)call TimerCtrl.getInterruptFlag()).bits.ocfc; } async command bool Timer.isOn() { -- 2.39.2