From b80bf3d26be7066d064ac117ac12876e4a383d4f Mon Sep 17 00:00:00 2001
From: smckown <smckown@4bc1554a-c7f2-4f65-a403-e0be01f0239c>
Date: Tue, 28 Apr 2009 18:59:05 +0000
Subject: [PATCH] Add feature to optionally clear PxREN bits for SPI comms.

---
 tos/chips/msp430/usci/Msp430SpiP.nc | 40 ++++++++++++++++++++++++++++-
 1 file changed, 39 insertions(+), 1 deletion(-)

diff --git a/tos/chips/msp430/usci/Msp430SpiP.nc b/tos/chips/msp430/usci/Msp430SpiP.nc
index ed3a331a..dad8e824 100644
--- a/tos/chips/msp430/usci/Msp430SpiP.nc
+++ b/tos/chips/msp430/usci/Msp430SpiP.nc
@@ -32,6 +32,8 @@
  *
  * TODO: Implement error checking via UCxxSTAT
  *
+ * NOTE: Define NO_REN_ON_SPI to disable PxREN bits when SPI is acquired.
+ *
  * @author R. Steve McKown <rsmckown@gmail.com>
  */
  
@@ -57,10 +59,13 @@ implementation {
     BLOCKSIZE_DEFAULT = 64,
 
     /* Bit positions in m_pins */
-    PINS_STE = 1,
+    PINS_STE = 0,
     PINS_SOMI,
     PINS_SIMO,
     PINS_CLK,
+#ifdef NO_REN_ON_SPI
+    PINS_RENADDR,	/* This gets added to store the PxREN bit */
+#endif
   };
 
   uint8_t m_pins;
@@ -107,6 +112,26 @@ implementation {
 
       /* Configure pins for SPI, saving prior pin states */
       m_pins = 0;
+#ifdef NO_REN_ON_SPI
+      /* - First save off and disable PxREN bits */
+      if (is4pin() && call STE.isRen()) {
+	m_pins |= (1 << (PINS_STE + PINS_RENADDR));
+	call STE.disableRen();
+      }
+      if (call SOMI.isRen()) {
+	m_pins |= (1 << (PINS_SOMI + PINS_RENADDR));
+	call SOMI.disableRen();
+      }
+      if (call SIMO.isRen()) {
+	m_pins |= (1 << (PINS_SIMO + PINS_RENADDR));
+	call SIMO.disableRen();
+      }
+      if (call CLK.isRen()) {
+	m_pins |= (1 << (PINS_CLK + PINS_RENADDR));
+	call CLK.disableRen();
+      }
+#endif
+      /* - Then save off IOFunc state and enable ModuleFunc */
       if (is4pin() && call STE.isIOFunc()) {
 	m_pins |= (1 << PINS_STE);
 	call STE.selectModuleFunc();
@@ -144,6 +169,7 @@ implementation {
       call Registers.clrIfgRx();
 
       /* Restore pins to their pre-configure state */
+      /* - First restore IOFunc states */
       if (is4pin() && (m_pins & (1 << PINS_STE)))
 	call STE.selectIOFunc();
       if (m_pins & (1 << PINS_SIMO))
@@ -152,6 +178,17 @@ implementation {
 	call SOMI.selectIOFunc();
       if (m_pins & (1 << PINS_CLK))
 	call CLK.selectIOFunc();
+      /* - Then restore PxREN bits */
+#ifdef NO_REN_ON_SPI
+      if (is4pin() && (m_pins & (1 << (PINS_STE + PINS_RENADDR))))
+	call STE.enableRen();
+      if (m_pins & (1 << (PINS_SIMO + PINS_RENADDR)))
+	call SIMO.enableRen();
+      if (m_pins & (1 << (PINS_SOMI + PINS_RENADDR)))
+	call SOMI.enableRen();
+      if (m_pins & (1 << (PINS_CLK + PINS_RENADDR)))
+	call CLK.enableRen();
+#endif
     }
   }
 
@@ -186,6 +223,7 @@ implementation {
 	tmp = call Registers.getRxbuf();
 	if (m_rxBuf)
 	  m_rxBuf[m_pos - 1] = call Registers.getRxbuf();
+	while (!call Registers.getIfgTx() && !call Registers.getCtl1(UCSWRST));
 	call Registers.setTxbuf(m_txBuf ? m_txBuf[m_pos] : 0);
       }
     }
-- 
2.39.2