X-Git-Url: https://oss.titaniummirror.com/gitweb?a=blobdiff_plain;f=gcc%2Fconfig%2Ffr30%2Ffr30.md;fp=gcc%2Fconfig%2Ffr30%2Ffr30.md;h=a198ea3544dbadcfc84d6f497ccd21441070e55a;hb=6fed43773c9b0ce596dca5686f37ac3fc0fa11c0;hp=1177c680b42f7643705fcc2490c3edf39740d54d;hpb=27b11d56b743098deb193d510b337ba22dc52e5c;p=msp430-gcc.git diff --git a/gcc/config/fr30/fr30.md b/gcc/config/fr30/fr30.md index 1177c680..a198ea35 100644 --- a/gcc/config/fr30/fr30.md +++ b/gcc/config/fr30/fr30.md @@ -1,27 +1,26 @@ ;; FR30 machine description. -;; Copyright (C) 1998, 1999, 2000 Free Software Foundation, Inc. +;; Copyright (C) 1998, 1999, 2000, 2002, 2004, 2005, 2007 +;; Free Software Foundation, Inc. ;; Contributed by Cygnus Solutions. -;; This file is part of GNU CC. +;; This file is part of GCC. -;; GNU CC is free software; you can redistribute it and/or modify +;; GCC is free software; you can redistribute it and/or modify ;; it under the terms of the GNU General Public License as published by -;; the Free Software Foundation; either version 2, or (at your option) +;; the Free Software Foundation; either version 3, or (at your option) ;; any later version. -;; GNU CC is distributed in the hope that it will be useful, +;; GCC is distributed in the hope that it will be useful, ;; but WITHOUT ANY WARRANTY; without even the implied warranty of ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ;; GNU General Public License for more details. ;; You should have received a copy of the GNU General Public License -;; along with GNU CC; see the file COPYING. If not, write to -;; the Free Software Foundation, 59 Temple Place - Suite 330, -;; Boston, MA 02111-1307, USA. +;; along with GCC; see the file COPYING3. If not see +;; . ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. -;;}}} ;;{{{ Attributes (define_attr "length" "" (const_int 2)) @@ -35,11 +34,11 @@ ;; Define an attribute to be used by the delay slot code. -;; An instruction by default is considered to be 'delyabable' +;; An instruction by default is considered to be 'delayable' ;; that is, it can be placed into a delay slot, but it is not -;; itself an delyaed branch type instruction. An instruction -;; whoes type is 'delayed' is one which has a delay slot, and -;; an instruction whoes delay_type is 'other' is one which does +;; itself a delayed branch type instruction. An instruction +;; whose type is 'delayed' is one which has a delay slot, and +;; an instruction whose delay_type is 'other' is one which does ;; not have a delay slot, nor can it be placed into a delay slot. (define_attr "delay_type" "delayable,delayed,other" (const_string "delayable")) @@ -54,6 +53,8 @@ (nil)] ) +(include "predicates.md") + ;;}}} ;;{{{ Moves @@ -287,12 +288,15 @@ ;; and time by loading the positive value and then sign extending it. (define_split [(set (match_operand:SI 0 "register_operand" "") - (match_operand:SI 1 "immediate_operand" ""))] - "INTVAL (operands[1]) <= -1 && INTVAL (operands[1]) >= -128" - [(set:SI (match_dup 0) (match_dup 2)) - (set:SI (match_dup 0) (sign_extend:SI (subreg:QI (match_dup 0) 0)))] + (match_operand:SI 1 "const_int_operand" ""))] + "INTVAL (operands[1]) <= -1 && INTVAL (operands[1]) >= -128 + && (GET_CODE (operands[0]) != SUBREG + || SCALAR_INT_MODE_P (GET_MODE (XEXP (operands[0], 0))))" + [(set:SI (match_dup 0) (match_dup 1)) + (set:SI (match_dup 0) (sign_extend:SI (match_dup 2)))] "{ - operands[2] = GEN_INT (INTVAL (operands[1]) & 0xff); + operands[1] = GEN_INT (INTVAL (operands[1]) & 0xff); + operands[2] = gen_lowpart (QImode, operands[0]); }" ) @@ -301,7 +305,7 @@ ;; and space by loading the byte value and shifting it into place. (define_split [(set (match_operand:SI 0 "register_operand" "") - (match_operand:SI 1 "immediate_operand" ""))] + (match_operand:SI 1 "const_int_operand" ""))] "(INTVAL (operands[1]) < 0) && ((INTVAL (operands[1]) & 0x00ffffff) == 0)" [(set:SI (match_dup 0) (match_dup 2)) (parallel [(set:SI (match_dup 0) (ashift:SI (match_dup 0) (const_int 24))) @@ -313,12 +317,12 @@ ) ;; If we are loading a large positive constant, one which has bits -;; in the top byte set, but whoes set bits all lie within an 8 bit +;; in the top byte set, but whose set bits all lie within an 8 bit ;; range, then we can save time and space by loading the byte value ;; and shifting it into place. (define_split [(set (match_operand:SI 0 "register_operand" "") - (match_operand:SI 1 "immediate_operand" ""))] + (match_operand:SI 1 "const_int_operand" ""))] "(INTVAL (operands[1]) > 0x00ffffff) && ((INTVAL (operands[1]) >> exact_log2 (INTVAL (operands[1]) & (- INTVAL (operands[1])))) < 0x100)" [(set:SI (match_dup 0) (match_dup 2)) @@ -336,8 +340,8 @@ ;; values are addresses which will fit in 20 bits. (define_insn "movsi_internal" - [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,red,m,r") - (match_operand:SI 1 "general_operand" "L,M,n,i,rde,r,rm"))] + [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,red,V,r,m") + (match_operand:SI 1 "general_operand" "L,M,n,i,rde,r,rm,r"))] "" "* { @@ -353,8 +357,9 @@ case 4: return \"mov \\t%1, %0\"; case 5: return \"st \\t%1, %0\"; case 6: return \"ld \\t%1, %0\"; - default: abort (); - } + case 7: return \"st \\t%1, %0\"; + default: gcc_unreachable (); + } }" [(set (attr "length") (cond [(eq_attr "alternative" "1") (const_int 4) (eq_attr "alternative" "2") (const_int 6) @@ -370,26 +375,27 @@ ;; Note - the FR30 does not have an 8 byte load/store instruction ;; but we have to support this pattern because some other patterns -;; (eg muldisi2) can produce a DImode result. +;; (e.g. muldisi2) can produce a DImode result. ;; (This code is stolen from the M32R port.) (define_expand "movdi" - [(set (match_operand:DI 0 "general_operand" "") - (match_operand:DI 1 "general_operand" ""))] + [(set (match_operand:DI 0 "nonimmediate_operand" "") + (match_operand:DI 1 "general_operand" ""))] "" " /* Everything except mem = const or mem = mem can be done easily. */ - + if (GET_CODE (operands[0]) == MEM) operands[1] = force_reg (DImode, operands[1]); - ") + " +) ;; We use an insn and a split so that we can generate ;; RTL rather than text from fr30_move_double(). (define_insn "*movdi_insn" [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r,r,m,r") - (match_operand:DI 1 "di_operand" "r,m,r,nF"))] + (match_operand:DI 1 "di_operand" "r,m,r,nF"))] "register_operand (operands[0], DImode) || register_operand (operands[1], DImode)" "#" [(set_attr "length" "4,8,12,12")] @@ -397,10 +403,11 @@ (define_split [(set (match_operand:DI 0 "nonimmediate_di_operand" "") - (match_operand:DI 1 "di_operand" ""))] + (match_operand:DI 1 "di_operand" ""))] "reload_completed" [(match_dup 2)] - "operands[2] = fr30_move_double (operands);") + "operands[2] = fr30_move_double (operands);" +) ;;}}} ;;{{{ Load & Store Multiple Registers @@ -521,7 +528,7 @@ ;;{{{ Floating Point Moves ;; Note - Patterns for SF mode moves are compulsory, but -;; patterns for DF are optional, as GCC can synthesise them. +;; patterns for DF are optional, as GCC can synthesize them. (define_expand "movsf" [(set (match_operand:SF 0 "general_operand" "") @@ -551,7 +558,7 @@ case 2: return \"mov \\t%1, %0\"; case 3: return \"st \\t%1, %0\"; case 4: return \"ld \\t%1, %0\"; - default: abort (); + default: gcc_unreachable (); } }" [(set (attr "length") (cond [(eq_attr "alternative" "0") (const_int 6) @@ -571,14 +578,9 @@ const char * ldi_instr; const char * tmp_reg; static char buffer[100]; - REAL_VALUE_TYPE d; - REAL_VALUE_FROM_CONST_DOUBLE (d, operands[1]); - - if (REAL_VALUES_EQUAL (d, dconst0)) - ldi_instr = \"ldi:8\"; - else - ldi_instr = \"ldi:32\"; + ldi_instr = fr30_const_double_is_zero (operands[1]) + ? ldi_instr = \"ldi:8\" : \"ldi:32\"; tmp_reg = reg_names [COMPILER_SCRATCH_REGISTER]; @@ -642,9 +644,9 @@ ) ;; We need some trickery to be able to handle the addition of -;; large (ie outside +/- 16) constants. We need to be able to +;; large (i.e. outside +/- 16) constants. We need to be able to ;; handle this because reload assumes that it can generate add -;; instructions with arbitary sized constants. +;; instructions with arbitrary sized constants. (define_expand "addsi3" [(set (match_operand:SI 0 "register_operand" "") (plus:SI (match_operand:SI 1 "register_operand" "") @@ -656,10 +658,11 @@ emit_insn (gen_addsi_regs (operands[0], operands[1], operands[2])); else if (GET_CODE (operands[2]) != CONST_INT) emit_insn (gen_addsi_big_int (operands[0], operands[1], operands[2])); - else if ( (REGNO (operands[1]) != FRAME_POINTER_REGNUM) - && (REGNO (operands[1]) != ARG_POINTER_REGNUM) - && (INTVAL (operands[2]) >= -16) - && (INTVAL (operands[2]) <= 15)) + else if (INTVAL (operands[2]) >= -16 + && INTVAL (operands[2]) <= 15 + && (!REG_P (operands[1]) + || !REGNO_PTR_FRAME_P (REGNO (operands[1])) + || REGNO (operands[1]) == STACK_POINTER_REGNUM)) emit_insn (gen_addsi_small_int (operands[0], operands[1], operands[2])); else emit_insn (gen_addsi_big_int (operands[0], operands[1], operands[2])); @@ -676,14 +679,15 @@ ) ;; Do not allow an eliminable register in the source register. It -;; might be eliminated in favour of the stack pointer, probably +;; might be eliminated in favor of the stack pointer, probably ;; increasing the offset, and so rendering the instruction illegal. (define_insn "addsi_small_int" [(set (match_operand:SI 0 "register_operand" "=r,r") (plus:SI (match_operand:SI 1 "register_operand" "0,0") (match_operand:SI 2 "add_immediate_operand" "I,J")))] - " (REGNO (operands[1]) != FRAME_POINTER_REGNUM) - && (REGNO (operands[1]) != ARG_POINTER_REGNUM)" + "!REG_P (operands[1]) + || !REGNO_PTR_FRAME_P (REGNO (operands[1])) + || REGNO (operands[1]) == STACK_POINTER_REGNUM" "@ addn %2, %0 addn2 %2, %0" @@ -696,7 +700,7 @@ "" "{ /* Cope with the possibility that ops 0 and 1 are the same register. */ - if (REGNO (operands[0]) == REGNO (operands[1])) + if (rtx_equal_p (operands[0], operands[1])) { if (reload_in_progress || reload_completed) { @@ -746,7 +750,7 @@ ;;}}} ;;{{{ Multiplication -;; Signed multiplication producing 64 bit results from 32 bit inputs +;; Signed multiplication producing 64-bit results from 32-bit inputs (define_insn "mulsidi3" [(set (match_operand:DI 0 "register_operand" "=r") (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "%r")) @@ -757,7 +761,7 @@ [(set_attr "length" "6")] ) -;; Unsigned multiplication producing 64 bit results from 32 bit inputs +;; Unsigned multiplication producing 64-bit results from 32-bit inputs (define_insn "umulsidi3" [(set (match_operand:DI 0 "register_operand" "=r") (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%r")) @@ -768,7 +772,7 @@ [(set_attr "length" "6")] ) -;; Signed multiplication producing 32 bit result from 16 bit inputs +;; Signed multiplication producing 32-bit result from 16-bit inputs (define_insn "mulhisi3" [(set (match_operand:SI 0 "register_operand" "=r") (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%r")) @@ -779,7 +783,7 @@ [(set_attr "length" "4")] ) -;; Unsigned multiplication producing 32 bit result from 16 bit inputs +;; Unsigned multiplication producing 32-bit result from 16-bit inputs (define_insn "umulhisi3" [(set (match_operand:SI 0 "register_operand" "=r") (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%r")) @@ -790,7 +794,7 @@ [(set_attr "length" "4")] ) -;; Signed multiplication producing 32 bit result from 32 bit inputs +;; Signed multiplication producing 32-bit result from 32-bit inputs (define_insn "mulsi3" [(set (match_operand:SI 0 "register_operand" "=r") (mult:SI (match_operand:SI 1 "register_operand" "%r") @@ -802,43 +806,6 @@ ) ;;}}} -;;{{{ Negation - -(define_expand "negsi2" - [(set (match_operand:SI 0 "register_operand" "") - (neg:SI (match_operand:SI 1 "register_operand" "")))] - "" - "{ - if (REGNO (operands[0]) == REGNO (operands[1])) - { - if (reload_in_progress || reload_completed) - { - rtx reg = gen_rtx_REG (SImode, 0/*COMPILER_SCRATCH_REGISTER*/); - - emit_insn (gen_movsi (reg, GEN_INT (0))); - emit_insn (gen_subsi3 (reg, reg, operands[0])); - emit_insn (gen_movsi (operands[0], reg)); - } - else - { - rtx reg = gen_reg_rtx (SImode); - - emit_insn (gen_movsi (reg, GEN_INT (0))); - emit_insn (gen_subsi3 (reg, reg, operands[0])); - emit_insn (gen_movsi (operands[0], reg)); - } - } - else - { - emit_insn (gen_movsi_internal (operands[0], GEN_INT (0))); - emit_insn (gen_subsi3 (operands[0], operands[0], operands[1])); - } - DONE; - }" -) - -;;}}} - ;;}}} ;;{{{ Shifts @@ -884,7 +851,7 @@ ;;}}} ;;{{{ Logical Operations -;; Logical AND, 32 bit integers +;; Logical AND, 32-bit integers (define_insn "andsi3" [(set (match_operand:SI 0 "register_operand" "=r") (and:SI (match_operand:SI 1 "register_operand" "%r") @@ -894,7 +861,7 @@ "and %1, %0" ) -;; Inclusive OR, 32 bit integers +;; Inclusive OR, 32-bit integers (define_insn "iorsi3" [(set (match_operand:SI 0 "register_operand" "=r") (ior:SI (match_operand:SI 1 "register_operand" "%r") @@ -904,7 +871,7 @@ "or %1, %0" ) -;; Exclusive OR, 32 bit integers +;; Exclusive OR, 32-bit integers (define_insn "xorsi3" [(set (match_operand:SI 0 "register_operand" "=r") (xor:SI (match_operand:SI 1 "register_operand" "%r") @@ -914,32 +881,32 @@ "eor %1, %0" ) -;; One's complement, 32 bit integers +;; One's complement, 32-bit integers (define_expand "one_cmplsi2" [(set (match_operand:SI 0 "register_operand" "") (not:SI (match_operand:SI 1 "register_operand" "")))] "" "{ - if (REGNO (operands[0]) == REGNO (operands[1])) + if (rtx_equal_p (operands[0], operands[1])) { if (reload_in_progress || reload_completed) { rtx reg = gen_rtx_REG (SImode, 0/*COMPILER_SCRATCH_REGISTER*/); - emit_insn (gen_movsi (reg, GEN_INT (-1))); + emit_insn (gen_movsi (reg, constm1_rtx)); emit_insn (gen_xorsi3 (operands[0], operands[0], reg)); } else { rtx reg = gen_reg_rtx (SImode); - emit_insn (gen_movsi (reg, GEN_INT (-1))); + emit_insn (gen_movsi (reg, constm1_rtx)); emit_insn (gen_xorsi3 (operands[0], operands[0], reg)); } } else { - emit_insn (gen_movsi_internal (operands[0], GEN_INT (-1))); + emit_insn (gen_movsi_internal (operands[0], constm1_rtx)); emit_insn (gen_xorsi3 (operands[0], operands[1], operands[0])); } DONE; @@ -1152,13 +1119,13 @@ ;; far away the destination is. ;; The calculation for the instruction length is derived as follows: -;; The branch instruction has a 9 bit signed displacement so we have +;; The branch instruction has a 9-bit signed displacement so we have ;; this inequality for the displacement: ;; ;; -256 <= pc < 256 ;; or ;; -256 + 256 <= pc + 256 < 256 + 256 -;; ie +;; i.e. ;; 0 <= pc + 256 < 512 ;; ;; if we consider the displacement as an unsigned value, then negative @@ -1171,7 +1138,7 @@ ;; from pc + 2, we increase the offset to 258. ;; ;; Note - we do not have to worry about whether the branch is delayed or -;; not, as branch shortening happens after delay slot reorganisation. +;; not, as branch shortening happens after delay slot reorganization. (define_insn "*branch_true" [(set (pc) @@ -1404,7 +1371,25 @@ "leave" ) -(define_insn "enter_func" +(define_expand "enter_func" + [(parallel + [(set:SI (mem:SI (minus:SI (match_dup 1) + (const_int 4))) + (match_dup 2)) + (set:SI (match_dup 2) + (minus:SI (match_dup 1) + (const_int 4))) + (set:SI (match_dup 1) + (minus:SI (match_dup 1) + (match_operand:SI 0 "immediate_operand")))] + )] + "" +{ + operands[1] = stack_pointer_rtx; + operands[2] = hard_frame_pointer_rtx; +}) + +(define_insn "*enter_func" [(set:SI (mem:SI (minus:SI (reg:SI 15) (const_int 4))) (reg:SI 14)) @@ -1437,6 +1422,7 @@ "" [(set_attr "length" "0")] ) +;;}}} ;; Local Variables: ;; mode: md