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diff --git a/gcc/config/ia64/lib1funcs.asm b/gcc/config/ia64/lib1funcs.asm
index 75e79b0a..b7eaa6ec 100644
--- a/gcc/config/ia64/lib1funcs.asm
+++ b/gcc/config/ia64/lib1funcs.asm
@@ -1,16 +1,46 @@
-#ifdef L__divtf3
+/* Copyright (C) 2000, 2001, 2003, 2005, 2009 Free Software Foundation, Inc.
+   Contributed by James E. Wilson <wilson@cygnus.com>.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   GCC is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+#ifdef L__divxf3
 // Compute a 80-bit IEEE double-extended quotient.
 //
 // From the Intel IA-64 Optimization Guide, choose the minimum latency
 // alternative.
 //
 // farg0 holds the dividend.  farg1 holds the divisor.
+//
+// __divtf3 is an alternate symbol name for backward compatibility.
 
 	.text
 	.align 16
+	.global __divxf3
+	.proc __divxf3
+__divxf3:
+#ifdef SHARED
 	.global __divtf3
-	.proc __divtf3
 __divtf3:
+#endif
 	cmp.eq p7, p0 = r0, r0
 	frcpa.s0 f10, p6 = farg0, farg1
 	;;
@@ -37,7 +67,7 @@ __divtf3:
 (p6)	fma.s0 fret0 = f12, f10, f11
 (p7)	mov fret0 = f10
 	br.ret.sptk rp
-	.endp __divtf3
+	.endp __divxf3
 #endif
 
 #ifdef L__divdf3
@@ -135,10 +165,13 @@ __divdi3:
 	// Transfer inputs to FP registers.
 	setf.sig f8 = in0
 	setf.sig f9 = in1
+	// Check divide by zero.
+	cmp.ne.unc p0,p7=0,in1
 	;;
 	// Convert the inputs to FP, so that they won't be treated as unsigned.
 	fcvt.xf f8 = f8
 	fcvt.xf f9 = f9
+(p7)	break 1
 	;;
 	// Compute the reciprocal approximation.
 	frcpa.s1 f10, p6 = f8, f9
@@ -185,10 +218,13 @@ __moddi3:
 	// Transfer inputs to FP registers.
 	setf.sig f14 = in0
 	setf.sig f9 = in1
+	// Check divide by zero.
+	cmp.ne.unc p0,p7=0,in1
 	;;
 	// Convert the inputs to FP, so that they won't be treated as unsigned.
 	fcvt.xf f8 = f14
 	fcvt.xf f9 = f9
+(p7)	break 1
 	;;
 	// Compute the reciprocal approximation.
 	frcpa.s1 f10, p6 = f8, f9
@@ -239,10 +275,13 @@ __udivdi3:
 	// Transfer inputs to FP registers.
 	setf.sig f8 = in0
 	setf.sig f9 = in1
+	// Check divide by zero.
+	cmp.ne.unc p0,p7=0,in1
 	;;
 	// Convert the inputs to FP, to avoid FP software-assist faults.
 	fcvt.xuf.s1 f8 = f8
 	fcvt.xuf.s1 f9 = f9
+(p7)	break 1
 	;;
 	// Compute the reciprocal approximation.
 	frcpa.s1 f10, p6 = f8, f9
@@ -289,10 +328,13 @@ __umoddi3:
 	// Transfer inputs to FP registers.
 	setf.sig f14 = in0
 	setf.sig f9 = in1
+	// Check divide by zero.
+	cmp.ne.unc p0,p7=0,in1
 	;;
 	// Convert the inputs to FP, to avoid FP software assist faults.
 	fcvt.xuf.s1 f8 = f14
 	fcvt.xuf.s1 f9 = f9
+(p7)	break 1;
 	;;
 	// Compute the reciprocal approximation.
 	frcpa.s1 f10, p6 = f8, f9
@@ -341,11 +383,14 @@ __umoddi3:
 	.proc __divsi3
 __divsi3:
 	.regstk 2,0,0,0
+	// Check divide by zero.
+	cmp.ne.unc p0,p7=0,in1
 	sxt4 in0 = in0
 	sxt4 in1 = in1
 	;;
 	setf.sig f8 = in0
 	setf.sig f9 = in1
+(p7)	break 1
 	;;
 	mov r2 = 0x0ffdd
 	fcvt.xf f8 = f8
@@ -390,6 +435,8 @@ __modsi3:
 	;;
 	setf.sig f13 = r32
 	setf.sig f9 = r33
+	// Check divide by zero.
+	cmp.ne.unc p0,p7=0,in1
 	;;
 	sub in1 = r0, in1
 	fcvt.xf f8 = f13
@@ -397,6 +444,7 @@ __modsi3:
 	;;
 	setf.exp f11 = r2
 	frcpa.s1 f10, p6 = f8, f9
+(p7)	break 1
 	;;
 (p6)	fmpy.s1 f12 = f8, f10
 (p6)	fnma.s1 f10 = f9, f10, f1
@@ -437,9 +485,12 @@ __udivsi3:
 	;;
 	setf.sig f8 = in0
 	setf.sig f9 = in1
+	// Check divide by zero.
+	cmp.ne.unc p0,p7=0,in1
 	;;
 	fcvt.xf f8 = f8
 	fcvt.xf f9 = f9
+(p7)	break 1
 	;;
 	setf.exp f11 = r2
 	frcpa.s1 f10, p6 = f8, f9
@@ -480,6 +531,8 @@ __umodsi3:
 	;;
 	setf.sig f13 = in0
 	setf.sig f9 = in1
+	// Check divide by zero.
+	cmp.ne.unc p0,p7=0,in1
 	;;
 	sub in1 = r0, in1
 	fcvt.xf f8 = f13
@@ -487,6 +540,7 @@ __umodsi3:
 	;;
 	setf.exp f11 = r2
 	frcpa.s1 f10, p6 = f8, f9
+(p7)	break 1;
 	;;
 (p6)	fmpy.s1 f12 = f8, f10
 (p6)	fnma.s1 f10 = f9, f10, f1
@@ -701,3 +755,41 @@ __ia64_trampoline:
 	}
 	.endp __ia64_trampoline
 #endif
+
+#ifdef SHARED
+// Thunks for backward compatibility.
+#ifdef L_fixtfdi
+	.text
+	.align 16
+	.global __fixtfti
+	.proc __fixtfti
+__fixtfti:
+	{ .bbb
+	  br.sptk.many __fixxfti
+	  ;;
+	}
+	.endp __fixtfti
+#endif
+#ifdef L_fixunstfdi
+	.align 16
+	.global __fixunstfti
+	.proc __fixunstfti
+__fixunstfti:
+	{ .bbb
+	  br.sptk.many __fixunsxfti
+	  ;;
+	}
+	.endp __fixunstfti
+#endif
+#ifdef L_floatditf
+	.align 16
+	.global __floattitf
+	.proc __floattitf
+__floattitf:
+	{ .bbb
+	  br.sptk.many __floattixf
+	  ;;
+	}
+	.endp __floattitf
+#endif
+#endif