X-Git-Url: https://oss.titaniummirror.com/gitweb?a=blobdiff_plain;f=gcc%2Fconfig%2Fs390%2Fs390.md;fp=gcc%2Fconfig%2Fs390%2Fs390.md;h=ae8a0eaffe15c1523f5fdef8f14e86e5a50136f5;hb=6fed43773c9b0ce596dca5686f37ac3fc0fa11c0;hp=274263812e2a80cf16e920076c6c0e15270c9bbf;hpb=27b11d56b743098deb193d510b337ba22dc52e5c;p=msp430-gcc.git
diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index 27426381..ae8a0eaf 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -1,801 +1,1139 @@
;;- Machine description for GNU compiler -- S/390 / zSeries version.
-;; Copyright (C) 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
+;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008,
+;; 2009 Free Software Foundation, Inc.
;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
-;; Ulrich Weigand (uweigand@de.ibm.com).
-;; This file is part of GNU CC.
+;; Ulrich Weigand (uweigand@de.ibm.com) and
+;; Andreas Krebbel (Andreas.Krebbel@de.ibm.com)
-;; GNU CC is free software; you can redistribute it and/or modify
-;; it under the terms of the GNU General Public License as published by
-;; the Free Software Foundation; either version 2, or (at your option)
-;; any later version.
+;; This file is part of GCC.
-;; GNU CC is distributed in the hope that it will be useful,
-;; but WITHOUT ANY WARRANTY; without even the implied warranty of
-;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-;; GNU General Public License for more details.
+;; GCC is free software; you can redistribute it and/or modify it under
+;; the terms of the GNU General Public License as published by the Free
+;; Software Foundation; either version 3, or (at your option) any later
+;; version.
+
+;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
+;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+;; for more details.
;; You should have received a copy of the GNU General Public License
-;; along with GNU CC; see the file COPYING. If not, write to
-;; the Free Software Foundation, 59 Temple Place - Suite 330,
-;; Boston, MA 02111-1307, USA.
+;; along with GCC; see the file COPYING3. If not see
+;; .
;;
-;; Special constraints for s/390 machine description:
-;;
-;; a -- Any address register from 1 to 15.
-;; d -- Any register from 0 to 15.
-;; I -- An 8-bit constant (0..255).
-;; J -- A 12-bit constant (0..4095).
-;; K -- A 16-bit constant (-32768..32767).
-;; Q -- A memory reference without index-register.
-;; S -- Valid operand for the LARL instruction.
+;; See constraints.md for a description of constraints specific to s390.
;;
+
;; Special formats used for outputting 390 instructions.
;;
-;; %b -- Print a constant byte integer. xy
-;; %h -- Print a signed 16-bit. wxyz
-;; %N -- Print next register (second word of a DImode reg) or next word.
-;; %M -- Print next register (second word of a TImode reg) or next word.
-;; %O -- Print the offset of a memory reference (PLUS (REG) (CONST_INT)).
-;; %R -- Print the register of a memory reference (PLUS (REG) (CONST_INT)).
+;; %C: print opcode suffix for branch condition.
+;; %D: print opcode suffix for inverse branch condition.
+;; %J: print tls_load/tls_gdcall/tls_ldcall suffix
+;; %G: print the size of the operand in bytes.
+;; %O: print only the displacement of a memory reference.
+;; %R: print only the base register of a memory reference.
+;; %S: print S-type memory reference (base+displacement).
+;; %N: print the second word of a DImode operand.
+;; %M: print the second word of a TImode operand.
+;; %Y: print shift count operand.
+;;
+;; %b: print integer X as if it's an unsigned byte.
+;; %c: print integer X as if it's an signed byte.
+;; %x: print integer X as if it's an unsigned halfword.
+;; %h: print integer X as if it's a signed halfword.
+;; %i: print the first nonzero HImode part of X.
+;; %j: print the first HImode part unequal to -1 of X.
+;; %k: print the first nonzero SImode part of X.
+;; %m: print the first SImode part unequal to -1 of X.
+;; %o: print integer X as if it's an unsigned 32bit word.
;;
;; We have a special constraint for pattern matching.
;;
;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
;;
+;;
+;; UNSPEC usage
+;;
-;; Define an insn type attribute. This is used in function unit delay
-;; computations.
-
-(define_attr "type" "none,integer,load,lr,la,lm,stm,cs,vs,store,imul,lmul,fmul,idiv,ldiv,fdiv,branch,jsr,other,o2,o3"
- (const_string "integer"))
-
-;; Insn are devide in two classes:
-;; mem: Insn accessing memory
-;; reg: Insn operands all in registers
-
-(define_attr "atype" "reg,mem"
- (const_string "reg"))
-
-;; Generic pipeline function unit.
-
-(define_function_unit "integer" 1 0
- (eq_attr "type" "none") 0 0)
-
-(define_function_unit "integer" 1 0
- (eq_attr "type" "integer") 1 1)
-
-(define_function_unit "integer" 1 0
- (eq_attr "type" "load") 1 1)
-
-(define_function_unit "integer" 1 0
- (eq_attr "type" "la") 1 1)
-
-(define_function_unit "integer" 1 0
- (eq_attr "type" "lr") 1 1)
-
-(define_function_unit "integer" 1 0
- (eq_attr "type" "store") 1 1)
+(define_constants
+ [; Miscellaneous
+ (UNSPEC_ROUND 1)
+ (UNSPEC_CCU_TO_INT 2)
+ (UNSPEC_CCZ_TO_INT 3)
+ (UNSPEC_ICM 10)
+ (UNSPEC_TIE 11)
+
+ ; GOT/PLT and lt-relative accesses
+ (UNSPEC_LTREL_OFFSET 100)
+ (UNSPEC_LTREL_BASE 101)
+ (UNSPEC_POOL_OFFSET 102)
+ (UNSPEC_GOTENT 110)
+ (UNSPEC_GOT 111)
+ (UNSPEC_GOTOFF 112)
+ (UNSPEC_PLT 113)
+ (UNSPEC_PLTOFF 114)
+
+ ; Literal pool
+ (UNSPEC_RELOAD_BASE 210)
+ (UNSPEC_MAIN_BASE 211)
+ (UNSPEC_LTREF 212)
+ (UNSPEC_INSN 213)
+ (UNSPEC_EXECUTE 214)
+
+ ; Atomic Support
+ (UNSPEC_MB 400)
+
+ ; TLS relocation specifiers
+ (UNSPEC_TLSGD 500)
+ (UNSPEC_TLSLDM 501)
+ (UNSPEC_NTPOFF 502)
+ (UNSPEC_DTPOFF 503)
+ (UNSPEC_GOTNTPOFF 504)
+ (UNSPEC_INDNTPOFF 505)
+
+ ; TLS support
+ (UNSPEC_TLSLDM_NTPOFF 511)
+ (UNSPEC_TLS_LOAD 512)
+
+ ; String Functions
+ (UNSPEC_SRST 600)
+ (UNSPEC_MVST 601)
+
+ ; Stack Smashing Protector
+ (UNSPEC_SP_SET 700)
+ (UNSPEC_SP_TEST 701)
+
+ ; Copy sign instructions
+ (UNSPEC_COPYSIGN 800)
+
+ ; Test Data Class (TDC)
+ (UNSPEC_TDC_INSN 900)
+ ])
-(define_function_unit "integer" 1 0
- (eq_attr "type" "lm") 2 2)
+;;
+;; UNSPEC_VOLATILE usage
+;;
-(define_function_unit "integer" 1 0
- (eq_attr "type" "stm") 2 2)
+(define_constants
+ [; Blockage
+ (UNSPECV_BLOCKAGE 0)
-(define_function_unit "integer" 1 0
- (eq_attr "type" "cs") 5 5)
+ ; TPF Support
+ (UNSPECV_TPF_PROLOGUE 20)
+ (UNSPECV_TPF_EPILOGUE 21)
-(define_function_unit "integer" 1 0
- (eq_attr "type" "vs") 30 30)
+ ; Literal pool
+ (UNSPECV_POOL 200)
+ (UNSPECV_POOL_SECTION 201)
+ (UNSPECV_POOL_ALIGN 202)
+ (UNSPECV_POOL_ENTRY 203)
+ (UNSPECV_MAIN_POOL 300)
-(define_function_unit "integer" 1 0
- (eq_attr "type" "jsr") 5 5)
+ ; TLS support
+ (UNSPECV_SET_TP 500)
-(define_function_unit "integer" 1 0
- (eq_attr "type" "imul") 7 7)
+ ; Atomic Support
+ (UNSPECV_CAS 700)
+ ])
-(define_function_unit "integer" 1 0
- (eq_attr "type" "fmul") 6 6)
+;;
+;; Registers
+;;
-(define_function_unit "integer" 1 0
- (eq_attr "type" "idiv") 33 33)
+; Registers with special meaning
+
+(define_constants
+ [
+ ; Sibling call register.
+ (SIBCALL_REGNUM 1)
+ ; Literal pool base register.
+ (BASE_REGNUM 13)
+ ; Return address register.
+ (RETURN_REGNUM 14)
+ ; Condition code register.
+ (CC_REGNUM 33)
+ ; Thread local storage pointer register.
+ (TP_REGNUM 36)
+ ])
+
+; Hardware register names
+
+(define_constants
+ [
+ ; General purpose registers
+ (GPR0_REGNUM 0)
+ ; Floating point registers.
+ (FPR0_REGNUM 16)
+ (FPR2_REGNUM 18)
+ ])
-(define_function_unit "integer" 1 0
- (eq_attr "type" "fdiv") 33 33)
+;;
+;; PFPO GPR0 argument format
+;;
-(define_function_unit "integer" 1 0
- (eq_attr "type" "o2") 2 2)
+(define_constants
+ [
+ ; PFPO operation type
+ (PFPO_CONVERT 0x1000000)
+ ; PFPO operand types
+ (PFPO_OP_TYPE_SF 0x5)
+ (PFPO_OP_TYPE_DF 0x6)
+ (PFPO_OP_TYPE_TF 0x7)
+ (PFPO_OP_TYPE_SD 0x8)
+ (PFPO_OP_TYPE_DD 0x9)
+ (PFPO_OP_TYPE_TD 0xa)
+ ; Bitposition of operand types
+ (PFPO_OP0_TYPE_SHIFT 16)
+ (PFPO_OP1_TYPE_SHIFT 8)
+ ])
+
+
+;; Instruction operand type as used in the Principles of Operation.
+;; Used to determine defaults for length and other attribute values.
-(define_function_unit "integer" 1 0
- (eq_attr "type" "o3") 3 3)
+(define_attr "op_type"
+ "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,RRR,SIL,RRS,RIS"
+ (const_string "NN"))
+
+;; Instruction type attribute used for scheduling.
+
+(define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
+ cs,vs,store,sem,idiv,
+ imulhi,imulsi,imuldi,
+ branch,jsr,fsimptf,fsimpdf,fsimpsf,fhex,
+ floadtf,floaddf,floadsf,fstoredf,fstoresf,
+ fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf,
+ ftoi,fsqrttf,fsqrtdf,fsqrtsf,
+ ftrunctf,ftruncdf, ftruncsd, ftruncdd,
+ itoftf, itofdf, itofsf, itofdd, itoftd,
+ fdivdd, fdivtd, floaddd, floadsd, fmuldd, fmultd,
+ fsimpdd, fsimpsd, fsimptd, fstoredd, fstoresd,
+ ftoidfp, other"
+ (cond [(eq_attr "op_type" "NN") (const_string "other")
+ (eq_attr "op_type" "SS") (const_string "cs")]
+ (const_string "integer")))
+
+;; Another attribute used for scheduling purposes:
+;; agen: Instruction uses the address generation unit
+;; reg: Instruction does not use the agen unit
+
+(define_attr "atype" "agen,reg"
+ (if_then_else (eq_attr "op_type" "E,RR,RI,RRE")
+ (const_string "reg")
+ (const_string "agen")))
+
+;; Properties concerning Z10 execution grouping and value forwarding.
+;; z10_super: instruction is superscalar.
+;; z10_super_c: instruction is superscalar and meets the condition of z10_c.
+;; z10_fwd: The instruction reads the value of an operand and stores it into a
+;; target register. It can forward this value to a second instruction that reads
+;; the same register if that second instruction is issued in the same group.
+;; z10_rec: The instruction is in the T pipeline and reads a register. If the
+;; instruction in the S pipe writes to the register, then the T instruction
+;; can immediately read the new value.
+;; z10_fr: union of Z10_fwd and z10_rec.
+;; z10_c: second operand of instruction is a register and read with complemented bits.
+;;
+;; An additional suffix A1, A3, or E1 indicates the respective AGI bypass.
-(define_function_unit "integer" 1 0
- (eq_attr "type" "other") 5 5)
-;; Operand type. Used to default length attribute values
+(define_attr "z10prop" "none,
+ z10_super, z10_super_E1, z10_super_A1, z10_super_c, z10_super_c_E1,
+ z10_fwd, z10_fwd_A1, z10_fwd_A3, z10_fwd_E1,
+ z10_rec,
+ z10_fr, z10_fr_A3, z10_fr_E1,
+ z10_c"
+ (const_string "none"))
-(define_attr "op_type"
- "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE"
- (const_string "RX"))
;; Length in bytes.
(define_attr "length" ""
-(cond [ (eq_attr "op_type" "E") (const_int 2)
- (eq_attr "op_type" "RR") (const_int 2)
- (eq_attr "op_type" "RX") (const_int 4)
- (eq_attr "op_type" "RI") (const_int 4)
- (eq_attr "op_type" "RRE") (const_int 4)
- (eq_attr "op_type" "RS") (const_int 4)
- (eq_attr "op_type" "RSI") (const_int 4)
- (eq_attr "op_type" "RX") (const_int 4)
- (eq_attr "op_type" "S") (const_int 4)
- (eq_attr "op_type" "SI") (const_int 4)
- (eq_attr "op_type" "SS") (const_int 6)
- (eq_attr "op_type" "SSE") (const_int 6)
- (eq_attr "op_type" "RXE") (const_int 6)
- (eq_attr "op_type" "RSE") (const_int 6)
- (eq_attr "op_type" "RIL") (const_int 6)]
- (const_int 4)))
-
-;; Define attributes for `asm' insns.
-
-(define_asm_attributes [(set_attr "type" "other")
- (set_attr "op_type" "NN")])
-
-;;
-;; Condition Codes
-;;
-;
-; CCL: Zero Nonzero Zero Nonzero (AL, ALR, SL, SLR, N, NC, NI, NR, O, OC, OI, OR, X, XC, XI, XR)
-; CCA: Zero Zero Overflow (A, AR, AH, AHI, S, SR, SH, SHI, LTR, LCR, LNR, LPR, SLA, SLDA, SLA, SRDA)
-; CCU: Equal ULess UGreater -- (CL, CLR, CLI, CLM)
-; CCS: Equal SLess SGreater -- (C, CR, CH, CHI, ICM)
-; CCT: Zero Mixed Mixed Ones (TM, TMH, TML)
-
-; CCZ -> CCL / CCZ1
-; CCZ1 -> CCA/CCU/CCS/CCT
-; CCS -> CCA
-
-; String: CLC, CLCL, CLCLE, CLST, CUSE, MVCL, MVCLE, MVPG, MVST, SRST
-; Clobber: CKSM, CFC, CS, CDS, CUUTF, CUTFU, PLO, SPM, STCK, STCKE, TS, TRT, TRE, UPT
+ (cond [(eq_attr "op_type" "E,RR") (const_int 2)
+ (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF,RRR") (const_int 4)]
+ (const_int 6)))
+
+
+;; Processor type. This attribute must exactly match the processor_type
+;; enumeration in s390.h. The current machine description does not
+;; distinguish between g5 and g6, but there are differences between the two
+;; CPUs could in theory be modeled.
+(define_attr "cpu" "g5,g6,z900,z990,z9_109,z10"
+ (const (symbol_ref "s390_tune")))
+
+(define_attr "cpu_facility" "standard,ieee,zarch,longdisp,extimm,dfp,z10"
+ (const_string "standard"))
+
+(define_attr "enabled" ""
+ (cond [(eq_attr "cpu_facility" "standard")
+ (const_int 1)
+
+ (and (eq_attr "cpu_facility" "ieee")
+ (ne (symbol_ref "TARGET_CPU_IEEE_FLOAT") (const_int 0)))
+ (const_int 1)
+
+ (and (eq_attr "cpu_facility" "zarch")
+ (ne (symbol_ref "TARGET_ZARCH") (const_int 0)))
+ (const_int 1)
+
+ (and (eq_attr "cpu_facility" "longdisp")
+ (ne (symbol_ref "TARGET_LONG_DISPLACEMENT") (const_int 0)))
+ (const_int 1)
+
+ (and (eq_attr "cpu_facility" "extimm")
+ (ne (symbol_ref "TARGET_EXTIMM") (const_int 0)))
+ (const_int 1)
+
+ (and (eq_attr "cpu_facility" "dfp")
+ (ne (symbol_ref "TARGET_DFP") (const_int 0)))
+ (const_int 1)
+
+ (and (eq_attr "cpu_facility" "z10")
+ (ne (symbol_ref "TARGET_Z10") (const_int 0)))
+ (const_int 1)]
+ (const_int 0)))
+
+;; Pipeline description for z900. For lack of anything better,
+;; this description is also used for the g5 and g6.
+(include "2064.md")
+
+;; Pipeline description for z990, z9-109 and z9-ec.
+(include "2084.md")
+
+;; Pipeline description for z10
+(include "2097.md")
+
+;; Predicates
+(include "predicates.md")
+
+;; Constraint definitions
+(include "constraints.md")
+
+;; Other includes
+(include "tpf.md")
+
+;; Iterators
+
+;; These mode iterators allow floating point patterns to be generated from the
+;; same template.
+(define_mode_iterator FP_ALL [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")
+ (SD "TARGET_HARD_DFP")])
+(define_mode_iterator FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")])
+(define_mode_iterator FPALL [TF DF SF TD DD SD])
+(define_mode_iterator BFP [TF DF SF])
+(define_mode_iterator DFP [TD DD])
+(define_mode_iterator DFP_ALL [TD DD SD])
+(define_mode_iterator DSF [DF SF])
+(define_mode_iterator SD_SF [SF SD])
+(define_mode_iterator DD_DF [DF DD])
+(define_mode_iterator TD_TF [TF TD])
+
+;; This mode iterator allows 31-bit and 64-bit TDSI patterns to be generated
+;; from the same template.
+(define_mode_iterator TDSI [(TI "TARGET_64BIT") DI SI])
+
+;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated
+;; from the same template.
+(define_mode_iterator GPR [(DI "TARGET_64BIT") SI])
+(define_mode_iterator DSI [DI SI])
+
+;; These mode iterators allow :P to be used for patterns that operate on
+;; pointer-sized quantities. Exactly one of the two alternatives will match.
+(define_mode_iterator DP [(TI "TARGET_64BIT") (DI "!TARGET_64BIT")])
+(define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")])
+
+;; This mode iterator allows the QI and HI patterns to be defined from
+;; the same template.
+(define_mode_iterator HQI [HI QI])
+
+;; This mode iterator allows the integer patterns to be defined from the
+;; same template.
+(define_mode_iterator INT [(DI "TARGET_64BIT") SI HI QI])
+(define_mode_iterator INTALL [TI DI SI HI QI])
+
+;; This iterator allows to unify all 'bCOND' expander patterns.
+(define_code_iterator COMPARE [eq ne gt gtu lt ltu ge geu le leu unordered
+ ordered uneq unlt ungt unle unge ltgt])
+
+;; This iterator allows to unify all 'sCOND' patterns.
+(define_code_iterator SCOND [ltu gtu leu geu])
+
+;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from
+;; the same template.
+(define_code_iterator SHIFT [ashift lshiftrt])
+
+;; This iterator and attribute allow to combine most atomic operations.
+(define_code_iterator ATOMIC [and ior xor plus minus mult])
+(define_code_attr atomic [(and "and") (ior "ior") (xor "xor")
+ (plus "add") (minus "sub") (mult "nand")])
+
+;; In FP templates, a string like "ltbr" will expand to "ltxbr" in
+;; TF/TDmode, "ltdbr" in DF/DDmode, and "ltebr" in SF/SDmode.
+(define_mode_attr xde [(TF "x") (DF "d") (SF "e") (TD "x") (DD "d") (SD "e")])
+
+;; In FP templates, a in "mr" will expand to "mxr" in
+;; TF/TDmode, "mdr" in DF/DDmode, "meer" in SFmode and "mer in
+;; SDmode.
+(define_mode_attr xdee [(TF "x") (DF "d") (SF "ee") (TD "x") (DD "d") (SD "e")])
+
+;; In FP templates, "" will expand to "RRE" in TFmode and "RR" otherwise.
+;; Likewise for "".
+(define_mode_attr RRe [(TF "RRE") (DF "RR") (SF "RR")])
+(define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")])
+
+;; The decimal floating point variants of add, sub, div and mul support 3
+;; fp register operands. The following attributes allow to merge the bfp and
+;; dfp variants in a single insn definition.
+
+;; This attribute is used to set op_type accordingly.
+(define_mode_attr RRer [(TF "RRE") (DF "RRE") (SF "RRE") (TD "RRR")
+ (DD "RRR") (SD "RRR")])
+
+;; This attribute is used in the operand constraint list in order to have the
+;; first and the second operand match for bfp modes.
+(define_mode_attr f0 [(TF "0") (DF "0") (SF "0") (TD "f") (DD "f") (DD "f")])
+
+;; This attribute is used in the operand list of the instruction to have an
+;; additional operand for the dfp instructions.
+(define_mode_attr op1 [(TF "") (DF "") (SF "")
+ (TD "%1,") (DD "%1,") (SD "%1,")])
+
+
+;; This attribute is used in the operand constraint list
+;; for instructions dealing with the sign bit of 32 or 64bit fp values.
+;; TFmode values are represented by a fp register pair. Since the
+;; sign bit instructions only handle single source and target fp registers
+;; these instructions can only be used for TFmode values if the source and
+;; target operand uses the same fp register.
+(define_mode_attr fT0 [(TF "0") (DF "f") (SF "f")])
+
+;; In FP templates, "" will expand to "f" in TFmode and "R" otherwise.
+;; This is used to disable the memory alternative in TFmode patterns.
+(define_mode_attr Rf [(TF "f") (DF "R") (SF "R") (TD "f") (DD "f") (SD "f")])
+
+;; This attribute adds b for bfp instructions and t for dfp instructions and is used
+;; within instruction mnemonics.
+(define_mode_attr bt [(TF "b") (DF "b") (SF "b") (TD "t") (DD "t") (SD "t")])
+
+;; This attribute is used within instruction mnemonics. It evaluates to d for dfp
+;; modes and to an empty string for bfp modes.
+(define_mode_attr _d [(TF "") (DF "") (SF "") (TD "d") (DD "d") (SD "d")])
+
+;; In GPR and P templates, a constraint like "" will expand to "d" in DImode
+;; and "0" in SImode. This allows to combine instructions of which the 31bit
+;; version only operates on one register.
+(define_mode_attr d0 [(DI "d") (SI "0")])
+
+;; In combination with d0 this allows to combine instructions of which the 31bit
+;; version only operates on one register. The DImode version needs an additional
+;; register for the assembler output.
+(define_mode_attr 1 [(DI "%1,") (SI "")])
+
+;; In SHIFT templates, a string like "sdl" will expand to "sldl" in
+;; 'ashift' and "srdl" in 'lshiftrt'.
+(define_code_attr lr [(ashift "l") (lshiftrt "r")])
+
+;; In SHIFT templates, this attribute holds the correct standard name for the
+;; pattern itself and the corresponding function calls.
+(define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")])
+
+;; This attribute handles differences in the instruction 'type' and will result
+;; in "RRE" for DImode and "RR" for SImode.
+(define_mode_attr E [(DI "E") (SI "")])
+
+;; This attribute handles differences in the instruction 'type' and makes RX
+;; to result in "RXY" for DImode and "RX" for SImode.
+(define_mode_attr Y [(DI "Y") (SI "")])
+
+;; This attribute handles differences in the instruction 'type' and will result
+;; in "RSE" for TImode and "RS" for DImode.
+(define_mode_attr TE [(TI "E") (DI "")])
+
+;; In GPR templates, a string like "lcr" will expand to "lcgr" in DImode
+;; and "lcr" in SImode.
+(define_mode_attr g [(DI "g") (SI "")])
+
+;; In GPR templates, a string like "sl" will expand to "slg" in DImode
+;; and "sly" in SImode. This is useful because on 64bit the ..g instructions
+;; were enhanced with long displacements whereas 31bit instructions got a ..y
+;; variant for long displacements.
+(define_mode_attr y [(DI "g") (SI "y")])
+
+;; In DP templates, a string like "cds" will expand to "cdsg" in TImode
+;; and "cds" in DImode.
+(define_mode_attr tg [(TI "g") (DI "")])
+
+;; In GPR templates, a string like "cdbr" will expand to "cgdbr" in DImode
+;; and "cfdbr" in SImode.
+(define_mode_attr gf [(DI "g") (SI "f")])
+
+;; ICM mask required to load MODE value into the lowest subreg
+;; of a SImode register.
+(define_mode_attr icm_lo [(HI "3") (QI "1")])
+
+;; In HQI templates, a string like "llg" will expand to "llgh" in
+;; HImode and "llgc" in QImode.
+(define_mode_attr hc [(HI "h") (QI "c")])
+
+;; In P templates, the mode will expand to "TI" in DImode and "DI"
+;; in SImode.
+(define_mode_attr DBL [(DI "TI") (SI "DI")])
+
+;; This attribute expands to DF for TFmode and to DD for TDmode . It is
+;; used for Txmode splitters splitting a Txmode copy into 2 Dxmode copies.
+(define_mode_attr HALF_TMODE [(TF "DF") (TD "DD")])
+
+;; Maximum unsigned integer that fits in MODE.
+(define_mode_attr max_uint [(HI "65535") (QI "255")])
;;
;;- Compare instructions.
;;
-(define_expand "cmpdi"
- [(set (reg:CC 33)
- (compare:CC (match_operand:DI 0 "register_operand" "")
- (match_operand:DI 1 "general_operand" "")))]
- "TARGET_64BIT"
- "
-{
- s390_compare_op0 = operands[0];
- s390_compare_op1 = operands[1];
- DONE;
-}")
-
-(define_expand "cmpsi"
- [(set (reg:CC 33)
- (compare:CC (match_operand:SI 0 "register_operand" "")
- (match_operand:SI 1 "general_operand" "")))]
+(define_expand "cmp"
+ [(set (reg:CC CC_REGNUM)
+ (compare:CC (match_operand:GPR 0 "register_operand" "")
+ (match_operand:GPR 1 "general_operand" "")))]
""
- "
-{
- s390_compare_op0 = operands[0];
- s390_compare_op1 = operands[1];
- DONE;
-}")
-
-;(define_expand "cmphi"
-; [(set (reg:CC 33)
-; (compare:CC (match_operand:HI 0 "register_operand" "")
-; (match_operand:HI 1 "general_operand" "")))]
-; ""
-; "
-;{
-; s390_compare_op0 = operands[0];
-; s390_compare_op1 = operands[1];
-; DONE;
-;}")
-
-;(define_expand "cmpqi"
-; [(set (reg:CC 33)
-; (compare:CC (match_operand:QI 0 "register_operand" "")
-; (match_operand:QI 1 "general_operand" "")))]
-; ""
-; "
-;{
-; s390_compare_op0 = operands[0];
-; s390_compare_op1 = operands[1];
-; DONE;
-;}")
-
-(define_expand "cmpdf"
- [(set (reg:CC 33)
- (compare:CC (match_operand:DF 0 "register_operand" "")
- (match_operand:DF 1 "general_operand" "")))]
- "TARGET_HARD_FLOAT"
- "
{
s390_compare_op0 = operands[0];
s390_compare_op1 = operands[1];
DONE;
-}")
+})
-(define_expand "cmpsf"
- [(set (reg:CC 33)
- (compare:CC (match_operand:SF 0 "register_operand" "")
- (match_operand:SF 1 "general_operand" "")))]
+(define_expand "cmp"
+ [(set (reg:CC CC_REGNUM)
+ (compare:CC (match_operand:FP 0 "register_operand" "")
+ (match_operand:FP 1 "general_operand" "")))]
"TARGET_HARD_FLOAT"
- "
{
s390_compare_op0 = operands[0];
s390_compare_op1 = operands[1];
DONE;
-}")
+})
-; DI instructions
-
-(define_insn "*cmpdi_tm2"
- [(set (reg 33)
- (compare (zero_extract:DI (match_operand:DI 0 "register_operand" "d")
- (match_operand:DI 1 "const_int_operand" "n")
- (match_operand:DI 2 "const_int_operand" "n"))
- (const_int 0)))]
- "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT
- && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
- && INTVAL (operands[1]) + INTVAL (operands[2]) <= 64
- && (INTVAL (operands[1]) + INTVAL (operands[2]) - 1) >> 4
- == INTVAL (operands[2]) >> 4"
- "*
-{
- int part = INTVAL (operands[2]) >> 4;
- int block = (1 << INTVAL (operands[1])) - 1;
- int shift = 16 - INTVAL (operands[1]) - (INTVAL (operands[2]) & 15);
-
- operands[2] = GEN_INT (block << shift);
+; Test-under-Mask instructions
- switch (part)
- {
- case 0: return \"tmhh\\t%0,%x2\";
- case 1: return \"tmhl\\t%0,%x2\";
- case 2: return \"tmlh\\t%0,%x2\";
- case 3: return \"tmll\\t%0,%x2\";
- default: abort ();
- }
-}"
- [(set_attr "op_type" "RI")])
+(define_insn "*tmqi_mem"
+ [(set (reg CC_REGNUM)
+ (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S")
+ (match_operand:QI 1 "immediate_operand" "n,n"))
+ (match_operand:QI 2 "immediate_operand" "n,n")))]
+ "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))"
+ "@
+ tm\t%S0,%b1
+ tmy\t%S0,%b1"
+ [(set_attr "op_type" "SI,SIY")
+ (set_attr "z10prop" "z10_super,z10_super")])
+
+(define_insn "*tmdi_reg"
+ [(set (reg CC_REGNUM)
+ (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d")
+ (match_operand:DI 1 "immediate_operand"
+ "N0HD0,N1HD0,N2HD0,N3HD0"))
+ (match_operand:DI 2 "immediate_operand" "n,n,n,n")))]
+ "TARGET_64BIT
+ && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
+ && s390_single_part (operands[1], DImode, HImode, 0) >= 0"
+ "@
+ tmhh\t%0,%i1
+ tmhl\t%0,%i1
+ tmlh\t%0,%i1
+ tmll\t%0,%i1"
+ [(set_attr "op_type" "RI")
+ (set_attr "z10prop" "z10_super,z10_super,z10_super,z10_super")])
+
+(define_insn "*tmsi_reg"
+ [(set (reg CC_REGNUM)
+ (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d")
+ (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0"))
+ (match_operand:SI 2 "immediate_operand" "n,n")))]
+ "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
+ && s390_single_part (operands[1], SImode, HImode, 0) >= 0"
+ "@
+ tmh\t%0,%i1
+ tml\t%0,%i1"
+ [(set_attr "op_type" "RI")
+ (set_attr "z10prop" "z10_super,z10_super")])
+
+(define_insn "*tm_full"
+ [(set (reg CC_REGNUM)
+ (compare (match_operand:HQI 0 "register_operand" "d")
+ (match_operand:HQI 1 "immediate_operand" "n")))]
+ "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))"
+ "tml\t%0,"
+ [(set_attr "op_type" "RI")
+ (set_attr "z10prop" "z10_super")])
-(define_insn "*cmpdi_tm_reg"
- [(set (reg 33)
- (compare (and:DI (match_operand:DI 0 "register_operand" "%d")
- (match_operand:DI 1 "immediate_operand" "n"))
- (const_int 0)))]
- "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT
- && s390_single_hi (operands[1], DImode, 0) >= 0"
- "*
-{
- int part = s390_single_hi (operands[1], DImode, 0);
- operands[1] = GEN_INT (s390_extract_hi (operands[1], DImode, part));
- switch (part)
- {
- case 0: return \"tmhh\\t%0,%x1\";
- case 1: return \"tmhl\\t%0,%x1\";
- case 2: return \"tmlh\\t%0,%x1\";
- case 3: return \"tmll\\t%0,%x1\";
- default: abort ();
- }
-}"
- [(set_attr "op_type" "RI")])
+;
+; Load-and-Test instructions
+;
-(define_insn "*cmpdi_tm_mem"
- [(set (reg 33)
- (compare (and:DI (match_operand:DI 0 "s_operand" "%Qo")
- (match_operand:DI 1 "immediate_operand" "n"))
- (const_int 0)))]
- "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT
- && s390_single_qi (operands[1], DImode, 0) >= 0"
- "*
-{
- int part = s390_single_qi (operands[1], DImode, 0);
- operands[1] = GEN_INT (s390_extract_qi (operands[1], DImode, part));
+; tst(di|si) instruction pattern(s).
- operands[0] = gen_rtx_MEM (QImode,
- plus_constant (XEXP (operands[0], 0), part));
- return \"tm\\t%0,%b1\";
-}"
- [(set_attr "op_type" "SI")
- (set_attr "atype" "mem")])
+(define_insn "*tstdi_sign"
+ [(set (reg CC_REGNUM)
+ (compare
+ (ashiftrt:DI
+ (ashift:DI
+ (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,RT") 0)
+ (const_int 32)) (const_int 32))
+ (match_operand:DI 1 "const0_operand" "")))
+ (set (match_operand:DI 2 "register_operand" "=d,d")
+ (sign_extend:DI (match_dup 0)))]
+ "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
+ "ltgfr\t%2,%0
+ ltgf\t%2,%0"
+ [(set_attr "op_type" "RRE,RXY")
+ (set_attr "cpu_facility" "*,z10")
+ (set_attr "z10prop" "z10_super_E1,z10_super_E1") ])
+
+; ltr, lt, ltgr, ltg
+(define_insn "*tst_extimm"
+ [(set (reg CC_REGNUM)
+ (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT")
+ (match_operand:GPR 1 "const0_operand" "")))
+ (set (match_operand:GPR 2 "register_operand" "=d,d")
+ (match_dup 0))]
+ "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
+ "@
+ ltr\t%2,%0
+ lt\t%2,%0"
+ [(set_attr "op_type" "RR,RXY")
+ (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3") ])
+
+; ltr, lt, ltgr, ltg
+(define_insn "*tst_cconly_extimm"
+ [(set (reg CC_REGNUM)
+ (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT")
+ (match_operand:GPR 1 "const0_operand" "")))
+ (clobber (match_scratch:GPR 2 "=X,d"))]
+ "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
+ "@
+ ltr\t%0,%0
+ lt\t%2,%0"
+ [(set_attr "op_type" "RR,RXY")
+ (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3")])
-(define_insn "*ltgr"
- [(set (reg 33)
+(define_insn "*tstdi"
+ [(set (reg CC_REGNUM)
(compare (match_operand:DI 0 "register_operand" "d")
(match_operand:DI 1 "const0_operand" "")))
(set (match_operand:DI 2 "register_operand" "=d")
(match_dup 0))]
- "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
- "ltgr\\t%2,%0"
- [(set_attr "op_type" "RRE")])
+ "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT && !TARGET_EXTIMM"
+ "ltgr\t%2,%0"
+ [(set_attr "op_type" "RRE")
+ (set_attr "z10prop" "z10_fr_E1")])
-(define_insn "*cmpdi_ccs_0_64"
- [(set (reg 33)
+(define_insn "*tstsi"
+ [(set (reg CC_REGNUM)
+ (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
+ (match_operand:SI 1 "const0_operand" "")))
+ (set (match_operand:SI 2 "register_operand" "=d,d,d")
+ (match_dup 0))]
+ "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM"
+ "@
+ ltr\t%2,%0
+ icm\t%2,15,%S0
+ icmy\t%2,15,%S0"
+ [(set_attr "op_type" "RR,RS,RSY")
+ (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
+
+(define_insn "*tstsi_cconly"
+ [(set (reg CC_REGNUM)
+ (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
+ (match_operand:SI 1 "const0_operand" "")))
+ (clobber (match_scratch:SI 2 "=X,d,d"))]
+ "s390_match_ccmode(insn, CCSmode)"
+ "@
+ ltr\t%0,%0
+ icm\t%2,15,%S0
+ icmy\t%2,15,%S0"
+ [(set_attr "op_type" "RR,RS,RSY")
+ (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
+
+(define_insn "*tstdi_cconly_31"
+ [(set (reg CC_REGNUM)
(compare (match_operand:DI 0 "register_operand" "d")
(match_operand:DI 1 "const0_operand" "")))]
- "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
- "ltgr\\t%0,%0"
- [(set_attr "op_type" "RRE")])
+ "s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT"
+ "srda\t%0,0"
+ [(set_attr "op_type" "RS")
+ (set_attr "atype" "reg")])
-(define_insn "*cmpdi_ccs_0_31"
- [(set (reg 33)
- (compare (match_operand:DI 0 "register_operand" "d")
- (match_operand:DI 1 "const0_operand" "")))]
+; ltr, ltgr
+(define_insn "*tst_cconly2"
+ [(set (reg CC_REGNUM)
+ (compare (match_operand:GPR 0 "register_operand" "d")
+ (match_operand:GPR 1 "const0_operand" "")))]
"s390_match_ccmode(insn, CCSmode)"
- "srda\\t%0,0"
- [(set_attr "op_type" "RS")])
+ "ltr\t%0,%0"
+ [(set_attr "op_type" "RR")
+ (set_attr "z10prop" "z10_fr_E1")])
-(define_insn "*cmpdi_ccs"
- [(set (reg 33)
- (compare (match_operand:DI 0 "register_operand" "d,d,d")
- (match_operand:DI 1 "general_operand" "d,K,m")))]
- "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
+; tst(hi|qi) instruction pattern(s).
+
+(define_insn "*tstCCT"
+ [(set (reg CC_REGNUM)
+ (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d")
+ (match_operand:HQI 1 "const0_operand" "")))
+ (set (match_operand:HQI 2 "register_operand" "=d,d,0")
+ (match_dup 0))]
+ "s390_match_ccmode(insn, CCTmode)"
"@
- cgr\\t%0,%1
- cghi\\t%0,%c1
- cg\\t%0,%1"
- [(set_attr "op_type" "RRE,RI,RXE")
- (set_attr "atype" "reg,reg,mem")])
-
-(define_insn "*cmpdi_ccu"
- [(set (reg 33)
- (compare (match_operand:DI 0 "register_operand" "d,d")
- (match_operand:DI 1 "general_operand" "d,m")))]
- "s390_match_ccmode(insn, CCUmode) && TARGET_64BIT"
+ icm\t%2,,%S0
+ icmy\t%2,,%S0
+ tml\t%0,"
+ [(set_attr "op_type" "RS,RSY,RI")
+ (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
+
+(define_insn "*tsthiCCT_cconly"
+ [(set (reg CC_REGNUM)
+ (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d")
+ (match_operand:HI 1 "const0_operand" "")))
+ (clobber (match_scratch:HI 2 "=d,d,X"))]
+ "s390_match_ccmode(insn, CCTmode)"
"@
- clgr\\t%0,%1
- clg\\t%0,%1"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "atype" "reg,mem")])
-
-(define_insn "*cmpdi_ccu_mem"
- [(set (reg 33)
- (compare (match_operand:DI 0 "s_operand" "oQ")
- (match_operand:DI 1 "s_imm_operand" "oQ")))]
- "s390_match_ccmode(insn, CCUmode)"
- "clc\\t%O0(8,%R0),%1"
- [(set_attr "op_type" "SS")
- (set_attr "atype" "mem")])
-
-; SI instructions
-
-(define_insn "*cmpsi_tm2"
- [(set (reg 33)
- (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
- (match_operand:SI 1 "const_int_operand" "n")
- (match_operand:SI 2 "const_int_operand" "n"))
- (const_int 0)))]
- "s390_match_ccmode(insn, CCTmode)
- && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
- && INTVAL (operands[1]) + INTVAL (operands[2]) <= 32
- && (INTVAL (operands[1]) + INTVAL (operands[2]) - 1) >> 4
- == INTVAL (operands[2]) >> 4"
- "*
-{
- int part = INTVAL (operands[2]) >> 4;
- int block = (1 << INTVAL (operands[1])) - 1;
- int shift = 16 - INTVAL (operands[1]) - (INTVAL (operands[2]) & 15);
-
- operands[2] = GEN_INT (block << shift);
-
- switch (part)
- {
- case 0: return \"tmh\\t%0,%x2\";
- case 1: return \"tml\\t%0,%x2\";
- default: abort ();
- }
-}"
- [(set_attr "op_type" "RI")])
+ icm\t%2,3,%S0
+ icmy\t%2,3,%S0
+ tml\t%0,65535"
+ [(set_attr "op_type" "RS,RSY,RI")
+ (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
+
+(define_insn "*tstqiCCT_cconly"
+ [(set (reg CC_REGNUM)
+ (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
+ (match_operand:QI 1 "const0_operand" "")))]
+ "s390_match_ccmode(insn, CCTmode)"
+ "@
+ cli\t%S0,0
+ cliy\t%S0,0
+ tml\t%0,255"
+ [(set_attr "op_type" "SI,SIY,RI")
+ (set_attr "z10prop" "z10_super,z10_super,z10_super")])
+
+(define_insn "*tst"
+ [(set (reg CC_REGNUM)
+ (compare (match_operand:HQI 0 "s_operand" "Q,S")
+ (match_operand:HQI 1 "const0_operand" "")))
+ (set (match_operand:HQI 2 "register_operand" "=d,d")
+ (match_dup 0))]
+ "s390_match_ccmode(insn, CCSmode)"
+ "@
+ icm\t%2,,%S0
+ icmy\t%2,,%S0"
+ [(set_attr "op_type" "RS,RSY")
+ (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
+
+(define_insn "*tst_cconly"
+ [(set (reg CC_REGNUM)
+ (compare (match_operand:HQI 0 "s_operand" "Q,S")
+ (match_operand:HQI 1 "const0_operand" "")))
+ (clobber (match_scratch:HQI 2 "=d,d"))]
+ "s390_match_ccmode(insn, CCSmode)"
+ "@
+ icm\t%2,,%S0
+ icmy\t%2,,%S0"
+ [(set_attr "op_type" "RS,RSY")
+ (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
-(define_insn "*cmpsi_tm_reg"
- [(set (reg 33)
- (compare (and:SI (match_operand:SI 0 "register_operand" "%d")
- (match_operand:SI 1 "immediate_operand" "n"))
- (const_int 0)))]
- "s390_match_ccmode(insn, CCTmode)
- && s390_single_hi (operands[1], SImode, 0) >= 0"
- "*
-{
- int part = s390_single_hi (operands[1], SImode, 0);
- operands[1] = GEN_INT (s390_extract_hi (operands[1], SImode, part));
- switch (part)
- {
- case 0: return \"tmh\\t%0,%x1\";
- case 1: return \"tml\\t%0,%x1\";
- default: abort ();
- }
-}"
- [(set_attr "op_type" "RI")])
+; Compare (equality) instructions
-(define_insn "*cmpsi_tm_mem"
- [(set (reg 33)
- (compare (and:SI (match_operand:SI 0 "s_operand" "%Qo")
- (match_operand:SI 1 "immediate_operand" "n"))
- (const_int 0)))]
- "s390_match_ccmode(insn, CCTmode)
- && s390_single_qi (operands[1], SImode, 0) >= 0"
- "*
-{
- int part = s390_single_qi (operands[1], SImode, 0);
- operands[1] = GEN_INT (s390_extract_qi (operands[1], SImode, part));
-
- operands[0] = gen_rtx_MEM (QImode,
- plus_constant (XEXP (operands[0], 0), part));
- return \"tm\\t%0,%b1\";
-}"
- [(set_attr "op_type" "SI")
- (set_attr "atype" "mem")])
-
-(define_insn "*ltr"
- [(set (reg 33)
- (compare (match_operand:SI 0 "register_operand" "d")
- (match_operand:SI 1 "const0_operand" "")))
- (set (match_operand:SI 2 "register_operand" "=d")
- (match_dup 0))]
- "s390_match_ccmode(insn, CCSmode)"
- "ltr\\t%2,%0"
- [(set_attr "op_type" "RR")])
+(define_insn "*cmpdi_cct"
+ [(set (reg CC_REGNUM)
+ (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q")
+ (match_operand:DI 1 "general_operand" "d,K,Os,RT,BQ")))]
+ "s390_match_ccmode (insn, CCTmode) && TARGET_64BIT"
+ "@
+ cgr\t%0,%1
+ cghi\t%0,%h1
+ cgfi\t%0,%1
+ cg\t%0,%1
+ #"
+ [(set_attr "op_type" "RRE,RI,RIL,RXY,SS")
+ (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,*")])
+
+(define_insn "*cmpsi_cct"
+ [(set (reg CC_REGNUM)
+ (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q")
+ (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))]
+ "s390_match_ccmode (insn, CCTmode)"
+ "@
+ cr\t%0,%1
+ chi\t%0,%h1
+ cfi\t%0,%1
+ c\t%0,%1
+ cy\t%0,%1
+ #"
+ [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS")
+ (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*")])
-(define_insn "*icm15"
- [(set (reg 33)
- (compare (match_operand:SI 0 "s_operand" "Qo")
- (match_operand:SI 1 "const0_operand" "")))
- (set (match_operand:SI 2 "register_operand" "=d")
- (match_dup 0))]
- "s390_match_ccmode(insn, CCSmode)"
- "icm\\t%2,15,%0"
- [(set_attr "op_type" "RS")
- (set_attr "atype" "mem")])
+; Compare (signed) instructions
-(define_insn "*icm15_cconly"
- [(set (reg 33)
- (compare (match_operand:SI 0 "s_operand" "Qo")
- (match_operand:SI 1 "const0_operand" "")))
- (clobber (match_scratch:SI 2 "=d"))]
- "s390_match_ccmode(insn, CCSmode)"
- "icm\\t%2,15,%0"
- [(set_attr "op_type" "RS")
- (set_attr "atype" "mem")])
+(define_insn "*cmpdi_ccs_sign"
+ [(set (reg CC_REGNUM)
+ (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand"
+ "d,RT,b"))
+ (match_operand:DI 0 "register_operand" "d, d,d")))]
+ "s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT"
+ "@
+ cgfr\t%0,%1
+ cgf\t%0,%1
+ cgfrl\t%0,%1"
+ [(set_attr "op_type" "RRE,RXY,RIL")
+ (set_attr "z10prop" "z10_c,*,*")
+ (set_attr "type" "*,*,larl")])
-(define_insn "*cmpsi_ccs_0"
- [(set (reg 33)
- (compare (match_operand:SI 0 "register_operand" "d")
- (match_operand:SI 1 "const0_operand" "")))]
- "s390_match_ccmode(insn, CCSmode)"
- "ltr\\t%0,%0"
- [(set_attr "op_type" "RR")])
-(define_insn "*cmpsidi_ccs"
- [(set (reg 33)
- (compare (match_operand:SI 0 "register_operand" "d")
- (sign_extend:SI (match_operand:HI 1 "memory_operand" "m"))))]
- "s390_match_ccmode(insn, CCSmode)"
- "ch\\t%0,%1"
- [(set_attr "op_type" "RR")
- (set_attr "atype" "mem")])
-(define_insn "*cmpsi_ccs"
- [(set (reg 33)
- (compare (match_operand:SI 0 "register_operand" "d,d,d")
- (match_operand:SI 1 "general_operand" "d,K,m")))]
- "s390_match_ccmode(insn, CCSmode)"
+(define_insn "*cmpsi_ccs_sign"
+ [(set (reg CC_REGNUM)
+ (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T,b"))
+ (match_operand:SI 0 "register_operand" "d,d,d")))]
+ "s390_match_ccmode(insn, CCSRmode)"
"@
- cr\\t%0,%1
- chi\\t%0,%c1
- c\\t%0,%1"
- [(set_attr "op_type" "RR,RI,RX")
- (set_attr "atype" "reg,reg,mem")])
-
-(define_insn "*cmpsi_ccu"
- [(set (reg 33)
- (compare (match_operand:SI 0 "register_operand" "d,d")
- (match_operand:SI 1 "general_operand" "d,m")))]
- "s390_match_ccmode(insn, CCUmode)"
- "@
- clr\\t%0,%1
- cl\\t%0,%1"
- [(set_attr "op_type" "RR,RX")
- (set_attr "atype" "reg,mem")])
-
-(define_insn "*cmpsi_ccu_mem"
- [(set (reg 33)
- (compare (match_operand:SI 0 "s_operand" "oQ")
- (match_operand:SI 1 "s_imm_operand" "oQ")))]
- "s390_match_ccmode(insn, CCUmode)"
- "clc\\t%O0(4,%R0),%1"
- [(set_attr "op_type" "SS")
- (set_attr "atype" "mem")])
-
-
-; HI instructions
-
-(define_insn "*cmphi_tm_sub"
- [(set (reg 33)
- (compare (and:SI (subreg:SI (match_operand:HI 0 "s_operand" "%Qo") 0)
- (match_operand:SI 1 "immediate_operand" "n"))
- (const_int 0)))]
- "s390_match_ccmode(insn, CCTmode)
- && s390_single_qi (operands[1], HImode, 0) >= 0"
- "*
-{
- int part = s390_single_qi (operands[1], HImode, 0);
- operands[1] = GEN_INT (s390_extract_qi (operands[1], HImode, part));
-
- operands[0] = gen_rtx_MEM (QImode,
- plus_constant (XEXP (operands[0], 0), part));
- return \"tm\\t%0,%b1\";
-}"
- [(set_attr "op_type" "SI")
- (set_attr "atype" "mem")])
-
-(define_insn "*icm3"
- [(set (reg 33)
- (compare (match_operand:HI 0 "s_operand" "Qo")
- (match_operand:HI 1 "const0_operand" "")))
- (set (match_operand:HI 2 "register_operand" "=d")
- (match_dup 0))]
+ ch\t%0,%1
+ chy\t%0,%1
+ chrl\t%0,%1"
+ [(set_attr "op_type" "RX,RXY,RIL")
+ (set_attr "cpu_facility" "*,*,z10")
+ (set_attr "type" "*,*,larl")])
+
+(define_insn "*cmphi_ccs_z10"
+ [(set (reg CC_REGNUM)
+ (compare (match_operand:HI 0 "s_operand" "Q")
+ (match_operand:HI 1 "immediate_operand" "K")))]
+ "s390_match_ccmode(insn, CCSmode) && TARGET_Z10"
+ "chhsi\t%0,%1"
+ [(set_attr "op_type" "SIL")])
+
+(define_insn "*cmpdi_ccs_signhi_rl"
+ [(set (reg CC_REGNUM)
+ (compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT,b"))
+ (match_operand:GPR 0 "register_operand" "d,d")))]
+ "s390_match_ccmode(insn, CCSRmode) && TARGET_Z10"
+ "@
+ cgh\t%0,%1
+ cghrl\t%0,%1"
+ [(set_attr "op_type" "RXY,RIL")
+ (set_attr "type" "*,larl")])
+
+; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg, chsi, cghsi, crl, cgrl
+(define_insn "*cmp_ccs"
+ [(set (reg CC_REGNUM)
+ (compare (match_operand:GPR 0 "nonimmediate_operand"
+ "d,d,Q, d,d,d,d")
+ (match_operand:GPR 1 "general_operand"
+ "d,K,K,Os,R,T,b")))]
"s390_match_ccmode(insn, CCSmode)"
- "icm\\t%2,3,%0"
- [(set_attr "op_type" "RS")
- (set_attr "atype" "mem")])
+ "@
+ cr\t%0,%1
+ chi\t%0,%h1
+ chsi\t%0,%h1
+ cfi\t%0,%1
+ c\t%0,%1
+ c\t%0,%1
+ crl\t%0,%1"
+ [(set_attr "op_type" "RR,RI,SIL,RIL,RX,RXY,RIL")
+ (set_attr "cpu_facility" "*,*,z10,extimm,*,*,z10")
+ (set_attr "type" "*,*,*,*,*,*,larl")
+ (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super")])
+
+
+; Compare (unsigned) instructions
+
+(define_insn "*cmpsi_ccu_zerohi_rlsi"
+ [(set (reg CC_REGNUM)
+ (compare (zero_extend:SI (mem:HI (match_operand:SI 1
+ "larl_operand" "X")))
+ (match_operand:SI 0 "register_operand" "d")))]
+ "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
+ "clhrl\t%0,%1"
+ [(set_attr "op_type" "RIL")
+ (set_attr "type" "larl")
+ (set_attr "z10prop" "z10_super")])
+
+; clhrl, clghrl
+(define_insn "*cmp_ccu_zerohi_rldi"
+ [(set (reg CC_REGNUM)
+ (compare (zero_extend:GPR (mem:HI (match_operand:DI 1
+ "larl_operand" "X")))
+ (match_operand:GPR 0 "register_operand" "d")))]
+ "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
+ "clhrl\t%0,%1"
+ [(set_attr "op_type" "RIL")
+ (set_attr "type" "larl")
+ (set_attr "z10prop" "z10_super")])
+
+(define_insn "*cmpdi_ccu_zero"
+ [(set (reg CC_REGNUM)
+ (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand"
+ "d,RT,b"))
+ (match_operand:DI 0 "register_operand" "d, d,d")))]
+ "s390_match_ccmode (insn, CCURmode) && TARGET_64BIT"
+ "@
+ clgfr\t%0,%1
+ clgf\t%0,%1
+ clgfrl\t%0,%1"
+ [(set_attr "op_type" "RRE,RXY,RIL")
+ (set_attr "cpu_facility" "*,*,z10")
+ (set_attr "type" "*,*,larl")
+ (set_attr "z10prop" "z10_super_c,z10_super_E1,z10_super")])
-(define_insn "*cmphi_cct_0"
- [(set (reg 33)
- (compare (match_operand:HI 0 "register_operand" "d")
- (match_operand:HI 1 "const0_operand" "")))]
- "s390_match_ccmode(insn, CCTmode)"
- "tml\\t%0,65535"
- [(set_attr "op_type" "RX")])
+(define_insn "*cmpdi_ccu"
+ [(set (reg CC_REGNUM)
+ (compare (match_operand:DI 0 "nonimmediate_operand"
+ "d, d,d,Q, d, Q,BQ")
+ (match_operand:DI 1 "general_operand"
+ "d,Op,b,D,RT,BQ,Q")))]
+ "s390_match_ccmode (insn, CCUmode) && TARGET_64BIT"
+ "@
+ clgr\t%0,%1
+ clgfi\t%0,%1
+ clgrl\t%0,%1
+ clghsi\t%0,%x1
+ clg\t%0,%1
+ #
+ #"
+ [(set_attr "op_type" "RRE,RIL,RIL,SIL,RXY,SS,SS")
+ (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*")
+ (set_attr "type" "*,*,larl,*,*,*,*")
+ (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*,*")])
-(define_insn "*cmphi_ccs_0"
- [(set (reg 33)
- (compare (match_operand:HI 0 "s_operand" "Qo")
- (match_operand:HI 1 "const0_operand" "")))
- (clobber (match_scratch:HI 2 "=d"))]
- "s390_match_ccmode(insn, CCSmode)"
- "icm\\t%2,3,%0"
- [(set_attr "op_type" "RS")
- (set_attr "atype" "mem")])
+(define_insn "*cmpsi_ccu"
+ [(set (reg CC_REGNUM)
+ (compare (match_operand:SI 0 "nonimmediate_operand" "d, d,d,Q,d,d, Q,BQ")
+ (match_operand:SI 1 "general_operand" "d,Os,b,D,R,T,BQ, Q")))]
+ "s390_match_ccmode (insn, CCUmode)"
+ "@
+ clr\t%0,%1
+ clfi\t%0,%o1
+ clrl\t%0,%1
+ clfhsi\t%0,%x1
+ cl\t%0,%1
+ cly\t%0,%1
+ #
+ #"
+ [(set_attr "op_type" "RR,RIL,RIL,SIL,RX,RXY,SS,SS")
+ (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*,*")
+ (set_attr "type" "*,*,larl,*,*,*,*,*")
+ (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,*,*")])
(define_insn "*cmphi_ccu"
- [(set (reg 33)
- (compare (match_operand:HI 0 "register_operand" "d")
- (match_operand:HI 1 "s_imm_operand" "Qo")))]
- "s390_match_ccmode(insn, CCUmode)"
- "clm\\t%0,3,%1"
- [(set_attr "op_type" "RS")
- (set_attr "atype" "mem")])
-
-(define_insn "*cmphi_ccu_mem"
- [(set (reg 33)
- (compare (match_operand:HI 0 "s_operand" "oQ")
- (match_operand:HI 1 "s_imm_operand" "oQ")))]
- "s390_match_ccmode(insn, CCUmode)"
- "clc\\t%O0(2,%R0),%1"
- [(set_attr "op_type" "SS")
- (set_attr "atype" "mem")])
-
-
-; QI instructions
-
-(define_insn "*cmpqi_tm2"
- [(set (reg 33)
- (compare (zero_extract:SI (match_operand:QI 0 "s_operand" "Qo")
- (match_operand:SI 1 "const_int_operand" "n")
- (match_operand:SI 2 "const_int_operand" "n"))
- (const_int 0)))]
- "s390_match_ccmode(insn, CCTmode)
- && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
- && INTVAL (operands[1]) + INTVAL (operands[2]) <= 8"
- "*
-{
- int block = (1 << INTVAL (operands[1])) - 1;
- int shift = 8 - INTVAL (operands[1]) - INTVAL (operands[2]);
-
- operands[2] = GEN_INT (block << shift);
- return \"tm\\t%0,%b2\";
-}"
- [(set_attr "op_type" "SI")
- (set_attr "atype" "mem")])
-
-(define_insn "*cmpqi_tm"
- [(set (reg 33)
- (compare (and:QI (match_operand:QI 0 "nonimmediate_operand" "%d,Q")
- (match_operand:QI 1 "immediate_operand" "n,n"))
- (const_int 0)))]
- "s390_match_ccmode(insn, CCTmode)"
+ [(set (reg CC_REGNUM)
+ (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,Q,BQ")
+ (match_operand:HI 1 "general_operand" "Q,S,D,BQ,Q")))]
+ "s390_match_ccmode (insn, CCUmode)
+ && !register_operand (operands[1], HImode)"
"@
- tml\\t%0,%b1
- tm\\t%0,%b1"
- [(set_attr "op_type" "RI,SI")
- (set_attr "atype" "reg,mem")])
+ clm\t%0,3,%S1
+ clmy\t%0,3,%S1
+ clhhsi\t%0,%1
+ #
+ #"
+ [(set_attr "op_type" "RS,RSY,SIL,SS,SS")
+ (set_attr "cpu_facility" "*,*,z10,*,*")
+ (set_attr "z10prop" "*,*,z10_super,*,*")])
-(define_insn "*cmpqi_tm_sub"
- [(set (reg 33)
- (compare (and:SI (subreg:SI (match_operand:QI 0 "s_operand" "%Qo") 0)
- (match_operand:SI 1 "immediate_operand" "n"))
- (const_int 0)))]
- "s390_match_ccmode(insn, CCTmode)"
- "tm\\t%0,%b1"
- [(set_attr "op_type" "SI")
- (set_attr "atype" "mem")])
-
-(define_insn "*icm1"
- [(set (reg 33)
- (compare (match_operand:QI 0 "s_operand" "Qo")
- (match_operand:QI 1 "const0_operand" "")))
- (set (match_operand:QI 2 "register_operand" "=d")
- (match_dup 0))]
- "s390_match_ccmode(insn, CCSmode)"
- "icm\\t%2,1,%0"
- [(set_attr "op_type" "RS")
- (set_attr "atype" "mem")])
-
-(define_insn "*tm_0"
- [(set (reg 33)
- (compare (zero_extend:SI (and:QI (match_operand:QI 0 "s_operand" "Qo")
- (match_operand:QI 1 "immediate_operand" "")))
- (const_int 0)))]
- "s390_match_ccmode(insn, CCTmode) &&
- INTVAL(operands[1]) >= 0 && INTVAL(operands[1]) < 256"
- "tm\\t%0,%1"
- [(set_attr "op_type" "RI")
- (set_attr "atype" "mem")])
+(define_insn "*cmpqi_ccu"
+ [(set (reg CC_REGNUM)
+ (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ")
+ (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))]
+ "s390_match_ccmode (insn, CCUmode)
+ && !register_operand (operands[1], QImode)"
+ "@
+ clm\t%0,1,%S1
+ clmy\t%0,1,%S1
+ cli\t%S0,%b1
+ cliy\t%S0,%b1
+ #
+ #"
+ [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")
+ (set_attr "z10prop" "*,*,z10_super,z10_super,*,*")])
-(define_insn "*cmpqi_cct_0"
- [(set (reg 33)
- (compare (match_operand:QI 0 "register_operand" "d")
- (match_operand:QI 1 "const0_operand" "")))]
- "s390_match_ccmode(insn, CCTmode)"
- "tml\\t%0,255"
- [(set_attr "op_type" "RI")])
-(define_insn "*cmpqi_ccs_0"
- [(set (reg 33)
- (compare (match_operand:QI 0 "s_operand" "Qo")
- (match_operand:QI 1 "const0_operand" "")))
- (clobber (match_scratch:QI 2 "=d"))]
- "s390_match_ccmode(insn, CCSmode)"
- "icm\\t%2,1,%0"
- [(set_attr "op_type" "RS")
- (set_attr "atype" "mem")])
+; Block compare (CLC) instruction patterns.
-(define_insn "*cmpqi_ccu_0"
- [(set (reg 33)
- (compare (match_operand:QI 0 "s_operand" "Qo")
- (match_operand:QI 1 "const0_operand" "")))]
- "s390_match_ccmode(insn, CCUmode)"
- "cli\\t%0,0"
- [(set_attr "op_type" "SI")
- (set_attr "atype" "mem")])
+(define_insn "*clc"
+ [(set (reg CC_REGNUM)
+ (compare (match_operand:BLK 0 "memory_operand" "Q")
+ (match_operand:BLK 1 "memory_operand" "Q")))
+ (use (match_operand 2 "const_int_operand" "n"))]
+ "s390_match_ccmode (insn, CCUmode)
+ && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
+ "clc\t%O0(%2,%R0),%S1"
+ [(set_attr "op_type" "SS")])
-(define_insn "*cmpqi_ccu"
- [(set (reg 33)
- (compare (match_operand:QI 0 "register_operand" "d")
- (match_operand:QI 1 "s_imm_operand" "Qo")))]
- "s390_match_ccmode(insn, CCUmode)"
- "clm\\t%0,1,%1"
- [(set_attr "op_type" "RS")
- (set_attr "atype" "mem")])
-
-(define_insn "*cmpqi_ccu_immed"
- [(set (reg 33)
- (compare (match_operand:QI 0 "s_operand" "Qo")
- (match_operand:QI 1 "const_int_operand" "n")))]
- "s390_match_ccmode(insn, CCUmode) &&
- INTVAL(operands[1]) >= 0 && INTVAL(operands[1]) < 256"
- "cli\\t%0,%1"
- [(set_attr "op_type" "SI")
- (set_attr "atype" "mem")])
-
-(define_insn "*cmpqi_ccu_mem"
- [(set (reg 33)
- (compare (match_operand:QI 0 "s_operand" "oQ")
- (match_operand:QI 1 "s_imm_operand" "oQ")))]
- "s390_match_ccmode(insn, CCUmode)"
- "clc\\t%O0(1,%R0),%1"
- [(set_attr "op_type" "SS")
- (set_attr "atype" "mem")])
-
-
-; DF instructions
-
-(define_insn "*cmpdf_ccs_0"
- [(set (reg 33)
- (compare (match_operand:DF 0 "register_operand" "f")
- (match_operand:DF 1 "const0_operand" "")))]
- "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "ltdbr\\t%0,%0"
- [(set_attr "op_type" "RRE")])
-
-(define_insn "*cmpdf_ccs_0_ibm"
- [(set (reg 33)
- (compare (match_operand:DF 0 "register_operand" "f")
- (match_operand:DF 1 "const0_operand" "")))]
- "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
- "ltdr\\t%0,%0"
- [(set_attr "op_type" "RR")])
-
-(define_insn "*cmpdf_ccs"
- [(set (reg 33)
- (compare (match_operand:DF 0 "register_operand" "f,f")
- (match_operand:DF 1 "general_operand" "f,m")))]
- "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "@
- cdbr\\t%0,%1
- cdb\\t%0,%1"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "atype" "reg,mem")])
-
-(define_insn "*cmpdf_ccs_ibm"
- [(set (reg 33)
- (compare (match_operand:DF 0 "register_operand" "f,f")
- (match_operand:DF 1 "general_operand" "f,m")))]
- "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
- "@
- cdr\\t%0,%1
- cd\\t%0,%1"
- [(set_attr "op_type" "RR,RX")
- (set_attr "atype" "reg,mem")])
-
-
-; SF instructions
-
-(define_insn "*cmpsf_ccs_0"
- [(set (reg 33)
- (compare (match_operand:SF 0 "register_operand" "f")
- (match_operand:SF 1 "const0_operand" "")))]
- "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "ltebr\\t%0,%0"
- [(set_attr "op_type" "RRE")])
-
-(define_insn "*cmpsf_ccs_0_ibm"
- [(set (reg 33)
- (compare (match_operand:SF 0 "register_operand" "f")
- (match_operand:SF 1 "const0_operand" "")))]
- "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
- "lter\\t%0,%0"
- [(set_attr "op_type" "RR")])
-
-(define_insn "*cmpsf_ccs"
- [(set (reg 33)
- (compare (match_operand:SF 0 "register_operand" "f,f")
- (match_operand:SF 1 "general_operand" "f,m")))]
- "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "@
- cebr\\t%0,%1
- ceb\\t%0,%1"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "atype" "reg,mem")])
+(define_split
+ [(set (reg CC_REGNUM)
+ (compare (match_operand 0 "memory_operand" "")
+ (match_operand 1 "memory_operand" "")))]
+ "reload_completed
+ && s390_match_ccmode (insn, CCUmode)
+ && GET_MODE (operands[0]) == GET_MODE (operands[1])
+ && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
+ [(parallel
+ [(set (match_dup 0) (match_dup 1))
+ (use (match_dup 2))])]
+{
+ operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
+ operands[0] = adjust_address (operands[0], BLKmode, 0);
+ operands[1] = adjust_address (operands[1], BLKmode, 0);
-(define_insn "*cmpsf_ccs"
- [(set (reg 33)
- (compare (match_operand:SF 0 "register_operand" "f,f")
- (match_operand:SF 1 "general_operand" "f,m")))]
- "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
- "@
- cer\\t%0,%1
- ce\\t%0,%1"
- [(set_attr "op_type" "RR,RX")
- (set_attr "atype" "reg,mem")])
+ operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))),
+ operands[0], operands[1]);
+ operands[0] = SET_DEST (PATTERN (curr_insn));
+})
+; (TF|DF|SF|TD|DD|SD) instructions
+
+; ltxbr, ltdbr, ltebr, ltxtr, ltdtr
+(define_insn "*cmp_ccs_0"
+ [(set (reg CC_REGNUM)
+ (compare (match_operand:FP 0 "register_operand" "f")
+ (match_operand:FP 1 "const0_operand" "")))]
+ "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
+ "ltr\t%0,%0"
+ [(set_attr "op_type" "RRE")
+ (set_attr "type" "fsimp")])
+
+; cxtr, cxbr, cdbr, cebr, cdb, ceb, cxbtr, cdbtr
+(define_insn "*cmp_ccs"
+ [(set (reg CC_REGNUM)
+ (compare (match_operand:FP 0 "register_operand" "f,f")
+ (match_operand:FP 1 "general_operand" "f,")))]
+ "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
+ "@
+ cr\t%0,%1
+ cb\t%0,%1"
+ [(set_attr "op_type" "RRE,RXE")
+ (set_attr "type" "fsimp")])
+
+
+; Compare and Branch instructions
+
+; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
+; The following instructions do a complementary access of their second
+; operand (z01 only): crj_c, cgrjc, cr, cgr
+(define_insn "*cmp_and_br_signed_"
+ [(set (pc)
+ (if_then_else (match_operator 0 "s390_signed_integer_comparison"
+ [(match_operand:GPR 1 "register_operand" "d,d")
+ (match_operand:GPR 2 "nonmemory_operand" "d,C")])
+ (label_ref (match_operand 3 "" ""))
+ (pc)))
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_Z10"
+{
+ if (get_attr_length (insn) == 6)
+ return which_alternative ?
+ "cij%C0\t%1,%c2,%l3" : "crj%C0\t%1,%2,%l3";
+ else
+ return which_alternative ?
+ "cfi\t%1,%c2\;jg%C0\t%l3" : "cr\t%1,%2\;jg%C0\t%l3";
+}
+ [(set_attr "op_type" "RIE")
+ (set_attr "type" "branch")
+ (set_attr "z10prop" "z10_super_c,z10_super")
+ (set (attr "length")
+ (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
+ (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
+ ; 10 byte for cgr/jg
+
+; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
+; The following instructions do a complementary access of their second
+; operand (z10 only): clrj, clgrj, clr, clgr
+(define_insn "*cmp_and_br_unsigned_"
+ [(set (pc)
+ (if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
+ [(match_operand:GPR 1 "register_operand" "d,d")
+ (match_operand:GPR 2 "nonmemory_operand" "d,I")])
+ (label_ref (match_operand 3 "" ""))
+ (pc)))
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_Z10"
+{
+ if (get_attr_length (insn) == 6)
+ return which_alternative ?
+ "clij%C0\t%1,%b2,%l3" : "clrj%C0\t%1,%2,%l3";
+ else
+ return which_alternative ?
+ "clfi\t%1,%b2\;jg%C0\t%l3" : "clr\t%1,%2\;jg%C0\t%l3";
+}
+ [(set_attr "op_type" "RIE")
+ (set_attr "type" "branch")
+ (set_attr "z10prop" "z10_super_c,z10_super")
+ (set (attr "length")
+ (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
+ (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
+ ; 10 byte for clgr/jg
+
+; And now the same two patterns as above but with a negated CC mask.
+
+; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
+; The following instructions do a complementary access of their second
+; operand (z01 only): crj_c, cgrjc, cr, cgr
+(define_insn "*icmp_and_br_signed_"
+ [(set (pc)
+ (if_then_else (match_operator 0 "s390_signed_integer_comparison"
+ [(match_operand:GPR 1 "register_operand" "d,d")
+ (match_operand:GPR 2 "nonmemory_operand" "d,C")])
+ (pc)
+ (label_ref (match_operand 3 "" ""))))
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_Z10"
+{
+ if (get_attr_length (insn) == 6)
+ return which_alternative ?
+ "cij%D0\t%1,%c2,%l3" : "crj%D0\t%1,%2,%l3";
+ else
+ return which_alternative ?
+ "cfi\t%1,%c2\;jg%D0\t%l3" : "cr\t%1,%2\;jg%D0\t%l3";
+}
+ [(set_attr "op_type" "RIE")
+ (set_attr "type" "branch")
+ (set_attr "z10prop" "z10_super_c,z10_super")
+ (set (attr "length")
+ (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
+ (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
+ ; 10 byte for cgr/jg
+
+; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
+; The following instructions do a complementary access of their second
+; operand (z10 only): clrj, clgrj, clr, clgr
+(define_insn "*icmp_and_br_unsigned_"
+ [(set (pc)
+ (if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
+ [(match_operand:GPR 1 "register_operand" "d,d")
+ (match_operand:GPR 2 "nonmemory_operand" "d,I")])
+ (pc)
+ (label_ref (match_operand 3 "" ""))))
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_Z10"
+{
+ if (get_attr_length (insn) == 6)
+ return which_alternative ?
+ "clij%D0\t%1,%b2,%l3" : "clrj%D0\t%1,%2,%l3";
+ else
+ return which_alternative ?
+ "clfi\t%1,%b2\;jg%D0\t%l3" : "clr\t%1,%2\;jg%D0\t%l3";
+}
+ [(set_attr "op_type" "RIE")
+ (set_attr "type" "branch")
+ (set_attr "z10prop" "z10_super_c,z10_super")
+ (set (attr "length")
+ (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
+ (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
+ ; 10 byte for clgr/jg
+
;;
;;- Move instructions.
;;
@@ -804,559 +1142,1162 @@
; movti instruction pattern(s).
;
-(define_insn "*movti_ss"
- [(set (match_operand:TI 0 "s_operand" "=Qo")
- (match_operand:TI 1 "s_imm_operand" "Qo"))]
- ""
- "mvc\\t%O0(16,%R0),%1"
- [(set_attr "op_type" "SS")
- (set_attr "atype" "mem")])
-
(define_insn "movti"
- [(set (match_operand:TI 0 "nonimmediate_operand" "=d,Q,d,m")
- (match_operand:TI 1 "general_operand" "Q,d,dKm,d"))]
+ [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o")
+ (match_operand:TI 1 "general_operand" "QS,d,dPRT,d"))]
"TARGET_64BIT"
"@
- lmg\\t%0,%N0,%1
- stmg\\t%1,%N1,%0
+ lmg\t%0,%N0,%S1
+ stmg\t%1,%N1,%S0
#
#"
- [(set_attr "op_type" "RSE,RSE,NN,NN")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "RSY,RSY,*,*")
+ (set_attr "type" "lm,stm,*,*")])
(define_split
[(set (match_operand:TI 0 "nonimmediate_operand" "")
(match_operand:TI 1 "general_operand" ""))]
"TARGET_64BIT && reload_completed
- && !s_operand (operands[0], VOIDmode)
- && !s_operand (operands[1], VOIDmode)
- && (register_operand (operands[0], VOIDmode)
- || register_operand (operands[1], VOIDmode))
- && (!register_operand (operands[0], VOIDmode)
- || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, TImode),
- operands[1])
- || !reg_overlap_mentioned_p (operand_subword (operands[0], 1, 0, TImode),
- operands[1]))"
+ && s390_split_ok_p (operands[0], operands[1], TImode, 0)"
[(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 5))]
- "
{
- if (!register_operand (operands[0], VOIDmode)
- || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, TImode),
- operands[1]))
- {
- operands[2] = operand_subword (operands[0], 0, 0, TImode);
- operands[3] = operand_subword (operands[0], 1, 0, TImode);
- operands[4] = operand_subword (operands[1], 0, 0, TImode);
- operands[5] = operand_subword (operands[1], 1, 0, TImode);
- }
- else
- {
- operands[2] = operand_subword (operands[0], 1, 0, TImode);
- operands[3] = operand_subword (operands[0], 0, 0, TImode);
- operands[4] = operand_subword (operands[1], 1, 0, TImode);
- operands[5] = operand_subword (operands[1], 0, 0, TImode);
- }
-}")
+ operands[2] = operand_subword (operands[0], 0, 0, TImode);
+ operands[3] = operand_subword (operands[0], 1, 0, TImode);
+ operands[4] = operand_subword (operands[1], 0, 0, TImode);
+ operands[5] = operand_subword (operands[1], 1, 0, TImode);
+})
+
+(define_split
+ [(set (match_operand:TI 0 "nonimmediate_operand" "")
+ (match_operand:TI 1 "general_operand" ""))]
+ "TARGET_64BIT && reload_completed
+ && s390_split_ok_p (operands[0], operands[1], TImode, 1)"
+ [(set (match_dup 2) (match_dup 4))
+ (set (match_dup 3) (match_dup 5))]
+{
+ operands[2] = operand_subword (operands[0], 1, 0, TImode);
+ operands[3] = operand_subword (operands[0], 0, 0, TImode);
+ operands[4] = operand_subword (operands[1], 1, 0, TImode);
+ operands[5] = operand_subword (operands[1], 0, 0, TImode);
+})
(define_split
[(set (match_operand:TI 0 "register_operand" "")
(match_operand:TI 1 "memory_operand" ""))]
"TARGET_64BIT && reload_completed
&& !s_operand (operands[1], VOIDmode)"
- [(set (match_dup 2) (match_dup 3))
- (set (match_dup 0) (mem:TI (match_dup 2)))]
- "operands[2] = operand_subword (operands[0], 1, 0, TImode);
- operands[3] = legitimize_la_operand (XEXP (operands[1], 0));")
+ [(set (match_dup 0) (match_dup 1))]
+{
+ rtx addr = operand_subword (operands[0], 1, 0, TImode);
+ s390_load_address (addr, XEXP (operands[1], 0));
+ operands[1] = replace_equiv_address (operands[1], addr);
+})
+
;
-; movdi instruction pattern(s).
+; Patterns used for secondary reloads
;
-;; If generating PIC code and operands[1] is a symbolic CONST, emit a
-;; move to get the address of the symbolic object from the GOT.
+; z10 provides move instructions accepting larl memory operands.
+; Unfortunately there is no such variant for QI, TI and FP mode moves.
+; These patterns are also used for unaligned SI and DI accesses.
+
+(define_expand "reload_tomem_z10"
+ [(parallel [(match_operand:INTALL 0 "memory_operand" "")
+ (match_operand:INTALL 1 "register_operand" "=d")
+ (match_operand:P 2 "register_operand" "=&a")])]
+ "TARGET_Z10"
+{
+ s390_reload_symref_address (operands[1], operands[0], operands[2], 1);
+ DONE;
+})
+
+(define_expand "reload_toreg_z10"
+ [(parallel [(match_operand:INTALL 0 "register_operand" "=d")
+ (match_operand:INTALL 1 "memory_operand" "")
+ (match_operand:P 2 "register_operand" "=a")])]
+ "TARGET_Z10"
+{
+ s390_reload_symref_address (operands[0], operands[1], operands[2], 0);
+ DONE;
+})
+
+(define_expand "reload_tomem_z10"
+ [(parallel [(match_operand:FPALL 0 "memory_operand" "")
+ (match_operand:FPALL 1 "register_operand" "=d")
+ (match_operand:P 2 "register_operand" "=&a")])]
+ "TARGET_Z10"
+{
+ s390_reload_symref_address (operands[1], operands[0], operands[2], 1);
+ DONE;
+})
+
+(define_expand "reload_toreg_z10"
+ [(parallel [(match_operand:FPALL 0 "register_operand" "=d")
+ (match_operand:FPALL 1 "memory_operand" "")
+ (match_operand:P 2 "register_operand" "=a")])]
+ "TARGET_Z10"
+{
+ s390_reload_symref_address (operands[0], operands[1], operands[2], 0);
+ DONE;
+})
+
+(define_expand "reload_larl_odd_addend_z10"
+ [(parallel [(match_operand:P 0 "register_operand" "=d")
+ (match_operand:P 1 "larl_operand" "")
+ (match_operand:P 2 "register_operand" "=a")])]
+ "TARGET_Z10"
+{
+ s390_reload_larl_operand (operands[0], operands[1], operands[2]);
+ DONE;
+})
+
+; Handles loading a PLUS (load address) expression
+
+(define_expand "reload_plus"
+ [(parallel [(match_operand:P 0 "register_operand" "=a")
+ (match_operand:P 1 "s390_plus_operand" "")
+ (match_operand:P 2 "register_operand" "=&a")])]
+ ""
+{
+ s390_expand_plus_operand (operands[0], operands[1], operands[2]);
+ DONE;
+})
+
+; Handles assessing a non-offsetable memory address
+
+(define_expand "reload_nonoffmem_in"
+ [(parallel [(match_operand 0 "register_operand" "")
+ (match_operand 1 "" "")
+ (match_operand:P 2 "register_operand" "=&a")])]
+ ""
+{
+ gcc_assert (MEM_P (operands[1]));
+ s390_load_address (operands[2], find_replacement (&XEXP (operands[1], 0)));
+ operands[1] = replace_equiv_address (operands[1], operands[2]);
+ emit_move_insn (operands[0], operands[1]);
+ DONE;
+})
+
+(define_expand "reload_nonoffmem_out"
+ [(parallel [(match_operand 0 "" "")
+ (match_operand 1 "register_operand" "")
+ (match_operand:P 2 "register_operand" "=&a")])]
+ ""
+{
+ gcc_assert (MEM_P (operands[0]));
+ s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
+ operands[0] = replace_equiv_address (operands[0], operands[2]);
+ emit_move_insn (operands[0], operands[1]);
+ DONE;
+})
+
+(define_expand "reload_PIC_addr"
+ [(parallel [(match_operand 0 "register_operand" "=d")
+ (match_operand 1 "larl_operand" "")
+ (match_operand:P 2 "register_operand" "=a")])]
+ ""
+{
+ rtx new_rtx = legitimize_pic_address (operands[1], operands[2]);
+ emit_move_insn (operands[0], new_rtx);
+})
+
+;
+; movdi instruction pattern(s).
+;
(define_expand "movdi"
[(set (match_operand:DI 0 "general_operand" "")
(match_operand:DI 1 "general_operand" ""))]
""
- "
-{
- /* Handle PIC symbolic constants. */
- if (TARGET_64BIT && flag_pic && SYMBOLIC_CONST (operands[1]))
- emit_pic_move (operands, DImode);
-
- /* During and after reload, we need to force constants
- to the literal pool ourselves, if necessary. */
- if ((reload_in_progress || reload_completed)
- && CONSTANT_P (operands[1])
- && (!legitimate_reload_constant_p (operands[1])
- || fp_operand (operands[0], VOIDmode)))
- operands[1] = force_const_mem (DImode, operands[1]);
-}")
-
-(define_insn "*movdi_lhi"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (match_operand:DI 1 "immediate_operand" "K"))]
- "TARGET_64BIT
- && GET_CODE (operands[1]) == CONST_INT
- && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K')
- && !fp_operand (operands[0], VOIDmode)"
- "lghi\\t%0,%h1"
- [(set_attr "op_type" "RI")
- (set_attr "atype" "reg")])
-
-(define_insn "*movdi_lli"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (match_operand:DI 1 "immediate_operand" "n"))]
- "TARGET_64BIT && s390_single_hi (operands[1], DImode, 0) >= 0
- && !fp_operand (operands[0], VOIDmode)"
- "*
{
- int part = s390_single_hi (operands[1], DImode, 0);
- operands[1] = GEN_INT (s390_extract_hi (operands[1], DImode, part));
-
- switch (part)
- {
- case 0: return \"llihh\\t%0,%x1\";
- case 1: return \"llihl\\t%0,%x1\";
- case 2: return \"llilh\\t%0,%x1\";
- case 3: return \"llill\\t%0,%x1\";
- default: abort ();
- }
-}"
- [(set_attr "op_type" "RI")
- (set_attr "atype" "reg")])
+ /* Handle symbolic constants. */
+ if (TARGET_64BIT
+ && (SYMBOLIC_CONST (operands[1])
+ || (GET_CODE (operands[1]) == PLUS
+ && XEXP (operands[1], 0) == pic_offset_table_rtx
+ && SYMBOLIC_CONST (XEXP (operands[1], 1)))))
+ emit_symbolic_move (operands);
+})
(define_insn "*movdi_larl"
[(set (match_operand:DI 0 "register_operand" "=d")
(match_operand:DI 1 "larl_operand" "X"))]
"TARGET_64BIT
- && !fp_operand (operands[0], VOIDmode)"
- "larl\\t%0,%1"
+ && !FP_REG_P (operands[0])"
+ "larl\t%0,%1"
[(set_attr "op_type" "RIL")
- (set_attr "atype" "reg")
- (set_attr "type" "la")])
-
-(define_insn "*movdi_ss"
- [(set (match_operand:DI 0 "s_operand" "=Qo")
- (match_operand:DI 1 "s_imm_operand" "Qo"))]
- ""
- "mvc\\t%O0(8,%R0),%1"
- [(set_attr "op_type" "SS")
- (set_attr "atype" "mem")])
+ (set_attr "type" "larl")
+ (set_attr "z10prop" "z10_super_A1")])
(define_insn "*movdi_64"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,m,!*f,!*f,!m")
- (match_operand:DI 1 "general_operand" "d,m,d,*f,m,*f"))]
+ [(set (match_operand:DI 0 "nonimmediate_operand"
+ "=d,d,d,d,d,d,d,d,f,d,d,d,d,d,
+ RT,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t")
+ (match_operand:DI 1 "general_operand"
+ "K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,RT,
+ d,*f,R,T,*f,*f,d,K,t,d,t,Q"))]
"TARGET_64BIT"
"@
- lgr\\t%0,%1
- lg\\t%0,%1
- stg\\t%1,%0
- ldr\\t%0,%1
- ld\\t%0,%1
- std\\t%1,%0"
- [(set_attr "op_type" "RRE,RXE,RXE,RR,RX,RX")
- (set_attr "atype" "reg,mem,mem,reg,mem,mem")])
+ lghi\t%0,%h1
+ llihh\t%0,%i1
+ llihl\t%0,%i1
+ llilh\t%0,%i1
+ llill\t%0,%i1
+ lgfi\t%0,%1
+ llihf\t%0,%k1
+ llilf\t%0,%k1
+ ldgr\t%0,%1
+ lgdr\t%0,%1
+ lay\t%0,%a1
+ lgrl\t%0,%1
+ lgr\t%0,%1
+ lg\t%0,%1
+ stg\t%1,%0
+ ldr\t%0,%1
+ ld\t%0,%1
+ ldy\t%0,%1
+ std\t%1,%0
+ stdy\t%1,%0
+ stgrl\t%1,%0
+ mvghi\t%0,%1
+ #
+ #
+ stam\t%1,%N1,%S0
+ lam\t%0,%N0,%S1"
+ [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RXY,RIL,RRE,RXY,
+ RXY,RR,RX,RXY,RX,RXY,RIL,SIL,*,*,RS,RS")
+ (set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,la,larl,lr,load,store,
+ floaddf,floaddf,floaddf,fstoredf,fstoredf,larl,*,*,*,
+ *,*")
+ (set_attr "cpu_facility" "*,*,*,*,*,extimm,extimm,extimm,dfp,dfp,longdisp,
+ z10,*,*,*,*,*,longdisp,*,longdisp,
+ z10,z10,*,*,*,*")
+ (set_attr "z10prop" "z10_fwd_A1,
+ z10_fwd_E1,
+ z10_fwd_E1,
+ z10_fwd_E1,
+ z10_fwd_E1,
+ z10_fwd_A1,
+ z10_fwd_E1,
+ z10_fwd_E1,
+ *,
+ *,
+ z10_fwd_A1,
+ z10_fwd_A3,
+ z10_fr_E1,
+ z10_fwd_A3,
+ z10_rec,
+ *,
+ *,
+ *,
+ *,
+ *,
+ z10_rec,
+ z10_super,
+ *,
+ *,
+ *,
+ *")
+])
+
+(define_split
+ [(set (match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "register_operand" ""))]
+ "TARGET_64BIT && ACCESS_REG_P (operands[1])"
+ [(set (match_dup 2) (match_dup 3))
+ (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
+ (set (strict_low_part (match_dup 2)) (match_dup 4))]
+ "operands[2] = gen_lowpart (SImode, operands[0]);
+ s390_split_access_reg (operands[1], &operands[4], &operands[3]);")
+
+(define_split
+ [(set (match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "register_operand" ""))]
+ "TARGET_64BIT && ACCESS_REG_P (operands[0])
+ && dead_or_set_p (insn, operands[1])"
+ [(set (match_dup 3) (match_dup 2))
+ (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32)))
+ (set (match_dup 4) (match_dup 2))]
+ "operands[2] = gen_lowpart (SImode, operands[1]);
+ s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
+
+(define_split
+ [(set (match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "register_operand" ""))]
+ "TARGET_64BIT && ACCESS_REG_P (operands[0])
+ && !dead_or_set_p (insn, operands[1])"
+ [(set (match_dup 3) (match_dup 2))
+ (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))
+ (set (match_dup 4) (match_dup 2))
+ (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))]
+ "operands[2] = gen_lowpart (SImode, operands[1]);
+ s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
(define_insn "*movdi_31"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=d,Q,d,m,!*f,!*f,!m")
- (match_operand:DI 1 "general_operand" "Q,d,dKm,d,*f,m,*f"))]
+ [(set (match_operand:DI 0 "nonimmediate_operand"
+ "=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,d")
+ (match_operand:DI 1 "general_operand"
+ " Q,S,d,d,dPRT,d, *f, R, T,*f,*f,b"))]
"!TARGET_64BIT"
"@
- lm\\t%0,%N0,%1
- stm\\t%1,%N1,%0
+ lm\t%0,%N0,%S1
+ lmy\t%0,%N0,%S1
+ stm\t%1,%N1,%S0
+ stmy\t%1,%N1,%S0
#
#
- ldr\\t%0,%1
- ld\\t%0,%1
- std\\t%1,%0"
- [(set_attr "op_type" "RS,RS,NN,NN,RR,RX,RX")
- (set_attr "atype" "mem,mem,*,*,reg,mem,mem")])
+ ldr\t%0,%1
+ ld\t%0,%1
+ ldy\t%0,%1
+ std\t%1,%0
+ stdy\t%1,%0
+ #"
+ [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,*")
+ (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")
+ (set_attr "cpu_facility" "*,*,*,*,*,*,*,*,*,*,*,z10")])
+
+; For a load from a symbol ref we can use one of the target registers
+; together with larl to load the address.
+(define_split
+ [(set (match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "memory_operand" ""))]
+ "!TARGET_64BIT && reload_completed && TARGET_Z10
+ && larl_operand (XEXP (operands[1], 0), SImode)"
+ [(set (match_dup 2) (match_dup 3))
+ (set (match_dup 0) (match_dup 1))]
+{
+ operands[2] = operand_subword (operands[0], 1, 0, DImode);
+ operands[3] = XEXP (operands[1], 0);
+ operands[1] = replace_equiv_address (operands[1], operands[2]);
+})
(define_split
[(set (match_operand:DI 0 "nonimmediate_operand" "")
(match_operand:DI 1 "general_operand" ""))]
"!TARGET_64BIT && reload_completed
- && !fp_operand (operands[0], VOIDmode)
- && !fp_operand (operands[1], VOIDmode)
- && !s_operand (operands[0], VOIDmode)
- && !s_operand (operands[1], VOIDmode)
- && (register_operand (operands[0], VOIDmode)
- || register_operand (operands[1], VOIDmode))
- && (!register_operand (operands[0], VOIDmode)
- || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DImode),
- operands[1])
- || !reg_overlap_mentioned_p (operand_subword (operands[0], 1, 0, DImode),
- operands[1]))"
+ && s390_split_ok_p (operands[0], operands[1], DImode, 0)"
[(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 5))]
- "
{
- if (!register_operand (operands[0], VOIDmode)
- || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DImode),
- operands[1]))
- {
- operands[2] = operand_subword (operands[0], 0, 0, DImode);
- operands[3] = operand_subword (operands[0], 1, 0, DImode);
- operands[4] = operand_subword (operands[1], 0, 0, DImode);
- operands[5] = operand_subword (operands[1], 1, 0, DImode);
- }
- else
- {
- operands[2] = operand_subword (operands[0], 1, 0, DImode);
- operands[3] = operand_subword (operands[0], 0, 0, DImode);
- operands[4] = operand_subword (operands[1], 1, 0, DImode);
- operands[5] = operand_subword (operands[1], 0, 0, DImode);
- }
-}")
+ operands[2] = operand_subword (operands[0], 0, 0, DImode);
+ operands[3] = operand_subword (operands[0], 1, 0, DImode);
+ operands[4] = operand_subword (operands[1], 0, 0, DImode);
+ operands[5] = operand_subword (operands[1], 1, 0, DImode);
+})
+
+(define_split
+ [(set (match_operand:DI 0 "nonimmediate_operand" "")
+ (match_operand:DI 1 "general_operand" ""))]
+ "!TARGET_64BIT && reload_completed
+ && s390_split_ok_p (operands[0], operands[1], DImode, 1)"
+ [(set (match_dup 2) (match_dup 4))
+ (set (match_dup 3) (match_dup 5))]
+{
+ operands[2] = operand_subword (operands[0], 1, 0, DImode);
+ operands[3] = operand_subword (operands[0], 0, 0, DImode);
+ operands[4] = operand_subword (operands[1], 1, 0, DImode);
+ operands[5] = operand_subword (operands[1], 0, 0, DImode);
+})
(define_split
[(set (match_operand:DI 0 "register_operand" "")
(match_operand:DI 1 "memory_operand" ""))]
"!TARGET_64BIT && reload_completed
- && !fp_operand (operands[0], VOIDmode)
- && !fp_operand (operands[1], VOIDmode)
+ && !FP_REG_P (operands[0])
&& !s_operand (operands[1], VOIDmode)"
- [(set (match_dup 2) (match_dup 3))
- (set (match_dup 0) (mem:DI (match_dup 2)))]
- "operands[2] = operand_subword (operands[0], 1, 0, DImode);
- operands[3] = legitimize_la_operand (XEXP (operands[1], 0));")
+ [(set (match_dup 0) (match_dup 1))]
+{
+ rtx addr = operand_subword (operands[0], 1, 0, DImode);
+ s390_load_address (addr, XEXP (operands[1], 0));
+ operands[1] = replace_equiv_address (operands[1], addr);
+})
+
+(define_peephole2
+ [(set (match_operand:DI 0 "register_operand" "")
+ (mem:DI (match_operand 1 "address_operand" "")))]
+ "TARGET_64BIT
+ && !FP_REG_P (operands[0])
+ && GET_CODE (operands[1]) == SYMBOL_REF
+ && CONSTANT_POOL_ADDRESS_P (operands[1])
+ && get_pool_mode (operands[1]) == DImode
+ && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
+ [(set (match_dup 0) (match_dup 2))]
+ "operands[2] = get_pool_constant (operands[1]);")
+
+(define_insn "*la_64"
+ [(set (match_operand:DI 0 "register_operand" "=d,d")
+ (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))]
+ "TARGET_64BIT"
+ "@
+ la\t%0,%a1
+ lay\t%0,%a1"
+ [(set_attr "op_type" "RX,RXY")
+ (set_attr "type" "la")
+ (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
+
+(define_peephole2
+ [(parallel
+ [(set (match_operand:DI 0 "register_operand" "")
+ (match_operand:QI 1 "address_operand" ""))
+ (clobber (reg:CC CC_REGNUM))])]
+ "TARGET_64BIT
+ && preferred_la_operand_p (operands[1], const0_rtx)"
+ [(set (match_dup 0) (match_dup 1))]
+ "")
+
+(define_peephole2
+ [(set (match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "register_operand" ""))
+ (parallel
+ [(set (match_dup 0)
+ (plus:DI (match_dup 0)
+ (match_operand:DI 2 "nonmemory_operand" "")))
+ (clobber (reg:CC CC_REGNUM))])]
+ "TARGET_64BIT
+ && !reg_overlap_mentioned_p (operands[0], operands[2])
+ && preferred_la_operand_p (operands[1], operands[2])"
+ [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
+ "")
;
; movsi instruction pattern(s).
;
-;; If generating PIC code and operands[1] is a symbolic CONST, emit a
-;; move to get the address of the symbolic object from the GOT.
-
(define_expand "movsi"
[(set (match_operand:SI 0 "general_operand" "")
(match_operand:SI 1 "general_operand" ""))]
""
- "
-{
- /* Handle PIC symbolic constants. */
- if (!TARGET_64BIT && flag_pic && SYMBOLIC_CONST (operands[1]))
- emit_pic_move (operands, SImode);
-
- /* expr.c tries to load an effective address using
- force_reg. This fails because we don't have a
- generic load_address pattern. Convert the move
- to a proper arithmetic operation instead, unless
- it is guaranteed to be OK. */
- if (GET_CODE (operands[1]) == PLUS
- && !legitimate_la_operand_p (operands[1]))
- {
- operands[1] = force_operand (operands[1], operands[0]);
- if (operands[1] == operands[0])
- DONE;
- }
+{
+ /* Handle symbolic constants. */
+ if (!TARGET_64BIT
+ && (SYMBOLIC_CONST (operands[1])
+ || (GET_CODE (operands[1]) == PLUS
+ && XEXP (operands[1], 0) == pic_offset_table_rtx
+ && SYMBOLIC_CONST (XEXP(operands[1], 1)))))
+ emit_symbolic_move (operands);
+})
+
+(define_insn "*movsi_larl"
+ [(set (match_operand:SI 0 "register_operand" "=d")
+ (match_operand:SI 1 "larl_operand" "X"))]
+ "!TARGET_64BIT && TARGET_CPU_ZARCH
+ && !FP_REG_P (operands[0])"
+ "larl\t%0,%1"
+ [(set_attr "op_type" "RIL")
+ (set_attr "type" "larl")
+ (set_attr "z10prop" "z10_fwd_A1")])
+
+(define_insn "*movsi_zarch"
+ [(set (match_operand:SI 0 "nonimmediate_operand"
+ "=d,d,d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t")
+ (match_operand:SI 1 "general_operand"
+ "K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,d,K,Q"))]
+ "TARGET_ZARCH"
+ "@
+ lhi\t%0,%h1
+ llilh\t%0,%i1
+ llill\t%0,%i1
+ iilf\t%0,%o1
+ lay\t%0,%a1
+ lrl\t%0,%1
+ lr\t%0,%1
+ l\t%0,%1
+ ly\t%0,%1
+ st\t%1,%0
+ sty\t%1,%0
+ ler\t%0,%1
+ le\t%0,%1
+ ley\t%0,%1
+ ste\t%1,%0
+ stey\t%1,%0
+ ear\t%0,%1
+ sar\t%0,%1
+ stam\t%1,%1,%S0
+ strl\t%1,%0
+ mvhi\t%0,%1
+ lam\t%0,%0,%S1"
+ [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RIL,RR,RX,RXY,RX,RXY,
+ RR,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS")
+ (set_attr "type" "*,
+ *,
+ *,
+ *,
+ la,
+ larl,
+ lr,
+ load,
+ load,
+ store,
+ store,
+ floadsf,
+ floadsf,
+ floadsf,
+ fstoresf,
+ fstoresf,
+ *,
+ *,
+ *,
+ larl,
+ *,
+ *")
+ (set_attr "cpu_facility" "*,*,*,extimm,longdisp,z10,*,*,longdisp,*,longdisp,
+ *,*,longdisp,*,longdisp,*,*,*,z10,z10,*")
+ (set_attr "z10prop" "z10_fwd_A1,
+ z10_fwd_E1,
+ z10_fwd_E1,
+ z10_fwd_A1,
+ z10_fwd_A1,
+ z10_fwd_A3,
+ z10_fr_E1,
+ z10_fwd_A3,
+ z10_fwd_A3,
+ z10_rec,
+ z10_rec,
+ *,
+ *,
+ *,
+ *,
+ *,
+ z10_super_E1,
+ z10_super,
+ *,
+ z10_rec,
+ z10_super,
+ *")])
+
+(define_insn "*movsi_esa"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t")
+ (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q"))]
+ "!TARGET_ZARCH"
+ "@
+ lhi\t%0,%h1
+ lr\t%0,%1
+ l\t%0,%1
+ st\t%1,%0
+ ler\t%0,%1
+ le\t%0,%1
+ ste\t%1,%0
+ ear\t%0,%1
+ sar\t%0,%1
+ stam\t%1,%1,%S0
+ lam\t%0,%0,%S1"
+ [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS")
+ (set_attr "type" "*,lr,load,store,floadsf,floadsf,fstoresf,*,*,*,*")
+ (set_attr "z10prop" "z10_fwd_A1,
+ z10_fr_E1,
+ z10_fwd_A3,
+ z10_rec,
+ *,
+ *,
+ *,
+ z10_super_E1,
+ z10_super,
+ *,
+ *")
+])
+
+(define_peephole2
+ [(set (match_operand:SI 0 "register_operand" "")
+ (mem:SI (match_operand 1 "address_operand" "")))]
+ "!FP_REG_P (operands[0])
+ && GET_CODE (operands[1]) == SYMBOL_REF
+ && CONSTANT_POOL_ADDRESS_P (operands[1])
+ && get_pool_mode (operands[1]) == SImode
+ && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
+ [(set (match_dup 0) (match_dup 2))]
+ "operands[2] = get_pool_constant (operands[1]);")
- /* During and after reload, we need to force constants
- to the literal pool ourselves, if necessary. */
- if ((reload_in_progress || reload_completed)
- && CONSTANT_P (operands[1])
- && (!legitimate_reload_constant_p (operands[1])
- || fp_operand (operands[0], VOIDmode)))
- operands[1] = force_const_mem (SImode, operands[1]);
-}")
+(define_insn "*la_31"
+ [(set (match_operand:SI 0 "register_operand" "=d,d")
+ (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))]
+ "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
+ "@
+ la\t%0,%a1
+ lay\t%0,%a1"
+ [(set_attr "op_type" "RX,RXY")
+ (set_attr "type" "la")
+ (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
-(define_insn "*movsi_lhi"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (match_operand:SI 1 "immediate_operand" "K"))]
- "GET_CODE (operands[1]) == CONST_INT
- && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K')
- && !fp_operand (operands[0], VOIDmode)"
- "lhi\\t%0,%h1"
- [(set_attr "op_type" "RI")])
+(define_peephole2
+ [(parallel
+ [(set (match_operand:SI 0 "register_operand" "")
+ (match_operand:QI 1 "address_operand" ""))
+ (clobber (reg:CC CC_REGNUM))])]
+ "!TARGET_64BIT
+ && preferred_la_operand_p (operands[1], const0_rtx)"
+ [(set (match_dup 0) (match_dup 1))]
+ "")
-(define_insn "*movsi_lli"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (match_operand:SI 1 "immediate_operand" "n"))]
- "TARGET_64BIT && s390_single_hi (operands[1], SImode, 0) >= 0
- && !fp_operand (operands[0], VOIDmode)"
- "*
-{
- int part = s390_single_hi (operands[1], SImode, 0);
- operands[1] = GEN_INT (s390_extract_hi (operands[1], SImode, part));
+(define_peephole2
+ [(set (match_operand:SI 0 "register_operand" "")
+ (match_operand:SI 1 "register_operand" ""))
+ (parallel
+ [(set (match_dup 0)
+ (plus:SI (match_dup 0)
+ (match_operand:SI 2 "nonmemory_operand" "")))
+ (clobber (reg:CC CC_REGNUM))])]
+ "!TARGET_64BIT
+ && !reg_overlap_mentioned_p (operands[0], operands[2])
+ && preferred_la_operand_p (operands[1], operands[2])"
+ [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
+ "")
- switch (part)
- {
- case 0: return \"llilh\\t%0,%x1\";
- case 1: return \"llill\\t%0,%x1\";
- default: abort ();
- }
-}"
- [(set_attr "op_type" "RI")])
+(define_insn "*la_31_and"
+ [(set (match_operand:SI 0 "register_operand" "=d,d")
+ (and:SI (match_operand:QI 1 "address_operand" "ZQZR,ZSZT")
+ (const_int 2147483647)))]
+ "!TARGET_64BIT"
+ "@
+ la\t%0,%a1
+ lay\t%0,%a1"
+ [(set_attr "op_type" "RX,RXY")
+ (set_attr "type" "la")
+ (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
-(define_insn "*movsi_ss"
- [(set (match_operand:SI 0 "s_operand" "=Qo")
- (match_operand:SI 1 "s_imm_operand" "Qo"))]
+(define_insn_and_split "*la_31_and_cc"
+ [(set (match_operand:SI 0 "register_operand" "=d")
+ (and:SI (match_operand:QI 1 "address_operand" "p")
+ (const_int 2147483647)))
+ (clobber (reg:CC CC_REGNUM))]
+ "!TARGET_64BIT"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0)
+ (and:SI (match_dup 1) (const_int 2147483647)))]
""
- "mvc\\t%O0(4,%R0),%1"
- [(set_attr "op_type" "SS")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "RX")
+ (set_attr "type" "la")])
-(define_insn "*movsi"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,m,!*f,!*f,!m")
- (match_operand:SI 1 "general_operand" "d,m,d,*f,m,*f"))]
- ""
+(define_insn "force_la_31"
+ [(set (match_operand:SI 0 "register_operand" "=d,d")
+ (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))
+ (use (const_int 0))]
+ "!TARGET_64BIT"
"@
- lr\\t%0,%1
- l\\t%0,%1
- st\\t%1,%0
- ler\\t%0,%1
- le\\t%0,%1
- ste\\t%1,%0"
- [(set_attr "op_type" "RR,RX,RX,RR,RX,RX")
- (set_attr "atype" "reg,mem,mem,reg,mem,mem")])
-
+ la\t%0,%a1
+ lay\t%0,%a1"
+ [(set_attr "op_type" "RX")
+ (set_attr "type" "la")
+ (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
;
; movhi instruction pattern(s).
;
-(define_insn "movhi"
- [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m")
- (match_operand:HI 1 "general_operand" "d,n,m,d"))]
+(define_expand "movhi"
+ [(set (match_operand:HI 0 "nonimmediate_operand" "")
+ (match_operand:HI 1 "general_operand" ""))]
""
- "@
- lr\\t%0,%1
- lhi\\t%0,%h1
- lh\\t%0,%1
- sth\\t%1,%0"
- [(set_attr "op_type" "RR,RI,RX,RX")
- (set_attr "atype" "reg,reg,mem,mem")])
+{
+ /* Make it explicit that loading a register from memory
+ always sign-extends (at least) to SImode. */
+ if (optimize && can_create_pseudo_p ()
+ && register_operand (operands[0], VOIDmode)
+ && GET_CODE (operands[1]) == MEM)
+ {
+ rtx tmp = gen_reg_rtx (SImode);
+ rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]);
+ emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
+ operands[1] = gen_lowpart (HImode, tmp);
+ }
+})
+(define_insn "*movhi"
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q")
+ (match_operand:HI 1 "general_operand" " d,n,R,T,b,d,d,d,K"))]
+ ""
+ "@
+ lr\t%0,%1
+ lhi\t%0,%h1
+ lh\t%0,%1
+ lhy\t%0,%1
+ lhrl\t%0,%1
+ sth\t%1,%0
+ sthy\t%1,%0
+ sthrl\t%1,%0
+ mvhhi\t%0,%1"
+ [(set_attr "op_type" "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL")
+ (set_attr "type" "lr,*,*,*,larl,store,store,store,*")
+ (set_attr "cpu_facility" "*,*,*,*,z10,*,*,z10,z10")
+ (set_attr "z10prop" "z10_fr_E1,
+ z10_fwd_A1,
+ z10_super_E1,
+ z10_super_E1,
+ z10_super_E1,
+ z10_rec,
+ z10_rec,
+ z10_rec,
+ z10_super")])
+
+(define_peephole2
+ [(set (match_operand:HI 0 "register_operand" "")
+ (mem:HI (match_operand 1 "address_operand" "")))]
+ "GET_CODE (operands[1]) == SYMBOL_REF
+ && CONSTANT_POOL_ADDRESS_P (operands[1])
+ && get_pool_mode (operands[1]) == HImode
+ && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
+ [(set (match_dup 0) (match_dup 2))]
+ "operands[2] = get_pool_constant (operands[1]);")
;
; movqi instruction pattern(s).
;
-(define_insn "movqi_64"
- [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,Q")
- (match_operand:QI 1 "general_operand" "d,n,m,d,n"))]
- "TARGET_64BIT"
- "@
- lr\\t%0,%1
- lhi\\t%0,%b1
- llgc\\t%0,%1
- stc\\t%1,%0
- mvi\\t%0,%b1"
- [(set_attr "op_type" "RR,RI,RXE,RX,SI")
- (set_attr "atype" "reg,reg,mem,mem,mem")])
-
+(define_expand "movqi"
+ [(set (match_operand:QI 0 "nonimmediate_operand" "")
+ (match_operand:QI 1 "general_operand" ""))]
+ ""
+{
+ /* On z/Architecture, zero-extending from memory to register
+ is just as fast as a QImode load. */
+ if (TARGET_ZARCH && optimize && can_create_pseudo_p ()
+ && register_operand (operands[0], VOIDmode)
+ && GET_CODE (operands[1]) == MEM)
+ {
+ rtx tmp = gen_reg_rtx (word_mode);
+ rtx ext = gen_rtx_ZERO_EXTEND (word_mode, operands[1]);
+ emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
+ operands[1] = gen_lowpart (QImode, tmp);
+ }
+})
-(define_insn "movqi"
- [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,Q")
- (match_operand:QI 1 "general_operand" "d,n,m,d,n"))]
+(define_insn "*movqi"
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S")
+ (match_operand:QI 1 "general_operand" "d,n,R,T,d,d,n,n"))]
""
"@
- lr\\t%0,%1
- lhi\\t%0,%b1
- ic\\t%0,%1
- stc\\t%1,%0
- mvi\\t%0,%b1"
- [(set_attr "op_type" "RR,RI,RX,RX,SI")
- (set_attr "atype" "reg,reg,mem,mem,mem")])
-
-
-;
-; moveqstrictqi instruction pattern(s).
+ lr\t%0,%1
+ lhi\t%0,%b1
+ ic\t%0,%1
+ icy\t%0,%1
+ stc\t%1,%0
+ stcy\t%1,%0
+ mvi\t%S0,%b1
+ mviy\t%S0,%b1"
+ [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY")
+ (set_attr "type" "lr,*,*,*,store,store,store,store")
+ (set_attr "z10prop" "z10_fr_E1,
+ z10_fwd_A1,
+ z10_super_E1,
+ z10_super_E1,
+ z10_rec,
+ z10_rec,
+ z10_super,
+ z10_super")])
+
+(define_peephole2
+ [(set (match_operand:QI 0 "nonimmediate_operand" "")
+ (mem:QI (match_operand 1 "address_operand" "")))]
+ "GET_CODE (operands[1]) == SYMBOL_REF
+ && CONSTANT_POOL_ADDRESS_P (operands[1])
+ && get_pool_mode (operands[1]) == QImode
+ && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
+ [(set (match_dup 0) (match_dup 2))]
+ "operands[2] = get_pool_constant (operands[1]);")
+
+;
+; movstrictqi instruction pattern(s).
;
(define_insn "*movstrictqi"
- [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
- (match_operand:QI 1 "memory_operand" "m"))]
+ [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d"))
+ (match_operand:QI 1 "memory_operand" "R,T"))]
""
- "ic\\t%0,%1"
- [(set_attr "op_type" "RX")
- (set_attr "atype" "mem")])
+ "@
+ ic\t%0,%1
+ icy\t%0,%1"
+ [(set_attr "op_type" "RX,RXY")
+ (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
;
; movstricthi instruction pattern(s).
;
(define_insn "*movstricthi"
- [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
- (match_operand:HI 1 "s_imm_operand" "Qo"))
- (clobber (reg:CC 33))]
+ [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d"))
+ (match_operand:HI 1 "memory_operand" "Q,S"))
+ (clobber (reg:CC CC_REGNUM))]
""
- "icm\\t%0,3,%1"
- [(set_attr "op_type" "RS")
- (set_attr "atype" "mem")])
-
+ "@
+ icm\t%0,3,%S1
+ icmy\t%0,3,%S1"
+ [(set_attr "op_type" "RS,RSY")
+ (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
;
; movstrictsi instruction pattern(s).
;
-(define_insn "movestrictsi"
- [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d"))
- (match_operand:SI 1 "general_operand" "d,m"))]
+(define_insn "movstrictsi"
+ [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d"))
+ (match_operand:SI 1 "general_operand" "d,R,T,t"))]
"TARGET_64BIT"
"@
- lr\\t%0,%1
- l\\t%0,%1"
- [(set_attr "op_type" "RR,RS")
- (set_attr "atype" "reg,mem")])
-
+ lr\t%0,%1
+ l\t%0,%1
+ ly\t%0,%1
+ ear\t%0,%1"
+ [(set_attr "op_type" "RR,RX,RXY,RRE")
+ (set_attr "type" "lr,load,load,*")
+ (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_super_E1")])
;
-; movdf instruction pattern(s).
+; mov(tf|td) instruction pattern(s).
;
-(define_expand "movdf"
- [(set (match_operand:DF 0 "nonimmediate_operand" "")
- (match_operand:DF 1 "general_operand" ""))]
+(define_expand "mov"
+ [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
+ (match_operand:TD_TF 1 "general_operand" ""))]
""
- "
-{
- /* During and after reload, we need to force constants
- to the literal pool ourselves, if necessary. */
- if ((reload_in_progress || reload_completed)
- && CONSTANT_P (operands[1]))
- operands[1] = force_const_mem (DFmode, operands[1]);
-}")
-
-(define_insn "*movdf_ss"
- [(set (match_operand:DF 0 "s_operand" "=Qo")
- (match_operand:DF 1 "s_imm_operand" "Qo"))]
+ "")
+
+(define_insn "*mov_64"
+ [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o, d,QS, d,o")
+ (match_operand:TD_TF 1 "general_operand" " G,f,o,f,QS, d,dRT,d"))]
+ "TARGET_64BIT"
+ "@
+ lzxr\t%0
+ lxr\t%0,%1
+ #
+ #
+ lmg\t%0,%N0,%S1
+ stmg\t%1,%N1,%S0
+ #
+ #"
+ [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*")
+ (set_attr "type" "fhex,fsimptf,*,*,lm,stm,*,*")])
+
+(define_insn "*mov_31"
+ [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o")
+ (match_operand:TD_TF 1 "general_operand" " G,f,o,f"))]
+ "!TARGET_64BIT"
+ "@
+ lzxr\t%0
+ lxr\t%0,%1
+ #
+ #"
+ [(set_attr "op_type" "RRE,RRE,*,*")
+ (set_attr "type" "fhex,fsimptf,*,*")])
+
+; TFmode in GPRs splitters
+
+(define_split
+ [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
+ (match_operand:TD_TF 1 "general_operand" ""))]
+ "TARGET_64BIT && reload_completed
+ && s390_split_ok_p (operands[0], operands[1], mode, 0)"
+ [(set (match_dup 2) (match_dup 4))
+ (set (match_dup 3) (match_dup 5))]
+{
+ operands[2] = operand_subword (operands[0], 0, 0, mode);
+ operands[3] = operand_subword (operands[0], 1, 0, mode);
+ operands[4] = operand_subword (operands[1], 0, 0, mode);
+ operands[5] = operand_subword (operands[1], 1, 0, mode);
+})
+
+(define_split
+ [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
+ (match_operand:TD_TF 1 "general_operand" ""))]
+ "TARGET_64BIT && reload_completed
+ && s390_split_ok_p (operands[0], operands[1], mode, 1)"
+ [(set (match_dup 2) (match_dup 4))
+ (set (match_dup 3) (match_dup 5))]
+{
+ operands[2] = operand_subword (operands[0], 1, 0, mode);
+ operands[3] = operand_subword (operands[0], 0, 0, mode);
+ operands[4] = operand_subword (operands[1], 1, 0, mode);
+ operands[5] = operand_subword (operands[1], 0, 0, mode);
+})
+
+(define_split
+ [(set (match_operand:TD_TF 0 "register_operand" "")
+ (match_operand:TD_TF 1 "memory_operand" ""))]
+ "TARGET_64BIT && reload_completed
+ && !FP_REG_P (operands[0])
+ && !s_operand (operands[1], VOIDmode)"
+ [(set (match_dup 0) (match_dup 1))]
+{
+ rtx addr = operand_subword (operands[0], 1, 0, mode);
+ s390_load_address (addr, XEXP (operands[1], 0));
+ operands[1] = replace_equiv_address (operands[1], addr);
+})
+
+; TFmode in BFPs splitters
+
+(define_split
+ [(set (match_operand:TD_TF 0 "register_operand" "")
+ (match_operand:TD_TF 1 "memory_operand" ""))]
+ "reload_completed && offsettable_memref_p (operands[1])
+ && FP_REG_P (operands[0])"
+ [(set (match_dup 2) (match_dup 4))
+ (set (match_dup 3) (match_dup 5))]
+{
+ operands[2] = simplify_gen_subreg (mode, operands[0],
+ mode, 0);
+ operands[3] = simplify_gen_subreg (mode, operands[0],
+ mode, 8);
+ operands[4] = adjust_address_nv (operands[1], mode, 0);
+ operands[5] = adjust_address_nv (operands[1], mode, 8);
+})
+
+(define_split
+ [(set (match_operand:TD_TF 0 "memory_operand" "")
+ (match_operand:TD_TF 1 "register_operand" ""))]
+ "reload_completed && offsettable_memref_p (operands[0])
+ && FP_REG_P (operands[1])"
+ [(set (match_dup 2) (match_dup 4))
+ (set (match_dup 3) (match_dup 5))]
+{
+ operands[2] = adjust_address_nv (operands[0], mode, 0);
+ operands[3] = adjust_address_nv (operands[0], mode, 8);
+ operands[4] = simplify_gen_subreg (mode, operands[1],
+ mode, 0);
+ operands[5] = simplify_gen_subreg (mode, operands[1],
+ mode, 8);
+})
+
+;
+; mov(df|dd) instruction pattern(s).
+;
+
+(define_expand "mov"
+ [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
+ (match_operand:DD_DF 1 "general_operand" ""))]
""
- "mvc\\t%O0(8,%R0),%1"
- [(set_attr "op_type" "SS")
- (set_attr "atype" "mem")])
+ "")
-(define_insn "*movdf_64"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,m,d,d,m")
- (match_operand:DF 1 "general_operand" "f,m,f,d,m,d"))]
+(define_insn "*mov_64dfp"
+ [(set (match_operand:DD_DF 0 "nonimmediate_operand"
+ "=f,f,f,d,f,f,R,T,d, d,RT")
+ (match_operand:DD_DF 1 "general_operand"
+ " G,f,d,f,R,T,f,f,d,RT, d"))]
+ "TARGET_64BIT && TARGET_DFP"
+ "@
+ lzdr\t%0
+ ldr\t%0,%1
+ ldgr\t%0,%1
+ lgdr\t%0,%1
+ ld\t%0,%1
+ ldy\t%0,%1
+ std\t%1,%0
+ stdy\t%1,%0
+ lgr\t%0,%1
+ lg\t%0,%1
+ stg\t%1,%0"
+ [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RRE,RXY,RXY")
+ (set_attr "type" "fhex,floaddf,floaddf,floaddf,floaddf,floaddf,
+ fstoredf,fstoredf,lr,load,store")
+ (set_attr "z10prop" "*,
+ *,
+ *,
+ *,
+ *,
+ *,
+ *,
+ *,
+ z10_fr_E1,
+ z10_fwd_A3,
+ z10_rec")
+])
+
+(define_insn "*mov_64"
+ [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d, d,RT")
+ (match_operand:DD_DF 1 "general_operand" "G,f,R,T,f,f,d,RT, d"))]
"TARGET_64BIT"
"@
- ldr\\t%0,%1
- ld\\t%0,%1
- std\\t%1,%0
- lgr\\t%0,%1
- lg\\t%0,%1
- stg\\t%1,%0"
- [(set_attr "op_type" "RR,RX,RX,RRE,RXE,RXE")
- (set_attr "atype" "reg,mem,mem,reg,mem,mem")])
-
-(define_insn "*movdf_31"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,m,d,Q,d,m")
- (match_operand:DF 1 "general_operand" "f,m,f,Q,d,dKm,d"))]
+ lzdr\t%0
+ ldr\t%0,%1
+ ld\t%0,%1
+ ldy\t%0,%1
+ std\t%1,%0
+ stdy\t%1,%0
+ lgr\t%0,%1
+ lg\t%0,%1
+ stg\t%1,%0"
+ [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RRE,RXY,RXY")
+ (set_attr "type" "fhex,fload,fload,fload,
+ fstore,fstore,lr,load,store")
+ (set_attr "z10prop" "*,
+ *,
+ *,
+ *,
+ *,
+ *,
+ z10_fr_E1,
+ z10_fwd_A3,
+ z10_rec")])
+
+(define_insn "*mov_31"
+ [(set (match_operand:DD_DF 0 "nonimmediate_operand"
+ "=f,f,f,f,R,T,d,d,Q,S, d,o")
+ (match_operand:DD_DF 1 "general_operand"
+ " G,f,R,T,f,f,Q,S,d,d,dPRT,d"))]
"!TARGET_64BIT"
"@
- ldr\\t%0,%1
- ld\\t%0,%1
- std\\t%1,%0
- lm\\t%0,%N0,%1
- stm\\t%1,%N1,%0
+ lzdr\t%0
+ ldr\t%0,%1
+ ld\t%0,%1
+ ldy\t%0,%1
+ std\t%1,%0
+ stdy\t%1,%0
+ lm\t%0,%N0,%S1
+ lmy\t%0,%N0,%S1
+ stm\t%1,%N1,%S0
+ stmy\t%1,%N1,%S0
#
#"
- [(set_attr "op_type" "RR,RX,RX,RS,RS,NN,NN")
- (set_attr "atype" "reg,mem,mem,mem,mem,*,*")])
+ [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*")
+ (set_attr "type" "fhex,fload,fload,fload,
+ fstore,fstore,lm,lm,stm,stm,*,*")])
+
+(define_split
+ [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
+ (match_operand:DD_DF 1 "general_operand" ""))]
+ "!TARGET_64BIT && reload_completed
+ && s390_split_ok_p (operands[0], operands[1], mode, 0)"
+ [(set (match_dup 2) (match_dup 4))
+ (set (match_dup 3) (match_dup 5))]
+{
+ operands[2] = operand_subword (operands[0], 0, 0, mode);
+ operands[3] = operand_subword (operands[0], 1, 0, mode);
+ operands[4] = operand_subword (operands[1], 0, 0, mode);
+ operands[5] = operand_subword (operands[1], 1, 0, mode);
+})
(define_split
- [(set (match_operand:DF 0 "nonimmediate_operand" "")
- (match_operand:DF 1 "general_operand" ""))]
+ [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
+ (match_operand:DD_DF 1 "general_operand" ""))]
"!TARGET_64BIT && reload_completed
- && !fp_operand (operands[0], VOIDmode)
- && !fp_operand (operands[1], VOIDmode)
- && !s_operand (operands[0], VOIDmode)
- && !s_operand (operands[1], VOIDmode)
- && (register_operand (operands[0], VOIDmode)
- || register_operand (operands[1], VOIDmode))
- && (!register_operand (operands[0], VOIDmode)
- || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DFmode),
- operands[1])
- || !reg_overlap_mentioned_p (operand_subword (operands[0], 1, 0, DFmode),
- operands[1]))"
+ && s390_split_ok_p (operands[0], operands[1], mode, 1)"
[(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 5))]
- "
{
- if (!register_operand (operands[0], VOIDmode)
- || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DFmode),
- operands[1]))
- {
- operands[2] = operand_subword (operands[0], 0, 0, DFmode);
- operands[3] = operand_subword (operands[0], 1, 0, DFmode);
- operands[4] = operand_subword (operands[1], 0, 0, DFmode);
- operands[5] = operand_subword (operands[1], 1, 0, DFmode);
- }
- else
- {
- operands[2] = operand_subword (operands[0], 1, 0, DFmode);
- operands[3] = operand_subword (operands[0], 0, 0, DFmode);
- operands[4] = operand_subword (operands[1], 1, 0, DFmode);
- operands[5] = operand_subword (operands[1], 0, 0, DFmode);
- }
-}")
+ operands[2] = operand_subword (operands[0], 1, 0, mode);
+ operands[3] = operand_subword (operands[0], 0, 0, mode);
+ operands[4] = operand_subword (operands[1], 1, 0, mode);
+ operands[5] = operand_subword (operands[1], 0, 0, mode);
+})
(define_split
- [(set (match_operand:DF 0 "register_operand" "")
- (match_operand:DF 1 "memory_operand" ""))]
+ [(set (match_operand:DD_DF 0 "register_operand" "")
+ (match_operand:DD_DF 1 "memory_operand" ""))]
"!TARGET_64BIT && reload_completed
- && !fp_operand (operands[0], VOIDmode)
- && !fp_operand (operands[1], VOIDmode)
+ && !FP_REG_P (operands[0])
&& !s_operand (operands[1], VOIDmode)"
- [(set (match_dup 2) (match_dup 3))
- (set (match_dup 0) (mem:DI (match_dup 2)))]
- "operands[2] = operand_subword (operands[0], 1, 0, DFmode);
- operands[3] = legitimize_la_operand (XEXP (operands[1], 0));")
+ [(set (match_dup 0) (match_dup 1))]
+{
+ rtx addr = operand_subword (operands[0], 1, 0, mode);
+ s390_load_address (addr, XEXP (operands[1], 0));
+ operands[1] = replace_equiv_address (operands[1], addr);
+})
;
-; movsf instruction pattern(s).
+; mov(sf|sd) instruction pattern(s).
;
-(define_expand "movsf"
- [(set (match_operand:SF 0 "nonimmediate_operand" "")
- (match_operand:SF 1 "general_operand" ""))]
+(define_insn "mov"
+ [(set (match_operand:SD_SF 0 "nonimmediate_operand"
+ "=f,f,f,f,R,T,d,d,d,R,T")
+ (match_operand:SD_SF 1 "general_operand"
+ " G,f,R,T,f,f,d,R,T,d,d"))]
""
- "
-{
- /* During and after reload, we need to force constants
- to the literal pool ourselves, if necessary. */
- if ((reload_in_progress || reload_completed)
- && CONSTANT_P (operands[1]))
- operands[1] = force_const_mem (SFmode, operands[1]);
-}")
-
-(define_insn "*movsf_ss"
- [(set (match_operand:SF 0 "s_operand" "=Qo")
- (match_operand:SF 1 "s_imm_operand" "Qo"))]
- ""
- "mvc\\t%O0(4,%R0),%1"
- [(set_attr "op_type" "SS")
- (set_attr "atype" "mem")])
-
-(define_insn "*movsf"
- [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,m,d,d,m")
- (match_operand:SF 1 "general_operand" "f,m,f,d,m,d"))]
+ "@
+ lzer\t%0
+ ler\t%0,%1
+ le\t%0,%1
+ ley\t%0,%1
+ ste\t%1,%0
+ stey\t%1,%0
+ lr\t%0,%1
+ l\t%0,%1
+ ly\t%0,%1
+ st\t%1,%0
+ sty\t%1,%0"
+ [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY")
+ (set_attr "type" "fhex,fload,fload,fload,
+ fstore,fstore,lr,load,load,store,store")
+ (set_attr "z10prop" "*,
+ *,
+ *,
+ *,
+ *,
+ *,
+ z10_fr_E1,
+ z10_fwd_A3,
+ z10_fwd_A3,
+ z10_rec,
+ z10_rec")])
+
+;
+; movcc instruction pattern
+;
+
+(define_insn "movcc"
+ [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T")
+ (match_operand:CC 1 "nonimmediate_operand" "d,d,c,R,T,d,d"))]
""
"@
- ler\\t%0,%1
- le\\t%0,%1
- ste\\t%1,%0
- lr\\t%0,%1
- l\\t%0,%1
- st\\t%1,%0"
- [(set_attr "op_type" "RR,RX,RX,RR,RX,RX")
- (set_attr "atype" "reg,mem,mem,reg,mem,mem")])
+ lr\t%0,%1
+ tmh\t%1,12288
+ ipm\t%0
+ st\t%0,%1
+ sty\t%0,%1
+ l\t%1,%0
+ ly\t%1,%0"
+ [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
+ (set_attr "type" "lr,*,*,store,store,load,load")
+ (set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_rec,z10_rec,z10_fwd_A3,z10_fwd_A3")])
+
+;
+; Block move (MVC) patterns.
+;
+
+(define_insn "*mvc"
+ [(set (match_operand:BLK 0 "memory_operand" "=Q")
+ (match_operand:BLK 1 "memory_operand" "Q"))
+ (use (match_operand 2 "const_int_operand" "n"))]
+ "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
+ "mvc\t%O0(%2,%R0),%S1"
+ [(set_attr "op_type" "SS")])
+
+(define_peephole2
+ [(parallel
+ [(set (match_operand:BLK 0 "memory_operand" "")
+ (match_operand:BLK 1 "memory_operand" ""))
+ (use (match_operand 2 "const_int_operand" ""))])
+ (parallel
+ [(set (match_operand:BLK 3 "memory_operand" "")
+ (match_operand:BLK 4 "memory_operand" ""))
+ (use (match_operand 5 "const_int_operand" ""))])]
+ "s390_offset_p (operands[0], operands[3], operands[2])
+ && s390_offset_p (operands[1], operands[4], operands[2])
+ && !s390_overlap_p (operands[0], operands[1],
+ INTVAL (operands[2]) + INTVAL (operands[5]))
+ && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
+ [(parallel
+ [(set (match_dup 6) (match_dup 7))
+ (use (match_dup 8))])]
+ "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
+ operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
+ operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
+
;
; load_multiple pattern(s).
;
+; ??? Due to reload problems with replacing registers inside match_parallel
+; we currently support load_multiple/store_multiple only after reload.
+;
(define_expand "load_multiple"
[(match_par_dup 3 [(set (match_operand 0 "" "")
(match_operand 1 "" ""))
(use (match_operand 2 "" ""))])]
- ""
- "
+ "reload_completed"
{
+ enum machine_mode mode;
int regno;
int count;
rtx from;
@@ -1374,9 +2315,12 @@
count = INTVAL (operands[2]);
regno = REGNO (operands[0]);
+ mode = GET_MODE (operands[0]);
+ if (mode != SImode && mode != word_mode)
+ FAIL;
operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
- if (no_new_pseudos)
+ if (!can_create_pseudo_p ())
{
if (GET_CODE (XEXP (operands[1], 0)) == REG)
{
@@ -1392,9 +2336,6 @@
}
else
FAIL;
-
- if (from == frame_pointer_rtx || from == arg_pointer_rtx)
- FAIL;
}
else
{
@@ -1404,61 +2345,48 @@
for (i = 0; i < count; i++)
XVECEXP (operands[3], 0, i)
- = gen_rtx_SET (VOIDmode, gen_rtx_REG (Pmode, regno + i),
- change_address (operands[1], Pmode,
- plus_constant (from,
- off + i * UNITS_PER_WORD)));
-}")
+ = gen_rtx_SET (VOIDmode, gen_rtx_REG (mode, regno + i),
+ change_address (operands[1], mode,
+ plus_constant (from, off + i * GET_MODE_SIZE (mode))));
+})
(define_insn "*load_multiple_di"
[(match_parallel 0 "load_multiple_operation"
[(set (match_operand:DI 1 "register_operand" "=r")
- (match_operand:DI 2 "s_operand" "oQ"))])]
- ""
- "*
+ (match_operand:DI 2 "s_operand" "QS"))])]
+ "reload_completed && word_mode == DImode"
{
int words = XVECLEN (operands[0], 0);
-
- if (XVECLEN (operands[0], 0) == 1)
- return \"lg\\t%1,0(%2)\";
-
operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
- return \"lmg\\t%1,%0,%2\";
-}"
- [(set_attr "op_type" "RXE")
- (set_attr "atype" "mem")
+ return "lmg\t%1,%0,%S2";
+}
+ [(set_attr "op_type" "RSY")
(set_attr "type" "lm")])
(define_insn "*load_multiple_si"
[(match_parallel 0 "load_multiple_operation"
- [(set (match_operand:SI 1 "register_operand" "=r")
- (match_operand:SI 2 "s_operand" "oQ"))])]
- ""
- "*
+ [(set (match_operand:SI 1 "register_operand" "=r,r")
+ (match_operand:SI 2 "s_operand" "Q,S"))])]
+ "reload_completed"
{
int words = XVECLEN (operands[0], 0);
-
- if (XVECLEN (operands[0], 0) == 1)
- return \"l\\t%1,0(%2)\";
-
operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
- return \"lm\\t%1,%0,%2\";
-}"
- [(set_attr "op_type" "RXE")
- (set_attr "atype" "mem")
+ return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2";
+}
+ [(set_attr "op_type" "RS,RSY")
(set_attr "type" "lm")])
;
-; store multiple pattern(s).
+; store multiple pattern(s).
;
(define_expand "store_multiple"
[(match_par_dup 3 [(set (match_operand 0 "" "")
(match_operand 1 "" ""))
(use (match_operand 2 "" ""))])]
- ""
- "
+ "reload_completed"
{
+ enum machine_mode mode;
int regno;
int count;
rtx to;
@@ -1476,10 +2404,13 @@
count = INTVAL (operands[2]);
regno = REGNO (operands[1]);
+ mode = GET_MODE (operands[1]);
+ if (mode != SImode && mode != word_mode)
+ FAIL;
operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
- if (no_new_pseudos)
+ if (!can_create_pseudo_p ())
{
if (GET_CODE (XEXP (operands[0], 0)) == REG)
{
@@ -1495,11 +2426,8 @@
}
else
FAIL;
-
- if (to == frame_pointer_rtx || to == arg_pointer_rtx)
- FAIL;
}
- else
+ else
{
to = force_reg (Pmode, XEXP (operands[0], 0));
off = 0;
@@ -1508,776 +2436,1027 @@
for (i = 0; i < count; i++)
XVECEXP (operands[3], 0, i)
= gen_rtx_SET (VOIDmode,
- change_address (operands[0], Pmode,
- plus_constant (to,
- off + i * UNITS_PER_WORD)),
- gen_rtx_REG (Pmode, regno + i));
-}")
+ change_address (operands[0], mode,
+ plus_constant (to, off + i * GET_MODE_SIZE (mode))),
+ gen_rtx_REG (mode, regno + i));
+})
(define_insn "*store_multiple_di"
[(match_parallel 0 "store_multiple_operation"
- [(set (match_operand:DI 1 "s_operand" "=oQ")
+ [(set (match_operand:DI 1 "s_operand" "=QS")
(match_operand:DI 2 "register_operand" "r"))])]
- ""
- "*
+ "reload_completed && word_mode == DImode"
{
int words = XVECLEN (operands[0], 0);
-
- if (XVECLEN (operands[0], 0) == 1)
- return \"stg\\t%1,0(%2)\";
-
operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
- return \"stmg\\t%2,%0,%1\";
-}"
- [(set_attr "op_type" "RXE")
- (set_attr "atype" "mem")
+ return "stmg\t%2,%0,%S1";
+}
+ [(set_attr "op_type" "RSY")
(set_attr "type" "stm")])
(define_insn "*store_multiple_si"
[(match_parallel 0 "store_multiple_operation"
- [(set (match_operand:SI 1 "s_operand" "=oQ")
- (match_operand:SI 2 "register_operand" "r"))])]
- ""
- "*
+ [(set (match_operand:SI 1 "s_operand" "=Q,S")
+ (match_operand:SI 2 "register_operand" "r,r"))])]
+ "reload_completed"
{
int words = XVECLEN (operands[0], 0);
-
- if (XVECLEN (operands[0], 0) == 1)
- return \"st\\t%1,0(%2)\";
-
operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
- return \"stm\\t%2,%0,%1\";
-}"
- [(set_attr "op_type" "RXE")
- (set_attr "atype" "mem")
+ return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1";
+}
+ [(set_attr "op_type" "RS,RSY")
(set_attr "type" "stm")])
;;
;; String instructions.
;;
-;
-; movstrdi instruction pattern(s).
-;
-
-(define_expand "movstrdi"
- [(set (match_operand:BLK 0 "general_operand" "")
- (match_operand:BLK 1 "general_operand" ""))
- (use (match_operand:DI 2 "general_operand" ""))
- (match_operand 3 "" "")]
- "TARGET_64BIT"
- "
-{
- rtx addr0, addr1;
-
- addr0 = force_operand (XEXP (operands[0], 0), NULL_RTX);
- addr1 = force_operand (XEXP (operands[1], 0), NULL_RTX);
-
- if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 256)
- {
- operands[0] = change_address (operands[0], VOIDmode, addr0);
- operands[1] = change_address (operands[1], VOIDmode, addr1);
- operands[2] = GEN_INT (INTVAL (operands[2]) - 1);
-
- emit_insn (gen_movstrdi_short (operands[0], operands[1], operands[2]));
- DONE;
- }
- else
- {
- if (TARGET_MVCLE)
- {
- /* implementation suggested by Richard Henderson */
- rtx reg0 = gen_reg_rtx (TImode);
- rtx reg1 = gen_reg_rtx (TImode);
- rtx len = operands[2];
-
- if (! CONSTANT_P (len))
- len = force_reg (DImode, len);
-
- /* Load up the address+length pairs. */
-
- emit_move_insn (gen_highpart (DImode, reg0), addr0);
- emit_move_insn (gen_lowpart (DImode, reg0), len);
+(define_insn "*execute_rl"
+ [(match_parallel 0 ""
+ [(unspec [(match_operand 1 "register_operand" "a")
+ (match_operand 2 "" "")
+ (match_operand:SI 3 "larl_operand" "X")] UNSPEC_EXECUTE)])]
+ "TARGET_Z10 && GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
+ && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
+ "exrl\t%1,%3"
+ [(set_attr "op_type" "RIL")
+ (set_attr "type" "cs")])
- emit_move_insn (gen_highpart (DImode, reg1), addr1);
- emit_move_insn (gen_lowpart (DImode, reg1), len);
+(define_insn "*execute"
+ [(match_parallel 0 ""
+ [(unspec [(match_operand 1 "register_operand" "a")
+ (match_operand:BLK 2 "memory_operand" "R")
+ (match_operand 3 "" "")] UNSPEC_EXECUTE)])]
+ "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
+ && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
+ "ex\t%1,%2"
+ [(set_attr "op_type" "RX")
+ (set_attr "type" "cs")])
- /* MOVE */
- emit_insn (gen_movstrdi_64 (reg0, reg1, reg0, reg1));
- DONE;
- }
- else
- {
- rtx label1 = gen_label_rtx ();
- rtx label2 = gen_label_rtx ();
- rtx reg0, reg1, len, blocks;
-
- reg0 = gen_reg_rtx (DImode);
- reg1 = gen_reg_rtx (DImode);
- len = gen_reg_rtx (DImode);
- blocks = gen_reg_rtx (DImode);
-
- emit_move_insn (len, operands[2]);
- emit_insn (gen_cmpdi (len, const0_rtx));
- emit_jump_insn (gen_beq (label1));
- emit_move_insn (reg0, addr0);
- emit_move_insn (reg1, addr1);
- emit_insn (gen_adddi3 (len, len, constm1_rtx));
- emit_insn (gen_ashrdi3 (blocks, len, GEN_INT (8)));
- emit_insn (gen_cmpdi (blocks, const0_rtx));
- emit_jump_insn (gen_beq (label2));
- emit_insn (gen_movstrdi_long (reg0, reg1, reg0, reg1, blocks, blocks));
- emit_label (label2);
- operands[0] = change_address (operands[0], VOIDmode, reg0);
- operands[1] = change_address (operands[1], VOIDmode, reg1);
- emit_insn (gen_movstrdi_short (operands[0], operands[1], len));
- emit_label (label1);
- DONE;
- }
- }
-}")
;
-; movstrsi instruction pattern(s).
+; strlenM instruction pattern(s).
;
-(define_expand "movstrsi"
- [(set (match_operand:BLK 0 "general_operand" "")
- (match_operand:BLK 1 "general_operand" ""))
- (use (match_operand:SI 2 "general_operand" ""))
- (match_operand 3 "" "")]
- "!TARGET_64BIT"
- "
+(define_expand "strlen"
+ [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" ""))
+ (parallel
+ [(set (match_dup 4)
+ (unspec:P [(const_int 0)
+ (match_operand:BLK 1 "memory_operand" "")
+ (reg:SI 0)
+ (match_operand 3 "immediate_operand" "")] UNSPEC_SRST))
+ (clobber (scratch:P))
+ (clobber (reg:CC CC_REGNUM))])
+ (parallel
+ [(set (match_operand:P 0 "register_operand" "")
+ (minus:P (match_dup 4) (match_dup 5)))
+ (clobber (reg:CC CC_REGNUM))])]
+ ""
{
- rtx addr0 = force_operand (XEXP (operands[0], 0), NULL_RTX);
- rtx addr1 = force_operand (XEXP (operands[1], 0), NULL_RTX);
+ operands[4] = gen_reg_rtx (Pmode);
+ operands[5] = gen_reg_rtx (Pmode);
+ emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX));
+ operands[1] = replace_equiv_address (operands[1], operands[5]);
+})
- if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 256)
- {
- operands[0] = change_address (operands[0], VOIDmode, addr0);
- operands[1] = change_address (operands[1], VOIDmode, addr1);
- operands[2] = GEN_INT (INTVAL (operands[2]) - 1);
+(define_insn "*strlen"
+ [(set (match_operand:P 0 "register_operand" "=a")
+ (unspec:P [(match_operand:P 2 "general_operand" "0")
+ (mem:BLK (match_operand:P 3 "register_operand" "1"))
+ (reg:SI 0)
+ (match_operand 4 "immediate_operand" "")] UNSPEC_SRST))
+ (clobber (match_scratch:P 1 "=a"))
+ (clobber (reg:CC CC_REGNUM))]
+ ""
+ "srst\t%0,%1\;jo\t.-4"
+ [(set_attr "length" "8")
+ (set_attr "type" "vs")])
- emit_insn (gen_movstrsi_short (operands[0], operands[1], operands[2]));
- DONE;
- }
- else
- {
- if (TARGET_MVCLE)
- {
- /* implementation suggested by Richard Henderson */
- rtx reg0 = gen_reg_rtx (DImode);
- rtx reg1 = gen_reg_rtx (DImode);
- rtx len = operands[2];
+;
+; cmpstrM instruction pattern(s).
+;
+(define_expand "cmpstrsi"
+ [(set (reg:SI 0) (const_int 0))
+ (parallel
+ [(clobber (match_operand 3 "" ""))
+ (clobber (match_dup 4))
+ (set (reg:CCU CC_REGNUM)
+ (compare:CCU (match_operand:BLK 1 "memory_operand" "")
+ (match_operand:BLK 2 "memory_operand" "")))
+ (use (reg:SI 0))])
+ (parallel
+ [(set (match_operand:SI 0 "register_operand" "=d")
+ (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_CCU_TO_INT))
+ (clobber (reg:CC CC_REGNUM))])]
+ ""
+{
+ /* As the result of CMPINT is inverted compared to what we need,
+ we have to swap the operands. */
+ rtx op1 = operands[2];
+ rtx op2 = operands[1];
+ rtx addr1 = gen_reg_rtx (Pmode);
+ rtx addr2 = gen_reg_rtx (Pmode);
+
+ emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
+ emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX));
+ operands[1] = replace_equiv_address_nv (op1, addr1);
+ operands[2] = replace_equiv_address_nv (op2, addr2);
+ operands[3] = addr1;
+ operands[4] = addr2;
+})
+
+(define_insn "*cmpstr"
+ [(clobber (match_operand:P 0 "register_operand" "=d"))
+ (clobber (match_operand:P 1 "register_operand" "=d"))
+ (set (reg:CCU CC_REGNUM)
+ (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0"))
+ (mem:BLK (match_operand:P 3 "register_operand" "1"))))
+ (use (reg:SI 0))]
+ ""
+ "clst\t%0,%1\;jo\t.-4"
+ [(set_attr "length" "8")
+ (set_attr "type" "vs")])
+
+;
+; movstr instruction pattern.
+;
+
+(define_expand "movstr"
+ [(set (reg:SI 0) (const_int 0))
+ (parallel
+ [(clobber (match_dup 3))
+ (set (match_operand:BLK 1 "memory_operand" "")
+ (match_operand:BLK 2 "memory_operand" ""))
+ (set (match_operand 0 "register_operand" "")
+ (unspec [(match_dup 1)
+ (match_dup 2)
+ (reg:SI 0)] UNSPEC_MVST))
+ (clobber (reg:CC CC_REGNUM))])]
+ ""
+{
+ rtx addr1 = gen_reg_rtx (Pmode);
+ rtx addr2 = gen_reg_rtx (Pmode);
- if (! CONSTANT_P (len))
- len = force_reg (SImode, len);
+ emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
+ emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX));
+ operands[1] = replace_equiv_address_nv (operands[1], addr1);
+ operands[2] = replace_equiv_address_nv (operands[2], addr2);
+ operands[3] = addr2;
+})
- /* Load up the address+length pairs. */
+(define_insn "*movstr"
+ [(clobber (match_operand:P 2 "register_operand" "=d"))
+ (set (mem:BLK (match_operand:P 1 "register_operand" "0"))
+ (mem:BLK (match_operand:P 3 "register_operand" "2")))
+ (set (match_operand:P 0 "register_operand" "=d")
+ (unspec [(mem:BLK (match_dup 1))
+ (mem:BLK (match_dup 3))
+ (reg:SI 0)] UNSPEC_MVST))
+ (clobber (reg:CC CC_REGNUM))]
+ ""
+ "mvst\t%1,%2\;jo\t.-4"
+ [(set_attr "length" "8")
+ (set_attr "type" "vs")])
- emit_move_insn (gen_highpart (SImode, reg0), addr0);
- emit_move_insn (gen_lowpart (SImode, reg0), len);
- emit_move_insn (gen_highpart (SImode, reg1), addr1);
- emit_move_insn (gen_lowpart (SImode, reg1), len);
+;
+; movmemM instruction pattern(s).
+;
- /* MOVE */
- emit_insn (gen_movstrsi_31 (reg0, reg1, reg0, reg1));
- DONE;
- }
- else
- {
- rtx label1 = gen_label_rtx ();
- rtx label2 = gen_label_rtx ();
- rtx reg0, reg1, len, blocks;
-
- reg0 = gen_reg_rtx (SImode);
- reg1 = gen_reg_rtx (SImode);
- len = gen_reg_rtx (SImode);
- blocks = gen_reg_rtx (SImode);
-
- emit_move_insn (len, operands[2]);
- emit_insn (gen_cmpsi (len, const0_rtx));
- emit_jump_insn (gen_beq (label1));
- emit_move_insn (reg0, addr0);
- emit_move_insn (reg1, addr1);
- emit_insn (gen_addsi3 (len, len, constm1_rtx));
- emit_insn (gen_ashrsi3 (blocks, len, GEN_INT (8)));
- emit_insn (gen_cmpsi (blocks, const0_rtx));
- emit_jump_insn (gen_beq (label2));
- emit_insn (gen_movstrsi_long (reg0, reg1, reg0, reg1, blocks, blocks));
- emit_label (label2);
- operands[0] = change_address (operands[0], VOIDmode, reg0);
- operands[1] = change_address (operands[1], VOIDmode, reg1);
- emit_insn (gen_movstrsi_short (operands[0], operands[1], len));
- emit_label (label1);
- DONE;
- }
- }
-}")
+(define_expand "movmem"
+ [(set (match_operand:BLK 0 "memory_operand" "") ; destination
+ (match_operand:BLK 1 "memory_operand" "")) ; source
+ (use (match_operand:GPR 2 "general_operand" "")) ; count
+ (match_operand 3 "" "")]
+ ""
+ "s390_expand_movmem (operands[0], operands[1], operands[2]); DONE;")
; Move a block that is up to 256 bytes in length.
; The block length is taken as (operands[2] % 256) + 1.
-(define_insn "movstrdi_short"
- [(set (match_operand:BLK 0 "s_operand" "=oQ,oQ")
- (match_operand:BLK 1 "s_operand" "oQ,oQ"))
- (use (match_operand:DI 2 "nonmemory_operand" "n,a"))
- (clobber (match_scratch:DI 3 "=X,&a"))]
- "TARGET_64BIT"
- "*
-{
- switch (which_alternative)
- {
- case 0:
- return \"mvc\\t%O0(%b2+1,%R0),%1\";
+(define_expand "movmem_short"
+ [(parallel
+ [(set (match_operand:BLK 0 "memory_operand" "")
+ (match_operand:BLK 1 "memory_operand" ""))
+ (use (match_operand 2 "nonmemory_operand" ""))
+ (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
+ (clobber (match_dup 3))])]
+ ""
+ "operands[3] = gen_rtx_SCRATCH (Pmode);")
+
+(define_insn "*movmem_short"
+ [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
+ (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q"))
+ (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
+ (use (match_operand 3 "immediate_operand" "X,R,X,X"))
+ (clobber (match_scratch 4 "=X,X,X,&a"))]
+ "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
+ && GET_MODE (operands[4]) == Pmode"
+ "#"
+ [(set_attr "type" "cs")
+ (set_attr "cpu_facility" "*,*,z10,*")])
- case 1:
- output_asm_insn (\"bras\\t%3,.+10\", operands);
- output_asm_insn (\"mvc\\t%O0(1,%R0),%1\", operands);
- return \"ex\\t%2,0(%3)\";
+(define_split
+ [(set (match_operand:BLK 0 "memory_operand" "")
+ (match_operand:BLK 1 "memory_operand" ""))
+ (use (match_operand 2 "const_int_operand" ""))
+ (use (match_operand 3 "immediate_operand" ""))
+ (clobber (scratch))]
+ "reload_completed"
+ [(parallel
+ [(set (match_dup 0) (match_dup 1))
+ (use (match_dup 2))])]
+ "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
- default:
- abort ();
- }
-}"
- [(set_attr "op_type" "SS,NN")
- (set_attr "atype" "mem,mem")
- (set_attr "length" "*,14")])
-
-(define_insn "movstrsi_short"
- [(set (match_operand:BLK 0 "s_operand" "=oQ,oQ")
- (match_operand:BLK 1 "s_operand" "oQ,oQ"))
- (use (match_operand:SI 2 "nonmemory_operand" "n,a"))
- (clobber (match_scratch:SI 3 "=X,&a"))]
- "!TARGET_64BIT"
- "*
-{
- switch (which_alternative)
- {
- case 0:
- return \"mvc\\t%O0(%b2+1,%R0),%1\";
+(define_split
+ [(set (match_operand:BLK 0 "memory_operand" "")
+ (match_operand:BLK 1 "memory_operand" ""))
+ (use (match_operand 2 "register_operand" ""))
+ (use (match_operand 3 "memory_operand" ""))
+ (clobber (scratch))]
+ "reload_completed"
+ [(parallel
+ [(unspec [(match_dup 2) (match_dup 3)
+ (const_int 0)] UNSPEC_EXECUTE)
+ (set (match_dup 0) (match_dup 1))
+ (use (const_int 1))])]
+ "")
- case 1:
- output_asm_insn (\"bras\\t%3,.+10\", operands);
- output_asm_insn (\"mvc\\t%O0(1,%R0),%1\", operands);
- return \"ex\\t%2,0(%3)\";
+(define_split
+ [(set (match_operand:BLK 0 "memory_operand" "")
+ (match_operand:BLK 1 "memory_operand" ""))
+ (use (match_operand 2 "register_operand" ""))
+ (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
+ (clobber (scratch))]
+ "TARGET_Z10 && reload_completed"
+ [(parallel
+ [(unspec [(match_dup 2) (const_int 0)
+ (label_ref (match_dup 3))] UNSPEC_EXECUTE)
+ (set (match_dup 0) (match_dup 1))
+ (use (const_int 1))])]
+ "operands[3] = gen_label_rtx ();")
- default:
- abort ();
- }
-}"
- [(set_attr "op_type" "SS,NN")
- (set_attr "atype" "mem,mem")
- (set_attr "length" "*,14")])
+(define_split
+ [(set (match_operand:BLK 0 "memory_operand" "")
+ (match_operand:BLK 1 "memory_operand" ""))
+ (use (match_operand 2 "register_operand" ""))
+ (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
+ (clobber (match_operand 3 "register_operand" ""))]
+ "reload_completed && TARGET_CPU_ZARCH"
+ [(set (match_dup 3) (label_ref (match_dup 4)))
+ (parallel
+ [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
+ (label_ref (match_dup 4))] UNSPEC_EXECUTE)
+ (set (match_dup 0) (match_dup 1))
+ (use (const_int 1))])]
+ "operands[4] = gen_label_rtx ();")
-; Move a block that is a multiple of 256 bytes in length
+; Move a block of arbitrary length.
-(define_insn "movstrdi_long"
- [(set (match_operand:DI 4 "register_operand" "=d")
- (const_int 0))
- (set (match_operand:DI 0 "register_operand" "=a")
- (plus:DI (match_operand:DI 2 "register_operand" "0")
- (ashift:DI (match_operand:DI 5 "register_operand" "4")
- (const_int 8))))
- (set (match_operand:DI 1 "register_operand" "=a")
- (plus:DI (match_operand:DI 3 "register_operand" "1")
- (ashift:DI (match_dup 5) (const_int 8))))
- (set (mem:BLK (match_dup 2))
- (mem:BLK (match_dup 3)))
- (use (match_dup 5))]
- "TARGET_64BIT"
- "*
-{
- output_asm_insn (\"mvc\\t0(256,%0),0(%1)\", operands);
- output_asm_insn (\"la\\t%0,256(%0)\", operands);
- output_asm_insn (\"la\\t%1,256(%1)\", operands);
- return \"brct\\t%4,.-14\";
-}"
- [(set_attr "op_type" "NN")
- (set_attr "atype" "mem")
- (set_attr "length" "18")])
-
-(define_insn "movstrsi_long"
- [(set (match_operand:SI 4 "register_operand" "=d")
- (const_int 0))
- (set (match_operand:SI 0 "register_operand" "=a")
- (plus:SI (match_operand:SI 2 "register_operand" "0")
- (ashift:SI (match_operand:SI 5 "register_operand" "4")
- (const_int 8))))
- (set (match_operand:SI 1 "register_operand" "=a")
- (plus:SI (match_operand:SI 3 "register_operand" "1")
- (ashift:SI (match_dup 5) (const_int 8))))
- (set (mem:BLK (match_dup 2))
- (mem:BLK (match_dup 3)))
- (use (match_dup 5))]
- "!TARGET_64BIT"
- "*
+(define_expand "movmem_long"
+ [(parallel
+ [(clobber (match_dup 2))
+ (clobber (match_dup 3))
+ (set (match_operand:BLK 0 "memory_operand" "")
+ (match_operand:BLK 1 "memory_operand" ""))
+ (use (match_operand 2 "general_operand" ""))
+ (use (match_dup 3))
+ (clobber (reg:CC CC_REGNUM))])]
+ ""
{
- output_asm_insn (\"mvc\\t0(256,%0),0(%1)\", operands);
- output_asm_insn (\"la\\t%0,256(%0)\", operands);
- output_asm_insn (\"la\\t%1,256(%1)\", operands);
- return \"brct\\t%4,.-14\";
-}"
- [(set_attr "op_type" "NN")
- (set_attr "atype" "mem")
- (set_attr "length" "18")])
-
-; Move a block that is larger than 255 bytes in length.
-
-(define_insn "movstrdi_64"
- [(set (match_operand:TI 0 "register_operand" "=d")
- (ashift:TI (plus:TI (match_operand:TI 2 "register_operand" "0")
- (lshiftrt:TI (match_dup 2) (const_int 64)))
- (const_int 64)))
- (set (match_operand:TI 1 "register_operand" "=d")
- (ashift:TI (plus:TI (match_operand:TI 3 "register_operand" "1")
- (lshiftrt:TI (match_dup 3) (const_int 64)))
- (const_int 64)))
- (set (mem:BLK (subreg:DI (match_dup 2) 0))
- (mem:BLK (subreg:DI (match_dup 3) 0)))
- (clobber (reg:CC 33))]
- "TARGET_64BIT"
- "mvcle\\t%0,%1,0\;jo\\t.-4"
- [(set_attr "op_type" "NN")
- (set_attr "atype" "mem")
- (set_attr "length" "8")])
-
-(define_insn "movstrsi_31"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (ashift:DI (plus:DI (match_operand:DI 2 "register_operand" "0")
- (lshiftrt:DI (match_dup 2) (const_int 32)))
- (const_int 32)))
- (set (match_operand:DI 1 "register_operand" "=d")
- (ashift:DI (plus:DI (match_operand:DI 3 "register_operand" "1")
- (lshiftrt:DI (match_dup 3) (const_int 32)))
- (const_int 32)))
- (set (mem:BLK (subreg:SI (match_dup 2) 0))
- (mem:BLK (subreg:SI (match_dup 3) 0)))
- (clobber (reg:CC 33))]
- "!TARGET_64BIT"
- "mvcle\\t%0,%1,0\;jo\\t.-4"
- [(set_attr "op_type" "NN")
- (set_attr "atype" "mem")
- (set_attr "length" "8")])
-
-;
-; clrstrdi instruction pattern(s).
-;
-
-(define_expand "clrstrdi"
- [(set (match_operand:BLK 0 "general_operand" "")
- (const_int 0))
- (use (match_operand:DI 1 "general_operand" ""))
- (match_operand 2 "" "")]
- "TARGET_64BIT"
- "
+ enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
+ rtx reg0 = gen_reg_rtx (dword_mode);
+ rtx reg1 = gen_reg_rtx (dword_mode);
+ rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
+ rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1));
+ rtx len0 = gen_lowpart (Pmode, reg0);
+ rtx len1 = gen_lowpart (Pmode, reg1);
+
+ emit_clobber (reg0);
+ emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
+ emit_move_insn (len0, operands[2]);
+
+ emit_clobber (reg1);
+ emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
+ emit_move_insn (len1, operands[2]);
+
+ operands[0] = replace_equiv_address_nv (operands[0], addr0);
+ operands[1] = replace_equiv_address_nv (operands[1], addr1);
+ operands[2] = reg0;
+ operands[3] = reg1;
+})
+
+(define_insn "*movmem_long"
+ [(clobber (match_operand: 0 "register_operand" "=d"))
+ (clobber (match_operand: 1 "register_operand" "=d"))
+ (set (mem:BLK (subreg:P (match_operand: 2 "register_operand" "0") 0))
+ (mem:BLK (subreg:P (match_operand: 3 "register_operand" "1") 0)))
+ (use (match_dup 2))
+ (use (match_dup 3))
+ (clobber (reg:CC CC_REGNUM))]
+ ""
+ "mvcle\t%0,%1,0\;jo\t.-4"
+ [(set_attr "length" "8")
+ (set_attr "type" "vs")])
+
+
+;
+; Test data class.
+;
+
+(define_expand "signbit2"
+ [(set (reg:CCZ CC_REGNUM)
+ (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
+ (match_dup 2)]
+ UNSPEC_TDC_INSN))
+ (set (match_operand:SI 0 "register_operand" "=d")
+ (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CCZ_TO_INT))]
+ "TARGET_HARD_FLOAT"
{
- rtx addr = force_operand (XEXP (operands[0], 0), NULL_RTX);
-
- operands[0] = change_address (operands[0], VOIDmode, addr);
-
- if (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) < 256)
- {
- emit_insn (gen_clrstrsico (operands[0], operands[1]));
- DONE;
- }
- else
- {
- rtx reg0 = gen_reg_rtx (TImode);
- rtx reg1 = gen_reg_rtx (TImode);
- rtx len = operands[1];
-
- if (! CONSTANT_P (len))
- len = force_reg (DImode, len);
-
- /* Load up the address+length pairs. */
+ operands[2] = GEN_INT (S390_TDC_SIGNBIT_SET);
+})
+
+(define_expand "isinf2"
+ [(set (reg:CCZ CC_REGNUM)
+ (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
+ (match_dup 2)]
+ UNSPEC_TDC_INSN))
+ (set (match_operand:SI 0 "register_operand" "=d")
+ (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CCZ_TO_INT))]
+ "TARGET_HARD_FLOAT"
+{
+ operands[2] = GEN_INT (S390_TDC_INFINITY);
+})
+
+; This insn is used to generate all variants of the Test Data Class
+; instruction, namely tcxb, tcdb, and tceb. The insn's first operand
+; is the register to be tested and the second one is the bit mask
+; specifying the required test(s).
+;
+(define_insn "*TDC_insn_"
+ [(set (reg:CCZ CC_REGNUM)
+ (unspec:CCZ [(match_operand:FP_ALL 0 "register_operand" "f")
+ (match_operand:SI 1 "const_int_operand")] UNSPEC_TDC_INSN))]
+ "TARGET_HARD_FLOAT"
+ "t<_d>c\t%0,%1"
+ [(set_attr "op_type" "RXE")
+ (set_attr "type" "fsimp")])
- emit_move_insn (gen_highpart (DImode, reg0), addr);
- emit_move_insn (gen_lowpart (DImode, reg0), len);
+(define_insn_and_split "*ccz_to_int"
+ [(set (match_operand:SI 0 "register_operand" "=d")
+ (unspec:SI [(match_operand:CCZ 1 "register_operand" "0")]
+ UNSPEC_CCZ_TO_INT))]
+ ""
+ "#"
+ "reload_completed"
+ [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 28)))])
- emit_move_insn (gen_lowpart (DImode, reg1), const0_rtx);
-
- /* Clear! */
- emit_insn (gen_clrstrsi_64 (reg0, reg1, reg0));
- DONE;
- }
-}")
;
-; clrstrsi instruction pattern(s).
+; setmemM instruction pattern(s).
;
-(define_expand "clrstrsi"
- [(set (match_operand:BLK 0 "general_operand" "")
- (const_int 0))
- (use (match_operand:SI 1 "general_operand" ""))
- (match_operand 2 "" "")]
- "!TARGET_64BIT"
- "
-{
- rtx addr = force_operand (XEXP (operands[0], 0), NULL_RTX);
-
- operands[0] = change_address (operands[0], VOIDmode, addr);
-
- if (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) < 256)
- {
- emit_insn (gen_clrstrsico (operands[0], operands[1]));
- DONE;
- }
- else
- {
- rtx reg0 = gen_reg_rtx (DImode);
- rtx reg1 = gen_reg_rtx (DImode);
- rtx len = operands[1];
-
- if (! CONSTANT_P (len))
- len = force_reg (SImode, len);
-
- /* Load up the address+length pairs. */
+(define_expand "setmem"
+ [(set (match_operand:BLK 0 "memory_operand" "")
+ (match_operand:QI 2 "general_operand" ""))
+ (use (match_operand:GPR 1 "general_operand" ""))
+ (match_operand 3 "" "")]
+ ""
+ "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;")
- emit_move_insn (gen_highpart (SImode, reg0), addr);
- emit_move_insn (gen_lowpart (SImode, reg0), len);
+; Clear a block that is up to 256 bytes in length.
+; The block length is taken as (operands[1] % 256) + 1.
- emit_move_insn (gen_lowpart (SImode, reg1), const0_rtx);
-
- /* CLear! */
- emit_insn (gen_clrstrsi_31 (reg0, reg1, reg0));
- DONE;
- }
-}")
+(define_expand "clrmem_short"
+ [(parallel
+ [(set (match_operand:BLK 0 "memory_operand" "")
+ (const_int 0))
+ (use (match_operand 1 "nonmemory_operand" ""))
+ (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
+ (clobber (match_dup 2))
+ (clobber (reg:CC CC_REGNUM))])]
+ ""
+ "operands[2] = gen_rtx_SCRATCH (Pmode);")
-; Clear memory with length less than 256 bytes
+(define_insn "*clrmem_short"
+ [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
+ (const_int 0))
+ (use (match_operand 1 "nonmemory_operand" "n,a,a,a"))
+ (use (match_operand 2 "immediate_operand" "X,R,X,X"))
+ (clobber (match_scratch 3 "=X,X,X,&a"))
+ (clobber (reg:CC CC_REGNUM))]
+ "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)
+ && GET_MODE (operands[3]) == Pmode"
+ "#"
+ [(set_attr "type" "cs")
+ (set_attr "cpu_facility" "*,*,z10,*")])
-(define_insn "clrstrsico"
- [(set (match_operand:BLK 0 "s_operand" "=Qo")
+(define_split
+ [(set (match_operand:BLK 0 "memory_operand" "")
(const_int 0))
- (use (match_operand 1 "immediate_operand" "I"))
- (clobber (reg:CC 33))]
- ""
- "xc\\t%O0(%1,%R0),%0"
- [(set_attr "op_type" "RS")
- (set_attr "type" "cs")
- (set_attr "atype" "mem")])
+ (use (match_operand 1 "const_int_operand" ""))
+ (use (match_operand 2 "immediate_operand" ""))
+ (clobber (scratch))
+ (clobber (reg:CC CC_REGNUM))]
+ "reload_completed"
+ [(parallel
+ [(set (match_dup 0) (const_int 0))
+ (use (match_dup 1))
+ (clobber (reg:CC CC_REGNUM))])]
+ "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);")
-; Clear memory with length greater 256 bytes or lenght not constant
+(define_split
+ [(set (match_operand:BLK 0 "memory_operand" "")
+ (const_int 0))
+ (use (match_operand 1 "register_operand" ""))
+ (use (match_operand 2 "memory_operand" ""))
+ (clobber (scratch))
+ (clobber (reg:CC CC_REGNUM))]
+ "reload_completed"
+ [(parallel
+ [(unspec [(match_dup 1) (match_dup 2)
+ (const_int 0)] UNSPEC_EXECUTE)
+ (set (match_dup 0) (const_int 0))
+ (use (const_int 1))
+ (clobber (reg:CC CC_REGNUM))])]
+ "")
-(define_insn "clrstrsi_64"
- [(set (match_operand:TI 0 "register_operand" "=d")
- (ashift:TI (plus:TI (match_operand:TI 2 "register_operand" "0")
- (lshiftrt:TI (match_dup 2) (const_int 64)))
- (const_int 64)))
- (set (mem:BLK (subreg:DI (match_dup 2) 0))
+(define_split
+ [(set (match_operand:BLK 0 "memory_operand" "")
(const_int 0))
- (use (match_operand:TI 1 "register_operand" "d"))
- (clobber (reg:CC 33))]
- "TARGET_64BIT"
- "mvcle\\t%0,%1,0\;jo\\t.-4"
- [(set_attr "op_type" "NN")
- (set_attr "atype" "mem")
- (set_attr "type" "vs")
- (set_attr "length" "8")])
+ (use (match_operand 1 "register_operand" ""))
+ (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
+ (clobber (scratch))
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_Z10 && reload_completed"
+ [(parallel
+ [(unspec [(match_dup 1) (const_int 0)
+ (label_ref (match_dup 3))] UNSPEC_EXECUTE)
+ (set (match_dup 0) (const_int 0))
+ (use (const_int 1))
+ (clobber (reg:CC CC_REGNUM))])]
+ "operands[3] = gen_label_rtx ();")
-(define_insn "clrstrsi_31"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (ashift:DI (plus:DI (match_operand:DI 2 "register_operand" "0")
- (lshiftrt:DI (match_dup 2) (const_int 32)))
- (const_int 32)))
- (set (mem:BLK (subreg:SI (match_dup 2) 0))
+(define_split
+ [(set (match_operand:BLK 0 "memory_operand" "")
(const_int 0))
- (use (match_operand:DI 1 "register_operand" "d"))
- (clobber (reg:CC 33))]
- "!TARGET_64BIT"
- "mvcle\\t%0,%1,0\;jo\\t.-4"
- [(set_attr "op_type" "NN")
- (set_attr "atype" "mem")
- (set_attr "type" "vs")
- (set_attr "length" "8")])
+ (use (match_operand 1 "register_operand" ""))
+ (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
+ (clobber (match_operand 2 "register_operand" ""))
+ (clobber (reg:CC CC_REGNUM))]
+ "reload_completed && TARGET_CPU_ZARCH"
+ [(set (match_dup 2) (label_ref (match_dup 3)))
+ (parallel
+ [(unspec [(match_dup 1) (mem:BLK (match_dup 2))
+ (label_ref (match_dup 3))] UNSPEC_EXECUTE)
+ (set (match_dup 0) (const_int 0))
+ (use (const_int 1))
+ (clobber (reg:CC CC_REGNUM))])]
+ "operands[3] = gen_label_rtx ();")
-;
-; cmpstrdi instruction pattern(s).
-;
+; Initialize a block of arbitrary length with (operands[2] % 256).
-(define_expand "cmpstrdi"
- [(set (match_operand:DI 0 "register_operand" "")
- (compare:DI (match_operand:BLK 1 "s_operand" "")
- (match_operand:BLK 2 "s_operand" "") ) )
- (use (match_operand:DI 3 "general_operand" ""))
- (use (match_operand:DI 4 "" ""))]
- "TARGET_64BIT"
- "
+(define_expand "setmem_long"
+ [(parallel
+ [(clobber (match_dup 1))
+ (set (match_operand:BLK 0 "memory_operand" "")
+ (match_operand 2 "shift_count_or_setmem_operand" ""))
+ (use (match_operand 1 "general_operand" ""))
+ (use (match_dup 3))
+ (clobber (reg:CC CC_REGNUM))])]
+ ""
{
- rtx addr0, addr1;
-
- /* for pre/post increment */
- operands[1] = protect_from_queue (operands[1], 0);
- operands[2] = protect_from_queue (operands[2], 0);
- operands[3] = protect_from_queue (operands[3], 0);
-
- addr0 = force_operand (XEXP (operands[1], 0), NULL_RTX);
- addr1 = force_operand (XEXP (operands[2], 0), NULL_RTX);
-
- if (GET_CODE (operands[3]) == CONST_INT && INTVAL (operands[3]) < 256)
- {
- if (INTVAL (operands[3]) == 0) {
- emit_move_insn (operands[0], operands[3]);
- DONE;
- }
+ enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
+ rtx reg0 = gen_reg_rtx (dword_mode);
+ rtx reg1 = gen_reg_rtx (dword_mode);
+ rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
+ rtx len0 = gen_lowpart (Pmode, reg0);
+
+ emit_clobber (reg0);
+ emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
+ emit_move_insn (len0, operands[1]);
+
+ emit_move_insn (reg1, const0_rtx);
+
+ operands[0] = replace_equiv_address_nv (operands[0], addr0);
+ operands[1] = reg0;
+ operands[3] = reg1;
+})
+
+(define_insn "*setmem_long"
+ [(clobber (match_operand: 0 "register_operand" "=d"))
+ (set (mem:BLK (subreg:P (match_operand: 3 "register_operand" "0") 0))
+ (match_operand 2 "shift_count_or_setmem_operand" "Y"))
+ (use (match_dup 3))
+ (use (match_operand: 1 "register_operand" "d"))
+ (clobber (reg:CC CC_REGNUM))]
+ ""
+ "mvcle\t%0,%1,%Y2\;jo\t.-4"
+ [(set_attr "length" "8")
+ (set_attr "type" "vs")])
+
+(define_insn "*setmem_long_and"
+ [(clobber (match_operand: 0 "register_operand" "=d"))
+ (set (mem:BLK (subreg:P (match_operand: 3 "register_operand" "0") 0))
+ (and (match_operand 2 "shift_count_or_setmem_operand" "Y")
+ (match_operand 4 "const_int_operand" "n")))
+ (use (match_dup 3))
+ (use (match_operand: 1 "register_operand" "d"))
+ (clobber (reg:CC CC_REGNUM))]
+ "(INTVAL (operands[4]) & 255) == 255"
+ "mvcle\t%0,%1,%Y2\;jo\t.-4"
+ [(set_attr "length" "8")
+ (set_attr "type" "vs")])
+;
+; cmpmemM instruction pattern(s).
+;
+
+(define_expand "cmpmemsi"
+ [(set (match_operand:SI 0 "register_operand" "")
+ (compare:SI (match_operand:BLK 1 "memory_operand" "")
+ (match_operand:BLK 2 "memory_operand" "") ) )
+ (use (match_operand:SI 3 "general_operand" ""))
+ (use (match_operand:SI 4 "" ""))]
+ ""
+ "s390_expand_cmpmem (operands[0], operands[1],
+ operands[2], operands[3]); DONE;")
- operands[1] = change_address (operands[1], VOIDmode, addr0);
- operands[2] = change_address (operands[2], VOIDmode, addr1);
+; Compare a block that is up to 256 bytes in length.
+; The block length is taken as (operands[2] % 256) + 1.
- emit_insn (gen_cmpstr_const (operands[1], operands[2], operands[3]));
- emit_insn (gen_cmpint_di (operands[0]));
- DONE;
- }
- else
- {
- /* implementation suggested by Richard Henderson */
- rtx reg0 = gen_reg_rtx (TImode);
- rtx reg1 = gen_reg_rtx (TImode);
- rtx len = operands[3];
+(define_expand "cmpmem_short"
+ [(parallel
+ [(set (reg:CCU CC_REGNUM)
+ (compare:CCU (match_operand:BLK 0 "memory_operand" "")
+ (match_operand:BLK 1 "memory_operand" "")))
+ (use (match_operand 2 "nonmemory_operand" ""))
+ (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
+ (clobber (match_dup 3))])]
+ ""
+ "operands[3] = gen_rtx_SCRATCH (Pmode);")
+
+(define_insn "*cmpmem_short"
+ [(set (reg:CCU CC_REGNUM)
+ (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q,Q")
+ (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q")))
+ (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
+ (use (match_operand 3 "immediate_operand" "X,R,X,X"))
+ (clobber (match_scratch 4 "=X,X,X,&a"))]
+ "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
+ && GET_MODE (operands[4]) == Pmode"
+ "#"
+ [(set_attr "type" "cs")
+ (set_attr "cpu_facility" "*,*,z10,*")])
- if (! CONSTANT_P (len))
- len = force_reg (DImode, len);
+(define_split
+ [(set (reg:CCU CC_REGNUM)
+ (compare:CCU (match_operand:BLK 0 "memory_operand" "")
+ (match_operand:BLK 1 "memory_operand" "")))
+ (use (match_operand 2 "const_int_operand" ""))
+ (use (match_operand 3 "immediate_operand" ""))
+ (clobber (scratch))]
+ "reload_completed"
+ [(parallel
+ [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
+ (use (match_dup 2))])]
+ "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
- /* Load up the address+length pairs. */
- emit_move_insn (gen_highpart (DImode, reg0), addr0);
- emit_move_insn (gen_lowpart (DImode, reg0), len);
+(define_split
+ [(set (reg:CCU CC_REGNUM)
+ (compare:CCU (match_operand:BLK 0 "memory_operand" "")
+ (match_operand:BLK 1 "memory_operand" "")))
+ (use (match_operand 2 "register_operand" ""))
+ (use (match_operand 3 "memory_operand" ""))
+ (clobber (scratch))]
+ "reload_completed"
+ [(parallel
+ [(unspec [(match_dup 2) (match_dup 3)
+ (const_int 0)] UNSPEC_EXECUTE)
+ (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
+ (use (const_int 1))])]
+ "")
- emit_move_insn (gen_highpart (DImode, reg1), addr1);
- emit_move_insn (gen_lowpart (DImode, reg1), len);
+(define_split
+ [(set (reg:CCU CC_REGNUM)
+ (compare:CCU (match_operand:BLK 0 "memory_operand" "")
+ (match_operand:BLK 1 "memory_operand" "")))
+ (use (match_operand 2 "register_operand" ""))
+ (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
+ (clobber (scratch))]
+ "TARGET_Z10 && reload_completed"
+ [(parallel
+ [(unspec [(match_dup 2) (const_int 0)
+ (label_ref (match_dup 4))] UNSPEC_EXECUTE)
+ (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
+ (use (const_int 1))])]
+ "operands[4] = gen_label_rtx ();")
- /* Compare! */
- emit_insn (gen_cmpstr_64 (reg0, reg1, reg0, reg1));
- emit_insn (gen_cmpint_di (operands[0]));
- DONE;
- }
-}")
+(define_split
+ [(set (reg:CCU CC_REGNUM)
+ (compare:CCU (match_operand:BLK 0 "memory_operand" "")
+ (match_operand:BLK 1 "memory_operand" "")))
+ (use (match_operand 2 "register_operand" ""))
+ (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
+ (clobber (match_operand 3 "register_operand" ""))]
+ "reload_completed && TARGET_CPU_ZARCH"
+ [(set (match_dup 3) (label_ref (match_dup 4)))
+ (parallel
+ [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
+ (label_ref (match_dup 4))] UNSPEC_EXECUTE)
+ (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
+ (use (const_int 1))])]
+ "operands[4] = gen_label_rtx ();")
-;
-; cmpstrsi instruction pattern(s).
-;
+; Compare a block of arbitrary length.
-(define_expand "cmpstrsi"
- [(set (match_operand:SI 0 "register_operand" "")
- (compare:SI (match_operand:BLK 1 "s_operand" "")
- (match_operand:BLK 2 "s_operand" "") ) )
- (use (match_operand:SI 3 "general_operand" ""))
- (use (match_operand:SI 4 "" ""))]
- ""
- "
+(define_expand "cmpmem_long"
+ [(parallel
+ [(clobber (match_dup 2))
+ (clobber (match_dup 3))
+ (set (reg:CCU CC_REGNUM)
+ (compare:CCU (match_operand:BLK 0 "memory_operand" "")
+ (match_operand:BLK 1 "memory_operand" "")))
+ (use (match_operand 2 "general_operand" ""))
+ (use (match_dup 3))])]
+ ""
{
- rtx addr0, addr1;
-
- /* for pre/post increment */
- operands[1] = protect_from_queue (operands[1], 0);
- operands[2] = protect_from_queue (operands[2], 0);
- operands[3] = protect_from_queue (operands[3], 0);
+ enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
+ rtx reg0 = gen_reg_rtx (dword_mode);
+ rtx reg1 = gen_reg_rtx (dword_mode);
+ rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
+ rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1));
+ rtx len0 = gen_lowpart (Pmode, reg0);
+ rtx len1 = gen_lowpart (Pmode, reg1);
+
+ emit_clobber (reg0);
+ emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
+ emit_move_insn (len0, operands[2]);
+
+ emit_clobber (reg1);
+ emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
+ emit_move_insn (len1, operands[2]);
+
+ operands[0] = replace_equiv_address_nv (operands[0], addr0);
+ operands[1] = replace_equiv_address_nv (operands[1], addr1);
+ operands[2] = reg0;
+ operands[3] = reg1;
+})
+
+(define_insn "*cmpmem_long"
+ [(clobber (match_operand: 0 "register_operand" "=d"))
+ (clobber (match_operand: 1 "register_operand" "=d"))
+ (set (reg:CCU CC_REGNUM)
+ (compare:CCU (mem:BLK (subreg:P (match_operand: 2 "register_operand" "0") 0))
+ (mem:BLK (subreg:P (match_operand: 3 "register_operand" "1") 0))))
+ (use (match_dup 2))
+ (use (match_dup 3))]
+ ""
+ "clcle\t%0,%1,0\;jo\t.-4"
+ [(set_attr "length" "8")
+ (set_attr "type" "vs")])
+
+; Convert CCUmode condition code to integer.
+; Result is zero if EQ, positive if LTU, negative if GTU.
+
+(define_insn_and_split "cmpint"
+ [(set (match_operand:SI 0 "register_operand" "=d")
+ (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
+ UNSPEC_CCU_TO_INT))
+ (clobber (reg:CC CC_REGNUM))]
+ ""
+ "#"
+ "reload_completed"
+ [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
+ (parallel
+ [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))
+ (clobber (reg:CC CC_REGNUM))])])
- addr0 = force_operand (XEXP (operands[1], 0), NULL_RTX);
- addr1 = force_operand (XEXP (operands[2], 0), NULL_RTX);
+(define_insn_and_split "*cmpint_cc"
+ [(set (reg CC_REGNUM)
+ (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
+ UNSPEC_CCU_TO_INT)
+ (const_int 0)))
+ (set (match_operand:SI 0 "register_operand" "=d")
+ (unspec:SI [(match_dup 1)] UNSPEC_CCU_TO_INT))]
+ "s390_match_ccmode (insn, CCSmode)"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
+ (parallel
+ [(set (match_dup 2) (match_dup 3))
+ (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])]
+{
+ rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30));
+ operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
+ operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
+})
- if (GET_CODE (operands[3]) == CONST_INT && INTVAL (operands[3]) < 256)
- {
- if (INTVAL (operands[3]) == 0) {
- emit_move_insn (operands[0], operands[3]);
- DONE;
- }
+(define_insn_and_split "*cmpint_sign"
+ [(set (match_operand:DI 0 "register_operand" "=d")
+ (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
+ UNSPEC_CCU_TO_INT)))
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_64BIT"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
+ (parallel
+ [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))
+ (clobber (reg:CC CC_REGNUM))])])
+
+(define_insn_and_split "*cmpint_sign_cc"
+ [(set (reg CC_REGNUM)
+ (compare (ashiftrt:DI (ashift:DI (subreg:DI
+ (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
+ UNSPEC_CCU_TO_INT) 0)
+ (const_int 32)) (const_int 32))
+ (const_int 0)))
+ (set (match_operand:DI 0 "register_operand" "=d")
+ (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_CCU_TO_INT)))]
+ "s390_match_ccmode (insn, CCSmode) && TARGET_64BIT"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
+ (parallel
+ [(set (match_dup 2) (match_dup 3))
+ (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])]
+{
+ rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62));
+ operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
+ operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
+})
- operands[1] = change_address (operands[1], VOIDmode, addr0);
- operands[2] = change_address (operands[2], VOIDmode, addr1);
- emit_insn (gen_cmpstr_const (operands[1], operands[2], operands[3]));
- emit_insn (gen_cmpint_si (operands[0]));
- DONE;
- }
- else
- {
- /* implementation suggested by Richard Henderson */
- rtx reg0, reg1;
- rtx len = operands[3];
+;;
+;;- Conversion instructions.
+;;
- if (TARGET_64BIT)
- {
- reg0 = gen_reg_rtx (TImode);
- reg1 = gen_reg_rtx (TImode);
- }
- else
- {
- reg0 = gen_reg_rtx (DImode);
- reg1 = gen_reg_rtx (DImode);
- }
+(define_insn "*sethighpartsi"
+ [(set (match_operand:SI 0 "register_operand" "=d,d")
+ (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S")
+ (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
+ (clobber (reg:CC CC_REGNUM))]
+ ""
+ "@
+ icm\t%0,%2,%S1
+ icmy\t%0,%2,%S1"
+ [(set_attr "op_type" "RS,RSY")
+ (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
- /* Load up the address+length pairs. */
- emit_move_insn (gen_highpart (Pmode, reg0), addr0);
- convert_move (gen_lowpart (Pmode, reg0), len, 1);
+(define_insn "*sethighpartdi_64"
+ [(set (match_operand:DI 0 "register_operand" "=d")
+ (unspec:DI [(match_operand:BLK 1 "s_operand" "QS")
+ (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM))
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_64BIT"
+ "icmh\t%0,%2,%S1"
+ [(set_attr "op_type" "RSY")
+ (set_attr "z10prop" "z10_super")])
- emit_move_insn (gen_highpart (Pmode, reg1), addr1);
- convert_move (gen_lowpart (Pmode, reg1), len, 1);
+(define_insn "*sethighpartdi_31"
+ [(set (match_operand:DI 0 "register_operand" "=d,d")
+ (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S")
+ (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
+ (clobber (reg:CC CC_REGNUM))]
+ "!TARGET_64BIT"
+ "@
+ icm\t%0,%2,%S1
+ icmy\t%0,%2,%S1"
+ [(set_attr "op_type" "RS,RSY")
+ (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
+
+
+(define_insn_and_split "*extzv"
+ [(set (match_operand:GPR 0 "register_operand" "=d")
+ (zero_extract:GPR (match_operand:QI 1 "s_operand" "QS")
+ (match_operand 2 "const_int_operand" "n")
+ (const_int 0)))
+ (clobber (reg:CC CC_REGNUM))]
+ "INTVAL (operands[2]) > 0
+ && INTVAL (operands[2]) <= GET_MODE_BITSIZE (SImode)"
+ "#"
+ "&& reload_completed"
+ [(parallel
+ [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
+ (clobber (reg:CC CC_REGNUM))])
+ (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))]
+{
+ int bitsize = INTVAL (operands[2]);
+ int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
+ int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
+
+ operands[1] = adjust_address (operands[1], BLKmode, 0);
+ set_mem_size (operands[1], GEN_INT (size));
+ operands[2] = GEN_INT (GET_MODE_BITSIZE (mode) - bitsize);
+ operands[3] = GEN_INT (mask);
+})
+
+(define_insn_and_split "*extv"
+ [(set (match_operand:GPR 0 "register_operand" "=d")
+ (sign_extract:GPR (match_operand:QI 1 "s_operand" "QS")
+ (match_operand 2 "const_int_operand" "n")
+ (const_int 0)))
+ (clobber (reg:CC CC_REGNUM))]
+ "INTVAL (operands[2]) > 0
+ && INTVAL (operands[2]) <= GET_MODE_BITSIZE (SImode)"
+ "#"
+ "&& reload_completed"
+ [(parallel
+ [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
+ (clobber (reg:CC CC_REGNUM))])
+ (parallel
+ [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
+ (clobber (reg:CC CC_REGNUM))])]
+{
+ int bitsize = INTVAL (operands[2]);
+ int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
+ int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
- /* Compare! */
- if (TARGET_64BIT)
- emit_insn (gen_cmpstr_64 (reg0, reg1, reg0, reg1));
- else
- emit_insn (gen_cmpstr_31 (reg0, reg1, reg0, reg1));
+ operands[1] = adjust_address (operands[1], BLKmode, 0);
+ set_mem_size (operands[1], GEN_INT (size));
+ operands[2] = GEN_INT (GET_MODE_BITSIZE (mode) - bitsize);
+ operands[3] = GEN_INT (mask);
+})
- emit_insn (gen_cmpint_si (operands[0]));
- DONE;
- }
-}")
-
-; Compare a block that is less than 256 bytes in length.
-
-(define_insn "cmpstr_const"
- [(set (reg:CCS 33)
- (compare:CCS (match_operand:BLK 0 "s_operand" "oQ")
- (match_operand:BLK 1 "s_operand" "oQ")))
- (use (match_operand 2 "immediate_operand" "I"))]
- "(unsigned) INTVAL (operands[2]) < 256"
- "clc\\t%O0(%c2,%R0),%1"
- [(set_attr "op_type" "SS")
- (set_attr "atype" "mem")
- (set_attr "type" "cs")])
+;
+; insv instruction patterns
+;
-; Compare a block that is larger than 255 bytes in length.
+(define_expand "insv"
+ [(set (zero_extract (match_operand 0 "nonimmediate_operand" "")
+ (match_operand 1 "const_int_operand" "")
+ (match_operand 2 "const_int_operand" ""))
+ (match_operand 3 "general_operand" ""))]
+ ""
+{
+ if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3]))
+ DONE;
+ FAIL;
+})
+
+(define_insn "*insv_z10"
+ [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
+ (match_operand 1 "const_int_operand" "I")
+ (match_operand 2 "const_int_operand" "I"))
+ (match_operand:GPR 3 "nonimmediate_operand" "d"))
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_Z10
+ && (INTVAL (operands[1]) + INTVAL (operands[2])) <=
+ GET_MODE_BITSIZE (mode)"
+{
+ int start = INTVAL (operands[2]);
+ int size = INTVAL (operands[1]);
+ int offset = 64 - GET_MODE_BITSIZE (mode);
-(define_insn "cmpstr_64"
- [(clobber (match_operand:TI 0 "register_operand" "=d"))
- (clobber (match_operand:TI 1 "register_operand" "=d"))
- (set (reg:CCS 33)
- (compare:CCS (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0))
- (mem:BLK (subreg:DI (match_operand:TI 3 "register_operand" "1") 0))))]
- "TARGET_64BIT"
- "clcl\\t%0,%1"
- [(set_attr "op_type" "RR")
- (set_attr "atype" "mem")
- (set_attr "type" "vs")])
-
-(define_insn "cmpstr_31"
- [(clobber (match_operand:DI 0 "register_operand" "=d"))
- (clobber (match_operand:DI 1 "register_operand" "=d"))
- (set (reg:CCS 33)
- (compare:CCS (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0))
- (mem:BLK (subreg:SI (match_operand:DI 3 "register_operand" "1") 0))))]
- "!TARGET_64BIT"
- "clcl\\t%0,%1"
- [(set_attr "op_type" "RR")
- (set_attr "atype" "mem")
- (set_attr "type" "vs")])
+ operands[2] = GEN_INT (offset + start); /* start bit position */
+ operands[1] = GEN_INT (offset + start + size - 1); /* end bit position */
+ operands[4] = GEN_INT (GET_MODE_BITSIZE (mode) -
+ start - size); /* left shift count */
-; Convert condition code to integer in range (-1, 0, 1)
+ return "risbg\t%0,%3,%b2,%b1,%b4";
+}
+ [(set_attr "op_type" "RIE")
+ (set_attr "z10prop" "z10_super_E1")])
+
+; and op1 with a mask being 1 for the selected bits and 0 for the rest
+; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest
+(define_insn "*insv_z10_noshift"
+ [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
+ (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
+ (match_operand 2 "const_int_operand" "n"))
+ (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0")
+ (match_operand 4 "const_int_operand" "n"))))
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_Z10
+ && s390_contiguous_bitmask_p (INTVAL (operands[2]),
+ GET_MODE_BITSIZE (mode), NULL, NULL)
+ && INTVAL (operands[2]) == ~(INTVAL (operands[4]))"
-(define_insn "cmpint_si"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (compare:SI (reg:CCS 33) (const_int 0)))]
- ""
- "*
-{
- output_asm_insn (\"lhi\\t%0,1\", operands);
- output_asm_insn (\"jh\\t.+12\", operands);
- output_asm_insn (\"jl\\t.+6\", operands);
- output_asm_insn (\"sr\\t%0,%0\", operands);
- return \"lcr\\t%0,%0\";
-}"
- [(set_attr "op_type" "NN")
- (set_attr "length" "16")
- (set_attr "atype" "reg")
- (set_attr "type" "other")])
-
-(define_insn "cmpint_di"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (compare:DI (reg:CCS 33) (const_int 0)))]
- "TARGET_64BIT"
- "*
{
- output_asm_insn (\"lghi\\t%0,1\", operands);
- output_asm_insn (\"jh\\t.+12\", operands);
- output_asm_insn (\"jl\\t.+6\", operands);
- output_asm_insn (\"sgr\\t%0,%0\", operands);
- return \"lcgr\\t%0,%0\";
-}"
- [(set_attr "op_type" "NN")
- (set_attr "length" "22")
- (set_attr "atype" "reg")
- (set_attr "type" "other")])
+ int start;
+ int size;
+ s390_contiguous_bitmask_p (INTVAL (operands[2]),
+ GET_MODE_BITSIZE (mode), &start, &size);
-;;
-;;- Conversion instructions.
-;;
+ operands[5] = GEN_INT (64 - start - size); /* start bit position */
+ operands[6] = GEN_INT (64 - 1 - start); /* end bit position */
+ operands[7] = const0_rtx; /* left shift count */
-(define_insn "*sethighqisi"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (unspec:SI [(match_operand:QI 1 "s_operand" "Qo")] 10))
- (clobber (reg:CC 33))]
- ""
- "icm\\t%0,8,%1"
- [(set_attr "op_type" "RS")
- (set_attr "atype" "mem")])
+ return "risbg\t%0,%1,%b5,%b6,%b7";
+}
+ [(set_attr "op_type" "RIE")
+ (set_attr "z10prop" "z10_super_E1")])
+
+; and op1 with a mask being 1 for the selected bits and 0 for the rest
+(define_insn "*insv_or_z10_noshift"
+ [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
+ (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
+ (match_operand 2 "const_int_operand" "n"))
+ (match_operand:GPR 3 "nonimmediate_operand" "0")))
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_Z10
+ && s390_contiguous_bitmask_p (INTVAL (operands[2]),
+ GET_MODE_BITSIZE (mode), NULL, NULL)"
+{
+ int start;
+ int size;
-(define_insn "*sethighhisi"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (unspec:SI [(match_operand:HI 1 "s_operand" "Qo")] 10))
- (clobber (reg:CC 33))]
- ""
- "icm\\t%0,12,%1"
- [(set_attr "op_type" "RS")
- (set_attr "atype" "mem")])
+ s390_contiguous_bitmask_p (INTVAL (operands[2]),
+ GET_MODE_BITSIZE (mode), &start, &size);
-(define_insn "*sethighqidi_64"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (unspec:DI [(match_operand:QI 1 "s_operand" "Qo")] 10))
- (clobber (reg:CC 33))]
- "TARGET_64BIT"
- "icmh\\t%0,8,%1"
- [(set_attr "op_type" "RSE")
- (set_attr "atype" "mem")])
+ operands[4] = GEN_INT (64 - start - size); /* start bit position */
+ operands[5] = GEN_INT (64 - 1 - start); /* end bit position */
+ operands[6] = const0_rtx; /* left shift count */
-(define_insn "*sethighqidi_31"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (unspec:DI [(match_operand:QI 1 "s_operand" "Qo")] 10))
- (clobber (reg:CC 33))]
- "!TARGET_64BIT"
- "icm\\t%0,8,%1"
- [(set_attr "op_type" "RS")
- (set_attr "atype" "mem")])
+ return "rosbg\t%0,%1,%b4,%b5,%b6";
+}
+ [(set_attr "op_type" "RIE")])
+
+(define_insn "*insv_mem_reg"
+ [(set (zero_extract:P (match_operand:QI 0 "memory_operand" "+Q,S")
+ (match_operand 1 "const_int_operand" "n,n")
+ (const_int 0))
+ (match_operand:P 2 "register_operand" "d,d"))]
+ "INTVAL (operands[1]) > 0
+ && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
+ && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
+{
+ int size = INTVAL (operands[1]) / BITS_PER_UNIT;
-(define_split
- [(set (match_operand:SI 0 "register_operand" "")
- (zero_extract:SI (match_operand:QI 1 "s_operand" "")
- (match_operand 2 "const_int_operand" "")
- (const_int 0)))]
- "!TARGET_64BIT && !reload_completed
- && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 8"
- [(parallel
- [(set (match_dup 0) (unspec:SI [(match_dup 1)] 10))
- (clobber (reg:CC 33))])
- (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
- "
+ operands[1] = GEN_INT ((1ul << size) - 1);
+ return (which_alternative == 0) ? "stcm\t%2,%1,%S0"
+ : "stcmy\t%2,%1,%S0";
+}
+ [(set_attr "op_type" "RS,RSY")
+ (set_attr "z10prop" "z10_super,z10_super")])
+
+(define_insn "*insvdi_mem_reghigh"
+ [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+QS")
+ (match_operand 1 "const_int_operand" "n")
+ (const_int 0))
+ (lshiftrt:DI (match_operand:DI 2 "register_operand" "d")
+ (const_int 32)))]
+ "TARGET_64BIT
+ && INTVAL (operands[1]) > 0
+ && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
+ && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
{
- operands[2] = GEN_INT (32 - INTVAL (operands[2]));
- operands[1] = change_address (operands[1], QImode, 0);
-}")
+ int size = INTVAL (operands[1]) / BITS_PER_UNIT;
-(define_split
- [(set (match_operand:SI 0 "register_operand" "")
- (zero_extract:SI (match_operand:QI 1 "s_operand" "")
- (match_operand 2 "const_int_operand" "")
- (const_int 0)))]
- "!TARGET_64BIT && !reload_completed
- && INTVAL (operands[2]) >= 8 && INTVAL (operands[2]) < 16"
- [(parallel
- [(set (match_dup 0) (unspec:SI [(match_dup 1)] 10))
- (clobber (reg:CC 33))])
- (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
- "
+ operands[1] = GEN_INT ((1ul << size) - 1);
+ return "stcmh\t%2,%1,%S0";
+}
+[(set_attr "op_type" "RSY")
+ (set_attr "z10prop" "z10_super")])
+
+(define_insn "*insv_reg_imm"
+ [(set (zero_extract:P (match_operand:P 0 "register_operand" "+d")
+ (const_int 16)
+ (match_operand 1 "const_int_operand" "n"))
+ (match_operand:P 2 "const_int_operand" "n"))]
+ "TARGET_ZARCH
+ && INTVAL (operands[1]) >= 0
+ && INTVAL (operands[1]) < BITS_PER_WORD
+ && INTVAL (operands[1]) % 16 == 0"
{
- operands[2] = GEN_INT (32 - INTVAL (operands[2]));
- operands[1] = change_address (operands[1], HImode, 0);
-}")
+ switch (BITS_PER_WORD - INTVAL (operands[1]))
+ {
+ case 64: return "iihh\t%0,%x2"; break;
+ case 48: return "iihl\t%0,%x2"; break;
+ case 32: return "iilh\t%0,%x2"; break;
+ case 16: return "iill\t%0,%x2"; break;
+ default: gcc_unreachable();
+ }
+}
+ [(set_attr "op_type" "RI")
+ (set_attr "z10prop" "z10_super_E1")])
+
+; Update the left-most 32 bit of a DI.
+(define_insn "*insv_h_di_reg_extimm"
+ [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
+ (const_int 32)
+ (const_int 0))
+ (match_operand:DI 1 "const_int_operand" "n"))]
+ "TARGET_EXTIMM"
+ "iihf\t%0,%o1"
+ [(set_attr "op_type" "RIL")
+ (set_attr "z10prop" "z10_fwd_E1")])
+
+; Update the right-most 32 bit of a DI, or the whole of a SI.
+(define_insn "*insv_l_reg_extimm"
+ [(set (zero_extract:P (match_operand:P 0 "register_operand" "+d")
+ (const_int 32)
+ (match_operand 1 "const_int_operand" "n"))
+ (match_operand:P 2 "const_int_operand" "n"))]
+ "TARGET_EXTIMM
+ && BITS_PER_WORD - INTVAL (operands[1]) == 32"
+ "iilf\t%0,%o2"
+ [(set_attr "op_type" "RIL")
+ (set_attr "z10prop" "z10_fwd_A1")])
;
; extendsidi2 instruction pattern(s).
@@ -2287,161 +3466,154 @@
[(set (match_operand:DI 0 "register_operand" "")
(sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
""
- "
{
if (!TARGET_64BIT)
{
- emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
+ emit_clobber (operands[0]);
emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
DONE;
}
-}
-")
+})
(define_insn "*extendsidi2"
- [(set (match_operand:DI 0 "register_operand" "=d,d")
- (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
+ [(set (match_operand:DI 0 "register_operand" "=d,d,d")
+ (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
"TARGET_64BIT"
"@
- lgfr\\t%0,%1
- lgf\\t%0,%1"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "atype" "reg,mem")])
+ lgfr\t%0,%1
+ lgf\t%0,%1
+ lgfrl\t%0,%1"
+ [(set_attr "op_type" "RRE,RXY,RIL")
+ (set_attr "type" "*,*,larl")
+ (set_attr "cpu_facility" "*,*,z10")
+ (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
;
-; extendhidi2 instruction pattern(s).
+; extend(hi|qi)(si|di)2 instruction pattern(s).
;
-(define_expand "extendhidi2"
- [(set (match_operand:DI 0 "register_operand" "")
- (sign_extend:DI (match_operand:HI 1 "register_operand" "")))]
+(define_expand "extend2"
+ [(set (match_operand:DSI 0 "register_operand" "")
+ (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))]
""
- "
{
- if (!TARGET_64BIT)
+ if (mode == DImode && !TARGET_64BIT)
{
rtx tmp = gen_reg_rtx (SImode);
- emit_insn (gen_extendhisi2 (tmp, operands[1]));
+ emit_insn (gen_extendsi2 (tmp, operands[1]));
emit_insn (gen_extendsidi2 (operands[0], tmp));
DONE;
}
- else
+ else if (!TARGET_EXTIMM)
{
- operands[1] = gen_lowpart (DImode, operands[1]);
- emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48)));
- emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (48)));
+ rtx bitcount = GEN_INT (GET_MODE_BITSIZE (mode) -
+ GET_MODE_BITSIZE (mode));
+
+ operands[1] = gen_lowpart (mode, operands[1]);
+ emit_insn (gen_ashl3 (operands[0], operands[1], bitcount));
+ emit_insn (gen_ashr3 (operands[0], operands[0], bitcount));
DONE;
}
-}
-")
-
-(define_insn "*extendhidi2"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
- "TARGET_64BIT"
- "lgh\\t%0,%1"
- [(set_attr "op_type" "RXE")
- (set_attr "atype" "mem")])
+})
;
-; extendqidi2 instruction pattern(s).
+; extendhidi2 instruction pattern(s).
;
-(define_expand "extendqidi2"
- [(set (match_operand:DI 0 "register_operand" "")
- (sign_extend:DI (match_operand:QI 1 "register_operand" "")))]
- ""
- "
-{
- if (!TARGET_64BIT)
- {
- rtx tmp = gen_reg_rtx (SImode);
- emit_insn (gen_extendqisi2 (tmp, operands[1]));
- emit_insn (gen_extendsidi2 (operands[0], tmp));
- DONE;
- }
- else
- {
- operands[1] = gen_lowpart (DImode, operands[1]);
- emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56)));
- emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (56)));
- DONE;
- }
-}
-")
+(define_insn "*extendhidi2_extimm"
+ [(set (match_operand:DI 0 "register_operand" "=d,d,d")
+ (sign_extend:DI (match_operand:HI 1 "general_operand" "d,RT,b")))]
+ "TARGET_64BIT && TARGET_EXTIMM"
+ "@
+ lghr\t%0,%1
+ lgh\t%0,%1
+ lghrl\t%0,%1"
+ [(set_attr "op_type" "RRE,RXY,RIL")
+ (set_attr "type" "*,*,larl")
+ (set_attr "cpu_facility" "extimm,extimm,z10")
+ (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (sign_extend:DI (match_operand:QI 1 "s_operand" "")))]
- "TARGET_64BIT && !reload_completed"
- [(parallel
- [(set (match_dup 0) (unspec:DI [(match_dup 1)] 10))
- (clobber (reg:CC 33))])
- (parallel
- [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 56)))
- (clobber (reg:CC 33))])]
- "")
+(define_insn "*extendhidi2"
+ [(set (match_operand:DI 0 "register_operand" "=d")
+ (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT")))]
+ "TARGET_64BIT"
+ "lgh\t%0,%1"
+ [(set_attr "op_type" "RXY")
+ (set_attr "z10prop" "z10_super_E1")])
;
; extendhisi2 instruction pattern(s).
;
-(define_expand "extendhisi2"
- [(set (match_operand:SI 0 "register_operand" "")
- (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
- ""
- "
-{
- operands[1] = gen_lowpart (SImode, operands[1]);
- emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (16)));
- emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (16)));
- DONE;
-}
-")
+(define_insn "*extendhisi2_extimm"
+ [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
+ (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" " d,R,T,b")))]
+ "TARGET_EXTIMM"
+ "@
+ lhr\t%0,%1
+ lh\t%0,%1
+ lhy\t%0,%1
+ lhrl\t%0,%1"
+ [(set_attr "op_type" "RRE,RX,RXY,RIL")
+ (set_attr "type" "*,*,*,larl")
+ (set_attr "cpu_facility" "extimm,extimm,extimm,z10")
+ (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
(define_insn "*extendhisi2"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
- ""
- "lh\\t%0,%1"
- [(set_attr "op_type" "RX")
- (set_attr "atype" "mem")])
+ [(set (match_operand:SI 0 "register_operand" "=d,d")
+ (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))]
+ "!TARGET_EXTIMM"
+ "@
+ lh\t%0,%1
+ lhy\t%0,%1"
+ [(set_attr "op_type" "RX,RXY")
+ (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
;
-; extendqisi2 instruction pattern(s).
+; extendqi(si|di)2 instruction pattern(s).
;
-(define_expand "extendqisi2"
- [(set (match_operand:SI 0 "register_operand" "")
- (sign_extend:SI (match_operand:QI 1 "register_operand" "")))]
- ""
- "
-{
- operands[1] = gen_lowpart (SImode, operands[1]);
- emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (24)));
- emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (24)));
- DONE;
-}
-")
-
-(define_split
- [(set (match_operand:SI 0 "register_operand" "")
- (sign_extend:SI (match_operand:QI 1 "s_operand" "")))]
- "!reload_completed"
+; lbr, lgbr, lb, lgb
+(define_insn "*extendqi2_extimm"
+ [(set (match_operand:GPR 0 "register_operand" "=d,d")
+ (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,RT")))]
+ "TARGET_EXTIMM"
+ "@
+ lbr\t%0,%1
+ lb\t%0,%1"
+ [(set_attr "op_type" "RRE,RXY")
+ (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
+
+; lb, lgb
+(define_insn "*extendqi2"
+ [(set (match_operand:GPR 0 "register_operand" "=d")
+ (sign_extend:GPR (match_operand:QI 1 "memory_operand" "RT")))]
+ "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT"
+ "lb\t%0,%1"
+ [(set_attr "op_type" "RXY")
+ (set_attr "z10prop" "z10_super_E1")])
+
+(define_insn_and_split "*extendqi2_short_displ"
+ [(set (match_operand:GPR 0 "register_operand" "=d")
+ (sign_extend:GPR (match_operand:QI 1 "s_operand" "Q")))
+ (clobber (reg:CC CC_REGNUM))]
+ "!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT"
+ "#"
+ "&& reload_completed"
[(parallel
- [(set (match_dup 0) (unspec:SI [(match_dup 1)] 10))
- (clobber (reg:CC 33))])
+ [(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM))
+ (clobber (reg:CC CC_REGNUM))])
(parallel
- [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24)))
- (clobber (reg:CC 33))])]
- "")
-
-;
-; extendqihi2 instruction pattern(s).
-;
-
+ [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
+ (clobber (reg:CC CC_REGNUM))])]
+{
+ operands[1] = adjust_address (operands[1], BLKmode, 0);
+ set_mem_size (operands[1], GEN_INT (GET_MODE_SIZE (QImode)));
+ operands[2] = GEN_INT (GET_MODE_BITSIZE (mode)
+ - GET_MODE_BITSIZE (QImode));
+})
;
; zero_extendsidi2 instruction pattern(s).
@@ -2451,146 +3623,186 @@
[(set (match_operand:DI 0 "register_operand" "")
(zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
""
- "
{
if (!TARGET_64BIT)
{
- emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
+ emit_clobber (operands[0]);
emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
DONE;
}
-}
-")
+})
(define_insn "*zero_extendsidi2"
- [(set (match_operand:DI 0 "register_operand" "=d,d")
- (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
+ [(set (match_operand:DI 0 "register_operand" "=d,d,d")
+ (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
"TARGET_64BIT"
"@
- llgfr\\t%0,%1
- llgf\\t%0,%1"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "atype" "reg,mem")])
+ llgfr\t%0,%1
+ llgf\t%0,%1
+ llgfrl\t%0,%1"
+ [(set_attr "op_type" "RRE,RXY,RIL")
+ (set_attr "type" "*,*,larl")
+ (set_attr "cpu_facility" "*,*,z10")
+ (set_attr "z10prop" "z10_fwd_E1,z10_fwd_A3,z10_fwd_A3")])
;
-; zero_extendhidi2 instruction pattern(s).
+; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
;
-(define_expand "zero_extendhidi2"
- [(set (match_operand:DI 0 "register_operand" "")
- (zero_extend:DI (match_operand:HI 1 "register_operand" "")))]
- ""
- "
-{
- if (!TARGET_64BIT)
- {
- rtx tmp = gen_reg_rtx (SImode);
- emit_insn (gen_zero_extendhisi2 (tmp, operands[1]));
- emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
- DONE;
- }
- else
- {
- operands[1] = gen_lowpart (DImode, operands[1]);
- emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48)));
- emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (48)));
- DONE;
- }
-}
-")
+(define_insn "*llgt_sidi"
+ [(set (match_operand:DI 0 "register_operand" "=d")
+ (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
+ (const_int 2147483647)))]
+ "TARGET_64BIT"
+ "llgt\t%0,%1"
+ [(set_attr "op_type" "RXE")
+ (set_attr "z10prop" "z10_super_E1")])
-(define_insn "*zero_extendhidi2"
+(define_insn_and_split "*llgt_sidi_split"
[(set (match_operand:DI 0 "register_operand" "=d")
- (zero_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
+ (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
+ (const_int 2147483647)))
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT"
- "llgh\\t%0,%1"
- [(set_attr "op_type" "RXE")
- (set_attr "atype" "mem")])
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0)
+ (and:DI (subreg:DI (match_dup 1) 0)
+ (const_int 2147483647)))]
+ "")
+
+(define_insn "*llgt_sisi"
+ [(set (match_operand:SI 0 "register_operand" "=d,d")
+ (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,RT")
+ (const_int 2147483647)))]
+ "TARGET_ZARCH"
+ "@
+ llgtr\t%0,%1
+ llgt\t%0,%1"
+ [(set_attr "op_type" "RRE,RXE")
+ (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
+
+(define_insn "*llgt_didi"
+ [(set (match_operand:DI 0 "register_operand" "=d,d")
+ (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
+ (const_int 2147483647)))]
+ "TARGET_64BIT"
+ "@
+ llgtr\t%0,%1
+ llgt\t%0,%N1"
+ [(set_attr "op_type" "RRE,RXE")
+ (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
+
+(define_split
+ [(set (match_operand:GPR 0 "register_operand" "")
+ (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "")
+ (const_int 2147483647)))
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_ZARCH && reload_completed"
+ [(set (match_dup 0)
+ (and:GPR (match_dup 1)
+ (const_int 2147483647)))]
+ "")
;
-; zero_extendqidi2 instruction pattern(s)
+; zero_extend(hi|qi)(si|di)2 instruction pattern(s).
;
-(define_expand "zero_extendqidi2"
+(define_expand "zero_extenddi2"
[(set (match_operand:DI 0 "register_operand" "")
- (zero_extend:DI (match_operand:QI 1 "register_operand" "")))]
+ (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))]
""
- "
{
if (!TARGET_64BIT)
{
rtx tmp = gen_reg_rtx (SImode);
- emit_insn (gen_zero_extendqisi2 (tmp, operands[1]));
+ emit_insn (gen_zero_extendsi2 (tmp, operands[1]));
emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
DONE;
}
- else
+ else if (!TARGET_EXTIMM)
{
+ rtx bitcount = GEN_INT (GET_MODE_BITSIZE(DImode) -
+ GET_MODE_BITSIZE(mode));
operands[1] = gen_lowpart (DImode, operands[1]);
- emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56)));
- emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (56)));
+ emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
+ emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount));
DONE;
}
-}
-")
-
-(define_insn "*zero_extendqidi2"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (zero_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
- "TARGET_64BIT"
- "llgc\\t%0,%1"
- [(set_attr "op_type" "RXE")
- (set_attr "atype" "mem")])
-
-;
-; zero_extendhisi2 instruction pattern(s).
-;
+})
-(define_expand "zero_extendhisi2"
+(define_expand "zero_extendsi2"
[(set (match_operand:SI 0 "register_operand" "")
- (zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
+ (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))]
""
- "
{
- operands[1] = gen_lowpart (SImode, operands[1]);
- emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xffff)));
- DONE;
-}
-")
+ if (!TARGET_EXTIMM)
+ {
+ operands[1] = gen_lowpart (SImode, operands[1]);
+ emit_insn (gen_andsi3 (operands[0], operands[1],
+ GEN_INT ((1 << GET_MODE_BITSIZE(mode)) - 1)));
+ DONE;
+ }
+})
-(define_insn "*zero_extendhisi2_64"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
- "TARGET_64BIT"
- "llgh\\t%0,%1"
- [(set_attr "op_type" "RXE")
- (set_attr "atype" "mem")])
-
-;
-; zero_extendqisi2 instruction pattern(s).
-;
+; llhrl, llghrl
+(define_insn "*zero_extendhi2_z10"
+ [(set (match_operand:GPR 0 "register_operand" "=d,d,d")
+ (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,RT,b")))]
+ "TARGET_Z10"
+ "@
+ llhr\t%0,%1
+ llh\t%0,%1
+ llhrl\t%0,%1"
+ [(set_attr "op_type" "RXY,RRE,RIL")
+ (set_attr "type" "*,*,larl")
+ (set_attr "cpu_facility" "*,*,z10")
+ (set_attr "z10prop" "z10_super_E1,z10_fwd_A3,z10_fwd_A3")])
+
+; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc
+(define_insn "*zero_extend2_extimm"
+ [(set (match_operand:GPR 0 "register_operand" "=d,d")
+ (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,RT")))]
+ "TARGET_EXTIMM"
+ "@
+ llr\t%0,%1
+ ll\t%0,%1"
+ [(set_attr "op_type" "RRE,RXY")
+ (set_attr "z10prop" "z10_super_E1,z10_fwd_A3")])
+
+; llgh, llgc
+(define_insn "*zero_extend2"
+ [(set (match_operand:GPR 0 "register_operand" "=d")
+ (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "RT")))]
+ "TARGET_ZARCH && !TARGET_EXTIMM"
+ "llg\t%0,%1"
+ [(set_attr "op_type" "RXY")
+ (set_attr "z10prop" "z10_fwd_A3")])
+
+(define_insn_and_split "*zero_extendhisi2_31"
+ [(set (match_operand:SI 0 "register_operand" "=&d")
+ (zero_extend:SI (match_operand:HI 1 "s_operand" "QS")))
+ (clobber (reg:CC CC_REGNUM))]
+ "!TARGET_ZARCH"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0) (const_int 0))
+ (parallel
+ [(set (strict_low_part (match_dup 2)) (match_dup 1))
+ (clobber (reg:CC CC_REGNUM))])]
+ "operands[2] = gen_lowpart (HImode, operands[0]);")
-(define_expand "zero_extendqisi2"
- [(set (match_operand:SI 0 "register_operand" "")
- (zero_extend:SI (match_operand:QI 1 "register_operand" "")))]
- ""
- "
-{
- operands[1] = gen_lowpart (SImode, operands[1]);
- emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xff)));
- DONE;
-}
-")
+(define_insn_and_split "*zero_extendqisi2_31"
+ [(set (match_operand:SI 0 "register_operand" "=&d")
+ (zero_extend:SI (match_operand:QI 1 "memory_operand" "RT")))]
+ "!TARGET_ZARCH"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0) (const_int 0))
+ (set (strict_low_part (match_dup 2)) (match_dup 1))]
+ "operands[2] = gen_lowpart (QImode, operands[0]);")
-(define_insn "*zero_extendqisi2_64"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
- "TARGET_64BIT"
- "llgc\\t%0,%1"
- [(set_attr "op_type" "RXE")
- (set_attr "atype" "mem")])
-
;
; zero_extendqihi2 instruction pattern(s).
;
@@ -2598,459 +3810,429 @@
(define_expand "zero_extendqihi2"
[(set (match_operand:HI 0 "register_operand" "")
(zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
- "TARGET_64BIT"
- "
+ "TARGET_ZARCH && !TARGET_EXTIMM"
{
operands[1] = gen_lowpart (HImode, operands[1]);
emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
DONE;
-}
-")
+})
(define_insn "*zero_extendqihi2_64"
[(set (match_operand:HI 0 "register_operand" "=d")
- (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))
- (clobber (reg:CC 33))]
- "TARGET_64BIT"
- "llgc\\t%0,%1"
- [(set_attr "op_type" "RXE")
- (set_attr "atype" "mem")])
+ (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))]
+ "TARGET_ZARCH && !TARGET_EXTIMM"
+ "llgc\t%0,%1"
+ [(set_attr "op_type" "RXY")
+ (set_attr "z10prop" "z10_fwd_A3")])
+
+(define_insn_and_split "*zero_extendqihi2_31"
+ [(set (match_operand:HI 0 "register_operand" "=&d")
+ (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))]
+ "!TARGET_ZARCH"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0) (const_int 0))
+ (set (strict_low_part (match_dup 2)) (match_dup 1))]
+ "operands[2] = gen_lowpart (QImode, operands[0]);")
;
-; fixuns_truncdfdi2 and fix_truncdfsi2 instruction pattern(s).
+; fixuns_trunc(dd|td)di2 instruction pattern(s).
;
-(define_expand "fixuns_truncdfdi2"
- [(set (match_operand:DI 0 "register_operand" "")
- (unsigned_fix:DI (match_operand:DF 1 "register_operand" "")))]
- "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "
+(define_expand "fixuns_truncdddi2"
+ [(parallel
+ [(set (match_operand:DI 0 "register_operand" "")
+ (unsigned_fix:DI (match_operand:DD 1 "register_operand" "")))
+ (clobber (match_scratch:TD 2 "=f"))])]
+
+ "TARGET_HARD_DFP"
{
rtx label1 = gen_label_rtx ();
rtx label2 = gen_label_rtx ();
- rtx temp = gen_reg_rtx (DFmode);
- operands[1] = force_reg (DFmode, operands[1]);
-
- emit_insn (gen_cmpdf (operands[1],
- CONST_DOUBLE_FROM_REAL_VALUE (
- REAL_VALUE_ATOF (\"9223372036854775808.0\", DFmode), DFmode)));
+ rtx temp = gen_reg_rtx (TDmode);
+ REAL_VALUE_TYPE cmp, sub;
+
+ decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
+ decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
+
+ /* 2^63 can't be represented as 64bit DFP number with full precision. The
+ solution is doing the check and the subtraction in TD mode and using a
+ TD -> DI convert afterwards. */
+ emit_insn (gen_extendddtd2 (temp, operands[1]));
+ temp = force_reg (TDmode, temp);
+ emit_insn (gen_cmptd (temp,
+ CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode)));
emit_jump_insn (gen_blt (label1));
- emit_insn (gen_subdf3 (temp, operands[1],
- CONST_DOUBLE_FROM_REAL_VALUE (
- REAL_VALUE_ATOF (\"18446744073709551616.0\", DFmode), DFmode)));
- emit_insn (gen_fix_truncdfdi2_ieee (operands[0], temp, GEN_INT(7)));
+ emit_insn (gen_subtd3 (temp, temp,
+ CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode)));
+ emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
emit_jump (label2);
emit_label (label1);
- emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
+ emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1], GEN_INT (9)));
emit_label (label2);
DONE;
-}")
+})
-(define_expand "fix_truncdfdi2"
+(define_expand "fixuns_trunctddi2"
[(set (match_operand:DI 0 "register_operand" "")
- (fix:DI (match_operand:DF 1 "nonimmediate_operand" "")))]
- "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "
-{
- operands[1] = force_reg (DFmode, operands[1]);
- emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
- DONE;
-}")
-
-(define_insn "fix_truncdfdi2_ieee"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (fix:DI (match_operand:DF 1 "register_operand" "f")))
- (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] 1)
- (clobber (reg:CC 33))]
- "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "cgdbr\\t%0,%h2,%1"
- [(set_attr "op_type" "RRE")
- (set_attr "type" "other")])
-
-;
-; fixuns_truncdfsi2 and fix_truncdfsi2 instruction pattern(s).
-;
-
-(define_expand "fixuns_truncdfsi2"
- [(set (match_operand:SI 0 "register_operand" "")
- (unsigned_fix:SI (match_operand:DF 1 "register_operand" "")))]
- "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "
+ (unsigned_fix:DI (match_operand:TD 1 "register_operand" "")))]
+ "TARGET_HARD_DFP"
{
rtx label1 = gen_label_rtx ();
rtx label2 = gen_label_rtx ();
- rtx temp = gen_reg_rtx (DFmode);
+ rtx temp = gen_reg_rtx (TDmode);
+ REAL_VALUE_TYPE cmp, sub;
+
+ operands[1] = force_reg (TDmode, operands[1]);
+ decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
+ decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
- operands[1] = force_reg (DFmode,operands[1]);
- emit_insn (gen_cmpdf (operands[1],
- CONST_DOUBLE_FROM_REAL_VALUE (
- REAL_VALUE_ATOF (\"2147483648.0\", DFmode), DFmode)));
+ emit_insn (gen_cmptd (operands[1],
+ CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode)));
emit_jump_insn (gen_blt (label1));
- emit_insn (gen_subdf3 (temp, operands[1],
- CONST_DOUBLE_FROM_REAL_VALUE (
- REAL_VALUE_ATOF (\"4294967296.0\", DFmode), DFmode)));
- emit_insn (gen_fix_truncdfsi2_ieee (operands[0], temp, GEN_INT (7)));
+ emit_insn (gen_subtd3 (temp, operands[1],
+ CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode)));
+ emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
emit_jump (label2);
emit_label (label1);
- emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
+ emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1], GEN_INT (9)));
emit_label (label2);
DONE;
-}")
-
-(define_expand "fix_truncdfsi2"
- [(set (match_operand:SI 0 "register_operand" "")
- (fix:SI (match_operand:DF 1 "nonimmediate_operand" "")))]
- "TARGET_HARD_FLOAT"
- "
-{
- if (TARGET_IBM_FLOAT)
- {
- /* This is the algorithm from POP chapter A.5.7.2. */
-
- rtx temp = assign_stack_local (BLKmode, 2 * UNITS_PER_WORD, BITS_PER_WORD);
- rtx two31r = s390_gen_rtx_const_DI (0x4f000000, 0x08000000);
- rtx two32 = s390_gen_rtx_const_DI (0x4e000001, 0x00000000);
-
- operands[1] = force_reg (DFmode, operands[1]);
- emit_insn (gen_fix_truncdfsi2_ibm (operands[0], operands[1],
- two31r, two32, temp));
- }
- else
- {
- operands[1] = force_reg (DFmode, operands[1]);
- emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
- }
-
- DONE;
-}")
-
-(define_insn "fix_truncdfsi2_ieee"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (fix:SI (match_operand:DF 1 "register_operand" "f")))
- (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] 1)
- (clobber (reg:CC 33))]
- "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "cfdbr\\t%0,%h2,%1"
- [(set_attr "op_type" "RRE")
- (set_attr "type" "other" )])
-
-(define_insn "fix_truncdfsi2_ibm"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (fix:SI (match_operand:DF 1 "nonimmediate_operand" "+f")))
- (use (match_operand:DI 2 "immediate_operand" "m"))
- (use (match_operand:DI 3 "immediate_operand" "m"))
- (use (match_operand:BLK 4 "memory_operand" "m"))
- (clobber (reg:CC 33))]
- "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
- "*
-{
- output_asm_insn (\"sd\\t%1,%2\", operands);
- output_asm_insn (\"aw\\t%1,%3\", operands);
- output_asm_insn (\"std\\t%1,%4\", operands);
- output_asm_insn (\"xi\\t%N4,128\", operands);
- return \"l\\t%0,%N4\";
-}"
- [(set_attr "op_type" "NN")
- (set_attr "type" "other")
- (set_attr "length" "20")])
+})
;
-; fixuns_truncsfdi2 and fix_truncsfdi2 instruction pattern(s).
+; fixuns_trunc(sf|df)(si|di)2 and fix_trunc(sf|df)(si|di)2
+; instruction pattern(s).
;
-(define_expand "fixuns_truncsfdi2"
- [(set (match_operand:DI 0 "register_operand" "")
- (unsigned_fix:DI (match_operand:SF 1 "register_operand" "")))]
- "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "
+(define_expand "fixuns_trunc2"
+ [(set (match_operand:GPR 0 "register_operand" "")
+ (unsigned_fix:GPR (match_operand:BFP 1 "register_operand" "")))]
+ "TARGET_HARD_FLOAT"
{
rtx label1 = gen_label_rtx ();
rtx label2 = gen_label_rtx ();
- rtx temp = gen_reg_rtx (SFmode);
+ rtx temp = gen_reg_rtx (mode);
+ REAL_VALUE_TYPE cmp, sub;
- operands[1] = force_reg (SFmode, operands[1]);
- emit_insn (gen_cmpsf (operands[1],
- CONST_DOUBLE_FROM_REAL_VALUE (
- REAL_VALUE_ATOF (\"9223372036854775808.0\", SFmode), SFmode)));
- emit_jump_insn (gen_blt (label1));
+ operands[1] = force_reg (mode, operands[1]);
+ real_2expN (&cmp, GET_MODE_BITSIZE(mode) - 1, mode);
+ real_2expN (&sub, GET_MODE_BITSIZE(mode), mode);
- emit_insn (gen_subsf3 (temp, operands[1],
- CONST_DOUBLE_FROM_REAL_VALUE (
- REAL_VALUE_ATOF (\"18446744073709551616.0\", SFmode), SFmode)));
- emit_insn (gen_fix_truncsfdi2_ieee (operands[0], temp, GEN_INT(7)));
+ emit_insn (gen_cmp (operands[1],
+ CONST_DOUBLE_FROM_REAL_VALUE (cmp, mode)));
+ emit_jump_insn (gen_blt (label1));
+ emit_insn (gen_sub3 (temp, operands[1],
+ CONST_DOUBLE_FROM_REAL_VALUE (sub, mode)));
+ emit_insn (gen_fix_trunc2_bfp (operands[0], temp,
+ GEN_INT (7)));
emit_jump (label2);
emit_label (label1);
- emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
+ emit_insn (gen_fix_trunc