X-Git-Url: https://oss.titaniummirror.com/gitweb?p=msp430-binutils.git;a=blobdiff_plain;f=bfd%2Fdoc%2Freloc.texi;fp=bfd%2Fdoc%2Freloc.texi;h=74902ae20119b42434751b3a6fc346c75c377314;hp=e3ea426ec890335ad6068a51675de5aeb653169f;hb=88750007d7869f178f0ba528f41efd3b74c424cf;hpb=6df9443a374e2b81278c61b8afc0a1eef7db280b

diff --git a/bfd/doc/reloc.texi b/bfd/doc/reloc.texi
index e3ea426..74902ae 100644
--- a/bfd/doc/reloc.texi
+++ b/bfd/doc/reloc.texi
@@ -556,6 +556,21 @@ For ELF.
 @deffn {} BFD_RELOC_68K_GLOB_DAT
 @deffnx {} BFD_RELOC_68K_JMP_SLOT
 @deffnx {} BFD_RELOC_68K_RELATIVE
+@deffnx {} BFD_RELOC_68K_TLS_GD32
+@deffnx {} BFD_RELOC_68K_TLS_GD16
+@deffnx {} BFD_RELOC_68K_TLS_GD8
+@deffnx {} BFD_RELOC_68K_TLS_LDM32
+@deffnx {} BFD_RELOC_68K_TLS_LDM16
+@deffnx {} BFD_RELOC_68K_TLS_LDM8
+@deffnx {} BFD_RELOC_68K_TLS_LDO32
+@deffnx {} BFD_RELOC_68K_TLS_LDO16
+@deffnx {} BFD_RELOC_68K_TLS_LDO8
+@deffnx {} BFD_RELOC_68K_TLS_IE32
+@deffnx {} BFD_RELOC_68K_TLS_IE16
+@deffnx {} BFD_RELOC_68K_TLS_IE8
+@deffnx {} BFD_RELOC_68K_TLS_LE32
+@deffnx {} BFD_RELOC_68K_TLS_LE16
+@deffnx {} BFD_RELOC_68K_TLS_LE8
 Relocations used by 68K ELF.
 @end deffn
 @deffn {} BFD_RELOC_32_BASEREL
@@ -612,6 +627,11 @@ Reloc types used for i960/b.out.
 @deffnx {} BFD_RELOC_SPARC_UA16
 @deffnx {} BFD_RELOC_SPARC_UA32
 @deffnx {} BFD_RELOC_SPARC_UA64
+@deffnx {} BFD_RELOC_SPARC_GOTDATA_HIX22
+@deffnx {} BFD_RELOC_SPARC_GOTDATA_LOX10
+@deffnx {} BFD_RELOC_SPARC_GOTDATA_OP_HIX22
+@deffnx {} BFD_RELOC_SPARC_GOTDATA_OP_LOX10
+@deffnx {} BFD_RELOC_SPARC_GOTDATA_OP
 SPARC ELF relocations.  There is probably some overlap with other
 relocation types already defined.
 @end deffn
@@ -688,6 +708,7 @@ SPARC TLS relocations
 @deffnx {} BFD_RELOC_SPU_HI16
 @deffnx {} BFD_RELOC_SPU_PPU32
 @deffnx {} BFD_RELOC_SPU_PPU64
+@deffnx {} BFD_RELOC_SPU_ADD_PIC
 SPU Relocations.
 @end deffn
 @deffn {} BFD_RELOC_ALPHA_GPDISP_HI16
@@ -759,6 +780,22 @@ Like BFD_RELOC_23_PCREL_S2, except that the source and target must
 share a common GP, and the target address is adjusted for
 STO_ALPHA_STD_GPLOAD.
 @end deffn
+@deffn {} BFD_RELOC_ALPHA_NOP
+The NOP relocation outputs a NOP if the longword displacement
+between two procedure entry points is < 2^21.
+@end deffn
+@deffn {} BFD_RELOC_ALPHA_BSR
+The BSR relocation outputs a BSR if the longword displacement
+between two procedure entry points is < 2^21.
+@end deffn
+@deffn {} BFD_RELOC_ALPHA_LDA
+The LDA relocation outputs a LDA if the longword displacement
+between two procedure entry points is < 2^16.
+@end deffn
+@deffn {} BFD_RELOC_ALPHA_BOH
+The BOH relocation outputs a BSR if the longword displacement
+between two procedure entry points is < 2^21, or else a hint.
+@end deffn
 @deffn {} BFD_RELOC_ALPHA_TLSGD
 @deffnx {} BFD_RELOC_ALPHA_TLSLDM
 @deffnx {} BFD_RELOC_ALPHA_DTPMOD64
@@ -805,6 +842,11 @@ High 16 bits of 32-bit pc-relative value, adjusted
 @deffn {} BFD_RELOC_LO16_PCREL
 Low 16 bits of pc-relative value
 @end deffn
+@deffn {} BFD_RELOC_MIPS16_GOT16
+@deffnx {} BFD_RELOC_MIPS16_CALL16
+Equivalent of BFD_RELOC_MIPS_*, but with the MIPS16 layout of
+16-bit immediate fields
+@end deffn
 @deffn {} BFD_RELOC_MIPS16_HI16
 MIPS16 high 16 bits of 32-bit value.
 @end deffn
@@ -858,7 +900,10 @@ MIPS ELF relocations.
 @end deffn
 @deffn {} BFD_RELOC_MIPS_COPY
 @deffnx {} BFD_RELOC_MIPS_JUMP_SLOT
-MIPS ELF relocations (VxWorks extensions).
+MIPS ELF relocations (VxWorks and PLT extensions).
+@end deffn
+@deffn {} BFD_RELOC_MOXIE_10_PCREL
+Moxie ELF relocations.
 @end deffn
 @deffn {} BFD_RELOC_FRV_LABEL16
 @deffnx {} BFD_RELOC_FRV_LABEL24
@@ -928,6 +973,16 @@ Create PLT entry.
 @deffn {} BFD_RELOC_MN10300_RELATIVE
 Adjust by program base.
 @end deffn
+@deffn {} BFD_RELOC_MN10300_SYM_DIFF
+Together with another reloc targeted at the same location,
+allows for a value that is the difference of two symbols
+in the same section.
+@end deffn
+@deffn {} BFD_RELOC_MN10300_ALIGN
+The addend of this reloc is an alignment power that must
+be honoured at the offset's location, regardless of linker
+relaxation.
+@end deffn
 @deffn {} BFD_RELOC_386_GOT32
 @deffnx {} BFD_RELOC_386_PLT32
 @deffnx {} BFD_RELOC_386_COPY
@@ -951,6 +1006,7 @@ Adjust by program base.
 @deffnx {} BFD_RELOC_386_TLS_GOTDESC
 @deffnx {} BFD_RELOC_386_TLS_DESC_CALL
 @deffnx {} BFD_RELOC_386_TLS_DESC
+@deffnx {} BFD_RELOC_386_IRELATIVE
 i386/elf relocations
 @end deffn
 @deffn {} BFD_RELOC_X86_64_GOT32
@@ -979,6 +1035,7 @@ i386/elf relocations
 @deffnx {} BFD_RELOC_X86_64_GOTPC32_TLSDESC
 @deffnx {} BFD_RELOC_X86_64_TLSDESC_CALL
 @deffnx {} BFD_RELOC_X86_64_TLSDESC
+@deffnx {} BFD_RELOC_X86_64_IRELATIVE
 x86-64/elf relocations
 @end deffn
 @deffn {} BFD_RELOC_NS32K_IMM_8
@@ -1063,6 +1120,8 @@ Picojava relocs.  Not all of these appear in object files.
 Power(rs6000) and PowerPC relocations.
 @end deffn
 @deffn {} BFD_RELOC_PPC_TLS
+@deffnx {} BFD_RELOC_PPC_TLSGD
+@deffnx {} BFD_RELOC_PPC_TLSLD
 @deffnx {} BFD_RELOC_PPC_DTPMOD
 @deffnx {} BFD_RELOC_PPC_TPREL16
 @deffnx {} BFD_RELOC_PPC_TPREL16_LO
@@ -1227,6 +1286,9 @@ ARM thread-local storage relocations.
 @deffnx {} BFD_RELOC_ARM_LDC_SB_G2
 ARM group relocations.
 @end deffn
+@deffn {} BFD_RELOC_ARM_V4BX
+Annotation of BX instructions.
+@end deffn
 @deffn {} BFD_RELOC_ARM_IMMEDIATE
 @deffnx {} BFD_RELOC_ARM_ADRL_IMMEDIATE
 @deffnx {} BFD_RELOC_ARM_T32_IMMEDIATE
@@ -2023,10 +2085,8 @@ s390 tls relocations.
 @deffnx {} BFD_RELOC_390_TLS_GOTIE20
 Long displacement extension.
 @end deffn
-@deffn {} BFD_RELOC_SCORE_DUMMY1
-Score relocations
-@end deffn
 @deffn {} BFD_RELOC_SCORE_GPREL15
+Score relocations
 Low 16 bit for load/store
 @end deffn
 @deffn {} BFD_RELOC_SCORE_DUMMY2
@@ -2036,12 +2096,21 @@ This is a 24-bit reloc with the right 1 bit assumed to be 0
 @deffn {} BFD_RELOC_SCORE_BRANCH
 This is a 19-bit reloc with the right 1 bit assumed to be 0
 @end deffn
+@deffn {} BFD_RELOC_SCORE_IMM30
+This is a 32-bit reloc for 48-bit instructions.
+@end deffn
+@deffn {} BFD_RELOC_SCORE_IMM32
+This is a 32-bit reloc for 48-bit instructions.
+@end deffn
 @deffn {} BFD_RELOC_SCORE16_JMP
 This is a 11-bit reloc with the right 1 bit assumed to be 0
 @end deffn
 @deffn {} BFD_RELOC_SCORE16_BRANCH
 This is a 8-bit reloc with the right 1 bit assumed to be 0
 @end deffn
+@deffn {} BFD_RELOC_SCORE_BCMP
+This is a 9-bit reloc with the right 1 bit assumed to be 0
+@end deffn
 @deffn {} BFD_RELOC_SCORE_GOT15
 @deffnx {} BFD_RELOC_SCORE_GOT_LO16
 @deffnx {} BFD_RELOC_SCORE_CALL15
@@ -2299,6 +2368,12 @@ NS CR16C Relocations.
 @deffnx {} BFD_RELOC_CR16_DISP20
 @deffnx {} BFD_RELOC_CR16_DISP24
 @deffnx {} BFD_RELOC_CR16_DISP24a
+@deffnx {} BFD_RELOC_CR16_SWITCH8
+@deffnx {} BFD_RELOC_CR16_SWITCH16
+@deffnx {} BFD_RELOC_CR16_SWITCH32
+@deffnx {} BFD_RELOC_CR16_GOT_REGREL20
+@deffnx {} BFD_RELOC_CR16_GOTC_REGREL20
+@deffnx {} BFD_RELOC_CR16_GLOB_DAT
 NS CR16 Relocations.
 @end deffn
 @deffn {} BFD_RELOC_CRX_REL4
@@ -2363,6 +2438,20 @@ Relocs used in ELF shared libraries for CRIS.
 @deffn {} BFD_RELOC_CRIS_32_PLT_PCREL
 32-bit offset to symbol with PLT entry, relative to this relocation.
 @end deffn
+@deffn {} BFD_RELOC_CRIS_32_GOT_GD
+@deffnx {} BFD_RELOC_CRIS_16_GOT_GD
+@deffnx {} BFD_RELOC_CRIS_32_GD
+@deffnx {} BFD_RELOC_CRIS_DTP
+@deffnx {} BFD_RELOC_CRIS_32_DTPREL
+@deffnx {} BFD_RELOC_CRIS_16_DTPREL
+@deffnx {} BFD_RELOC_CRIS_32_GOT_TPREL
+@deffnx {} BFD_RELOC_CRIS_16_GOT_TPREL
+@deffnx {} BFD_RELOC_CRIS_32_TPREL
+@deffnx {} BFD_RELOC_CRIS_16_TPREL
+@deffnx {} BFD_RELOC_CRIS_DTPMOD
+@deffnx {} BFD_RELOC_CRIS_32_IE
+Relocs used in TLS code for CRIS.
+@end deffn
 @deffn {} BFD_RELOC_860_COPY
 @deffnx {} BFD_RELOC_860_GLOB_DAT
 @deffnx {} BFD_RELOC_860_JUMP_SLOT
@@ -2539,6 +2628,15 @@ assembler-expanded instructions.  This is commonly used
 internally by the linker after analysis of a
 BFD_RELOC_XTENSA_ASM_EXPAND.
 @end deffn
+@deffn {} BFD_RELOC_XTENSA_TLSDESC_FN
+@deffnx {} BFD_RELOC_XTENSA_TLSDESC_ARG
+@deffnx {} BFD_RELOC_XTENSA_TLS_DTPOFF
+@deffnx {} BFD_RELOC_XTENSA_TLS_TPOFF
+@deffnx {} BFD_RELOC_XTENSA_TLS_FUNC
+@deffnx {} BFD_RELOC_XTENSA_TLS_ARG
+@deffnx {} BFD_RELOC_XTENSA_TLS_CALL
+Xtensa TLS relocations.
+@end deffn
 @deffn {} BFD_RELOC_Z80_DISP8
 8 bit signed offset in (ix+d) or (iy+d).
 @end deffn
@@ -2551,6 +2649,77 @@ CALR offset.
 @deffn {} BFD_RELOC_Z8K_IMM4L
 4 bit value.
 @end deffn
+@deffn {} BFD_RELOC_LM32_CALL
+@deffnx {} BFD_RELOC_LM32_BRANCH
+@deffnx {} BFD_RELOC_LM32_16_GOT
+@deffnx {} BFD_RELOC_LM32_GOTOFF_HI16
+@deffnx {} BFD_RELOC_LM32_GOTOFF_LO16
+@deffnx {} BFD_RELOC_LM32_COPY
+@deffnx {} BFD_RELOC_LM32_GLOB_DAT
+@deffnx {} BFD_RELOC_LM32_JMP_SLOT
+@deffnx {} BFD_RELOC_LM32_RELATIVE
+Lattice Mico32 relocations.
+@end deffn
+@deffn {} BFD_RELOC_MACH_O_SECTDIFF
+Difference between two section addreses.  Must be followed by a
+BFD_RELOC_MACH_O_PAIR.
+@end deffn
+@deffn {} BFD_RELOC_MACH_O_PAIR
+Mach-O generic relocations.
+@end deffn
+@deffn {} BFD_RELOC_MICROBLAZE_32_LO
+This is a 32 bit reloc for the microblaze that stores the 
+low 16 bits of a value
+@end deffn
+@deffn {} BFD_RELOC_MICROBLAZE_32_LO_PCREL
+This is a 32 bit pc-relative reloc for the microblaze that 
+stores the low 16 bits of a value
+@end deffn
+@deffn {} BFD_RELOC_MICROBLAZE_32_ROSDA
+This is a 32 bit reloc for the microblaze that stores a 
+value relative to the read-only small data area anchor
+@end deffn
+@deffn {} BFD_RELOC_MICROBLAZE_32_RWSDA
+This is a 32 bit reloc for the microblaze that stores a 
+value relative to the read-write small data area anchor
+@end deffn
+@deffn {} BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM
+This is a 32 bit reloc for the microblaze to handle 
+expressions of the form "Symbol Op Symbol"
+@end deffn
+@deffn {} BFD_RELOC_MICROBLAZE_64_NONE
+This is a 64 bit reloc that stores the 32 bit pc relative 
+value in two words (with an imm instruction).  No relocation is 
+done here - only used for relaxing
+@end deffn
+@deffn {} BFD_RELOC_MICROBLAZE_64_GOTPC
+This is a 64 bit reloc that stores the 32 bit pc relative 
+value in two words (with an imm instruction).  The relocation is
+PC-relative GOT offset
+@end deffn
+@deffn {} BFD_RELOC_MICROBLAZE_64_GOT
+This is a 64 bit reloc that stores the 32 bit pc relative 
+value in two words (with an imm instruction).  The relocation is
+GOT offset
+@end deffn
+@deffn {} BFD_RELOC_MICROBLAZE_64_PLT
+This is a 64 bit reloc that stores the 32 bit pc relative 
+value in two words (with an imm instruction).  The relocation is
+PC-relative offset into PLT
+@end deffn
+@deffn {} BFD_RELOC_MICROBLAZE_64_GOTOFF
+This is a 64 bit reloc that stores the 32 bit GOT relative 
+value in two words (with an imm instruction).  The relocation is
+relative offset from _GLOBAL_OFFSET_TABLE_
+@end deffn
+@deffn {} BFD_RELOC_MICROBLAZE_32_GOTOFF
+This is a 32 bit reloc that stores the 32 bit GOT relative 
+value in a word.  The relocation is relative offset from
+@end deffn
+@deffn {} BFD_RELOC_MICROBLAZE_COPY
+This is used to tell the dynamic linker to copy the value out of
+the dynamic object into the runtime process image.
+@end deffn
 
 @example