X-Git-Url: https://oss.titaniummirror.com/gitweb?p=msp430-binutils.git;a=blobdiff_plain;f=gas%2Ftestsuite%2Fgas%2Fi386%2Fx86-64-opcode-inval-intel.d;fp=gas%2Ftestsuite%2Fgas%2Fi386%2Fx86-64-opcode-inval-intel.d;h=7cf0c27e5400d8328c588ccae50a1782abf92f53;hp=0000000000000000000000000000000000000000;hb=88750007d7869f178f0ba528f41efd3b74c424cf;hpb=6df9443a374e2b81278c61b8afc0a1eef7db280b

diff --git a/gas/testsuite/gas/i386/x86-64-opcode-inval-intel.d b/gas/testsuite/gas/i386/x86-64-opcode-inval-intel.d
new file mode 100644
index 0000000..7cf0c27
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-opcode-inval-intel.d
@@ -0,0 +1,50 @@
+#as: --32
+#source: x86-64-opcode-inval.s
+#objdump: -dw -Mx86-64 -Mintel
+#name: 64bit illegal opcodes (Intel mode)
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <aaa>:
+[ 	]*[a-f0-9]+:	37                   	\(bad\)  
+
+0+1 <aad0>:
+[ 	]*[a-f0-9]+:	d5                   	\(bad\)  
+[ 	]*[a-f0-9]+:	0a d5                	or     dl,ch
+
+0+3 <aad1>:
+[ 	]*[a-f0-9]+:	d5                   	\(bad\)  
+[ 	]*[a-f0-9]+:	02 d4                	add    dl,ah
+
+0+5 <aam0>:
+[ 	]*[a-f0-9]+:	d4                   	\(bad\)  
+[ 	]*[a-f0-9]+:	0a d4                	or     dl,ah
+
+0+7 <aam1>:
+[ 	]*[a-f0-9]+:	d4                   	\(bad\)  
+[ 	]*[a-f0-9]+:	02 3f                	add    bh,BYTE PTR \[rdi\]
+
+0+9 <aas>:
+[ 	]*[a-f0-9]+:	3f                   	\(bad\)  
+
+0+a <bound>:
+[ 	]*[a-f0-9]+:	62                   	\(bad\)  
+[ 	]*[a-f0-9]+:	10 27                	adc    BYTE PTR \[rdi\],ah
+
+0+c <daa>:
+[ 	]*[a-f0-9]+:	27                   	\(bad\)  
+
+0+d <das>:
+[ 	]*[a-f0-9]+:	2f                   	\(bad\)  
+
+0+e <into>:
+[ 	]*[a-f0-9]+:	ce                   	\(bad\)  
+
+0+f <pusha>:
+[ 	]*[a-f0-9]+:	60                   	\(bad\)  
+
+0+10 <popa>:
+[ 	]*[a-f0-9]+:	61                   	\(bad\)  
+#pass