X-Git-Url: https://oss.titaniummirror.com/gitweb?p=msp430-binutils.git;a=blobdiff_plain;f=gas%2Ftestsuite%2Fgas%2Fmips%2Fmips16-intermix.d;fp=gas%2Ftestsuite%2Fgas%2Fmips%2Fmips16-intermix.d;h=0242d9c2b61e019f4b992a8def5fdf5b8276712e;hp=9b541eefebcf3932bd3e3b6f8f8b90d9d0f848d3;hb=88750007d7869f178f0ba528f41efd3b74c424cf;hpb=6df9443a374e2b81278c61b8afc0a1eef7db280b diff --git a/gas/testsuite/gas/mips/mips16-intermix.d b/gas/testsuite/gas/mips/mips16-intermix.d index 9b541ee..0242d9c 100644 --- a/gas/testsuite/gas/mips/mips16-intermix.d +++ b/gas/testsuite/gas/mips/mips16-intermix.d @@ -1,164 +1,121 @@ -#objdump: -t -#as: -mips32r2 +#PROG: nm +#as: -mips32r2 -32 #name: MIPS16 intermix -.*: +file format .*mips.* - -SYMBOL TABLE: -#... -0+[0-9a-f]+ l F .text 0+[0-9a-f]+ m32_static_l -0+[0-9a-f]+ l F .text 0+[0-9a-f]+ 0xf0 m16_static_l -0+[0-9a-f]+ l F .text 0+[0-9a-f]+ m32_static1_l -0+[0-9a-f]+ l F .text 0+[0-9a-f]+ 0xf0 m16_static1_l -0+[0-9a-f]+ l F .text 0+[0-9a-f]+ m32_static32_l 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+0+[0-9a-f]+ T m16_d +0+[0-9a-f]+ T m16_d_d +0+[0-9a-f]+ T m16_d_l +0+[0-9a-f]+ T m16_dl +0+[0-9a-f]+ T m16_dlld +0+[0-9a-f]+ T m16_l +0+[0-9a-f]+ T m16_ld +0+[0-9a-f]+ t m16_static16_d +0+[0-9a-f]+ t m16_static16_d_d +0+[0-9a-f]+ t m16_static16_d_l +0+[0-9a-f]+ t m16_static16_dl +0+[0-9a-f]+ t m16_static16_dlld +0+[0-9a-f]+ t m16_static16_l +0+[0-9a-f]+ t m16_static16_ld +0+[0-9a-f]+ t m16_static1_d +0+[0-9a-f]+ t m16_static1_d_d +0+[0-9a-f]+ t m16_static1_d_l +0+[0-9a-f]+ t m16_static1_dl +0+[0-9a-f]+ t m16_static1_dlld +0+[0-9a-f]+ t m16_static1_l +0+[0-9a-f]+ t m16_static1_ld +0+[0-9a-f]+ t m16_static32_d +0+[0-9a-f]+ t m16_static32_d_d +0+[0-9a-f]+ t m16_static32_d_l +0+[0-9a-f]+ t m16_static32_dl +0+[0-9a-f]+ t m16_static32_dlld +0+[0-9a-f]+ t m16_static32_l +0+[0-9a-f]+ t m16_static32_ld +0+[0-9a-f]+ t m16_static_d +0+[0-9a-f]+ t m16_static_d_d +0+[0-9a-f]+ t m16_static_d_l +0+[0-9a-f]+ t m16_static_dl +0+[0-9a-f]+ t m16_static_dlld +0+[0-9a-f]+ t m16_static_l +0+[0-9a-f]+ t m16_static_ld +0+[0-9a-f]+ T m32_d +0+[0-9a-f]+ T m32_d_d +0+[0-9a-f]+ T m32_d_l +0+[0-9a-f]+ T m32_dl +0+[0-9a-f]+ T m32_dlld +0+[0-9a-f]+ T m32_l +0+[0-9a-f]+ T m32_ld +0+[0-9a-f]+ t m32_static16_d +0+[0-9a-f]+ t m32_static16_d_d +0+[0-9a-f]+ t m32_static16_d_l +0+[0-9a-f]+ t m32_static16_dl +0+[0-9a-f]+ t m32_static16_dlld +0+[0-9a-f]+ t m32_static16_l +0+[0-9a-f]+ t m32_static16_ld +0+[0-9a-f]+ t m32_static1_d +0+[0-9a-f]+ t m32_static1_d_d +0+[0-9a-f]+ t m32_static1_d_l +0+[0-9a-f]+ t m32_static1_dl +0+[0-9a-f]+ t m32_static1_dlld +0+[0-9a-f]+ t m32_static1_l +0+[0-9a-f]+ t m32_static1_ld +0+[0-9a-f]+ t m32_static32_d +0+[0-9a-f]+ t m32_static32_d_d +0+[0-9a-f]+ t m32_static32_d_l +0+[0-9a-f]+ t m32_static32_dl +0+[0-9a-f]+ t m32_static32_dlld +0+[0-9a-f]+ t m32_static32_l +0+[0-9a-f]+ t m32_static32_ld +0+[0-9a-f]+ t m32_static_d +0+[0-9a-f]+ t m32_static_d_d +0+[0-9a-f]+ t m32_static_d_l +0+[0-9a-f]+ t m32_static_dl +0+[0-9a-f]+ t m32_static_dlld +0+[0-9a-f]+ t m32_static_l +0+[0-9a-f]+ t m32_static_ld #pass