X-Git-Url: https://oss.titaniummirror.com/gitweb?p=msp430-binutils.git;a=blobdiff_plain;f=include%2Fopcode%2Fi386.h;fp=include%2Fopcode%2Fi386.h;h=a0447b9d54c29ff90fb10fb16a9e99e6f9a9c5eb;hp=4fe769a58bfcfadfd31b4adc50ad987a82f368b6;hb=d5da4f291af551c0b8b79e1d4a9b173d60e5c10e;hpb=7b5ea4fcdf2819e070665ab5610f8b48e3867c10

diff --git a/include/opcode/i386.h b/include/opcode/i386.h
index 4fe769a..a0447b9 100644
--- a/include/opcode/i386.h
+++ b/include/opcode/i386.h
@@ -1,6 +1,6 @@
 /* opcode/i386.h -- Intel 80386 opcode macros
    Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
-   2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
+   2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger.
@@ -35,6 +35,9 @@
 
    The affected opcode map is dceX, dcfX, deeX, defX.  */
 
+#ifndef OPCODE_I386_H
+#define OPCODE_I386_H
+
 #ifndef SYSV386_COMPAT
 /* Set non-zero for broken, compatible instructions.  Set to zero for
    non-broken opcodes at your peril.  gcc generates SystemV/386
@@ -56,6 +59,11 @@
 /* The opcode for the fwait instruction, which disassembler treats as a
    prefix when it can.  */
 #define FWAIT_OPCODE 0x9b
+
+/* Instruction prefixes.
+   NOTE: For certain SSE* instructions, 0x66,0xf2,0xf3 are treated as
+   part of the opcode.  Other prefixes may still appear between them
+   and the 0x0f part of the opcode.  */
 #define ADDR_PREFIX_OPCODE 0x67
 #define DATA_PREFIX_OPCODE 0x66
 #define LOCK_PREFIX_OPCODE 0xf0
@@ -72,8 +80,14 @@
 #define NOP_OPCODE (char) 0x90
 
 /* register numbers */
-#define EBP_REG_NUM 5
+#define EAX_REG_NUM 0
+#define ECX_REG_NUM 1
+#define EDX_REG_NUM 2
+#define EBX_REG_NUM 3
 #define ESP_REG_NUM 4
+#define EBP_REG_NUM 5
+#define ESI_REG_NUM 6
+#define EDI_REG_NUM 7
 
 /* modrm_byte.regmem for twobyte escape */
 #define ESCAPE_TO_TWO_BYTE_ADDRESSING ESP_REG_NUM
@@ -87,9 +101,22 @@
 #define REGMEM_FIELD_HAS_REG 0x3/* always = 0x3 */
 #define REGMEM_FIELD_HAS_MEM (~REGMEM_FIELD_HAS_REG)
 
+/* Extract fields from the mod/rm byte.  */
+#define MODRM_MOD_FIELD(modrm) (((modrm) >> 6) & 3)
+#define MODRM_REG_FIELD(modrm) (((modrm) >> 3) & 7)
+#define MODRM_RM_FIELD(modrm)  (((modrm) >> 0) & 7)
+
+/* Extract fields from the sib byte.  */
+#define SIB_SCALE_FIELD(sib) (((sib) >> 6) & 3)
+#define SIB_INDEX_FIELD(sib) (((sib) >> 3) & 7)
+#define SIB_BASE_FIELD(sib)  (((sib) >> 0) & 7)
+
 /* x86-64 extension prefix.  */
 #define REX_OPCODE	0x40
 
+/* Non-zero if OPCODE is the rex prefix.  */
+#define REX_PREFIX_P(opcode) (((opcode) & 0xf0) == REX_OPCODE)
+
 /* Indicates 64 bit operand size.  */
 #define REX_W	8
 /* High extension to reg field of modrm byte.  */
@@ -100,7 +127,7 @@
 #define REX_B	1
 
 /* max operands per insn */
-#define MAX_OPERANDS 4
+#define MAX_OPERANDS 5
 
 /* max immediates per insn (lcall, ljmp, insertq, extrq) */
 #define MAX_IMMEDIATE_OPERANDS 2
@@ -109,7 +136,9 @@
 #define MAX_MEMORY_OPERANDS 2
 
 /* max size of insn mnemonics.  */
-#define MAX_MNEM_SIZE 16
+#define MAX_MNEM_SIZE 20
 
 /* max size of register name in insn mnemonics.  */
 #define MAX_REG_NAME_SIZE 8
+
+#endif /* OPCODE_I386_H */