X-Git-Url: https://oss.titaniummirror.com/gitweb?p=msp430-binutils.git;a=blobdiff_plain;f=ld%2Ftestsuite%2Fld-mips-elf%2Fpic-and-nonpic-6-n64.dd;fp=ld%2Ftestsuite%2Fld-mips-elf%2Fpic-and-nonpic-6-n64.dd;h=7efa5d15d05110d912f29f2e4fdc9ce04ddad01b;hp=0000000000000000000000000000000000000000;hb=d5da4f291af551c0b8b79e1d4a9b173d60e5c10e;hpb=7b5ea4fcdf2819e070665ab5610f8b48e3867c10

diff --git a/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64.dd b/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64.dd
new file mode 100644
index 0000000..7efa5d1
--- /dev/null
+++ b/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64.dd
@@ -0,0 +1,101 @@
+# GOT layout:
+#
+# -32752: lazy resolution function
+# -32744: reserved for module pointer
+# -32736: extf2's GOT entry (undefined 0)
+# -32728: extf3's GOT entry (PLT entry)
+# -32720: extd2's GOT entry (copy reloc)
+# -32712: extf1's GOT entry (.MIPS.stubs entry)
+# -32704: extd1's GOT entry (undefined 0)
+# -32696: extf4's GOT entry (PLT entry)
+# -32688: extd4's GOT entry (undefined 0, reloc only)
+
+.*
+
+Disassembly of section \.plt:
+
+0+43080 <.*>:
+.*:	3c0e0008 	lui	t2,0x8
+.*:	ddd91000 	ld	t9,4096\(t2\)
+.*:	25ce1000 	addiu	t2,t2,4096
+.*:	030ec023 	subu	t8,t8,t2
+.*:	03e07821 	move	t3,ra
+.*:	0018c0c2 	srl	t8,t8,0x3
+.*:	0320f809 	jalr	t9
+.*:	2718fffe 	addiu	t8,t8,-2
+
+0+430a0 <extf4@plt>:
+.*:	3c0f0008 	lui	t3,0x8
+.*:	ddf91010 	ld	t9,4112\(t3\)
+.*:	03200008 	jr	t9
+.*:	25f81010 	addiu	t8,t3,4112
+
+0+430b0 <extf5@plt>:
+.*:	3c0f0008 	lui	t3,0x8
+.*:	ddf91018 	ld	t9,4120\(t3\)
+.*:	03200008 	jr	t9
+.*:	25f81018 	addiu	t8,t3,4120
+
+0+430c0 <extf3@plt>:
+.*:	3c0f0008 	lui	t3,0x8
+.*:	ddf91020 	ld	t9,4128\(t3\)
+.*:	03200008 	jr	t9
+.*:	25f81020 	addiu	t8,t3,4128
+
+Disassembly of section \.text:
+
+0+44000 <.*>:
+	\.\.\.
+
+0+44008 <\.pic\.f1>:
+   44008:	3c190004 	lui	t9,0x4
+   4400c:	27394010 	addiu	t9,t9,16400
+
+0+44010 <f1>:
+   44010:	0c011013 	jal	4404c <f3>
+   44014:	3c020004 	lui	v0,0x4
+   44018:	03e00008 	jr	ra
+   4401c:	24424020 	addiu	v0,v0,16416
+
+0+44020 <f2>:
+   44020:	3c1c0006 	lui	gp,0x6
+   44024:	0399e021 	addu	gp,gp,t9
+   44028:	279c3fd0 	addiu	gp,gp,16336
+   4402c:	df998038 	ld	t9,-32712\(gp\)
+   44030:	df848020 	ld	a0,-32736\(gp\)
+   44034:	df858040 	ld	a1,-32704\(gp\)
+   44038:	0320f809 	jalr	t9
+   4403c:	df868030 	ld	a2,-32720\(gp\)
+   44040:	df998028 	ld	t9,-32728\(gp\)
+   44044:	03200008 	jr	t9
+   44048:	df848048 	ld	a0,-32696\(gp\)
+
+0+4404c <f3>:
+   4404c:	03e00008 	jr	ra
+   44050:	00000000 	nop
+	\.\.\.
+
+0+44060 <__start>:
+   44060:	0c011002 	jal	44008 <\.pic\.f1>
+   44064:	00000000 	nop
+   44068:	3c020004 	lui	v0,0x4
+   4406c:	24424020 	addiu	v0,v0,16416
+   44070:	0c010c30 	jal	430c0 <extf3@plt>
+   44074:	00000000 	nop
+   44078:	0c010c28 	jal	430a0 <extf4@plt>
+   4407c:	00000000 	nop
+   44080:	0c010c2c 	jal	430b0 <extf5@plt>
+   44084:	00000000 	nop
+   44088:	3c02000a 	lui	v0,0xa
+   4408c:	24422000 	addiu	v0,v0,8192
+   44090:	3c02000a 	lui	v0,0xa
+   44094:	24422018 	addiu	v0,v0,8216
+	\.\.\.
+Disassembly of section \.MIPS\.stubs:
+
+0+440a0 <\.MIPS\.stubs>:
+   440a0:	df998010 	ld	t9,-32752\(gp\)
+   440a4:	03e0782d 	move	t3,ra
+   440a8:	0320f809 	jalr	t9
+   440ac:	6418000a 	daddiu	t8,zero,10
+	\.\.\.