X-Git-Url: https://oss.titaniummirror.com/gitweb?p=msp430-binutils.git;a=blobdiff_plain;f=opcodes%2Fcr16-opc.c;fp=opcodes%2Fcr16-opc.c;h=fed2ea13b23e7553cd6a283cbb144ff41fb8c3ae;hp=081c63d8206485f2664af96dd2576285371a7457;hb=88750007d7869f178f0ba528f41efd3b74c424cf;hpb=6df9443a374e2b81278c61b8afc0a1eef7db280b

diff --git a/opcodes/cr16-opc.c b/opcodes/cr16-opc.c
index 081c63d..fed2ea1 100644
--- a/opcodes/cr16-opc.c
+++ b/opcodes/cr16-opc.c
@@ -1,5 +1,5 @@
 /* cr16-opc.c -- Table of opcodes for the CR16 processor.
-   Copyright 2007 Free Software Foundation, Inc.
+   Copyright 2007, 2008 Free Software Foundation, Inc.
    Contributed by M R Swami Reddy (MR.Swami.Reddy@nsc.com)
 
    This file is part of the GNU opcodes library.
@@ -160,11 +160,11 @@ const inst cr16_instruction[] =
 /* Create a conditional branch instruction.  */
 #define  BRANCH_INST(NAME, OPC)                                       \
   /* opc4 c4 dispe9 */                                                \
-  {NAME,  1, OPC, 28, BRANCH_INS, {{cc,20}, {dispe9,16}}},            \
+  {NAME,  1, OPC, 28, BRANCH_INS | RELAXABLE, {{cc,20}, {dispe9,16}}},\
   /* opc4 c4 disps17 */                                               \
-  {NAME,  2, ((OPC<<4)+0x8), 24, BRANCH_INS, {{cc,20}, {disps17,0}}}, \
+  {NAME,  2, ((OPC<<4)+0x8), 24, BRANCH_INS | RELAXABLE, {{cc,20}, {disps17,0}}},\
   /* opc4 c4 disps25 */                                               \
-  {NAME,  3, (OPC<<4), 16 , BRANCH_INS, {{cc,4}, {disps25,16}}}
+  {NAME,  3, (OPC<<4), 16 , BRANCH_INS | RELAXABLE, {{cc,4}, {disps25,16}}}
 
   BRANCH_INST ("b", 0x1),
 
@@ -593,6 +593,7 @@ const operand_entry cr16_optab[] =
   {4,    arg_cc,       OP_UNSIGNED}               /* cc - code */
 };
 
+const unsigned int cr16_num_optab = ARRAY_SIZE (cr16_optab);
 
 /* CR16 traps/interrupts.  */
 const trap_entry cr16_traps[] =