X-Git-Url: https://oss.titaniummirror.com/gitweb?p=msp430-binutils.git;a=blobdiff_plain;f=opcodes%2Fia64-dis.c;fp=opcodes%2Fia64-dis.c;h=13ee194925893fcf84041b01e11103b009740810;hp=146464fecbaacce2e346158b3a732a1589f802ef;hb=d5da4f291af551c0b8b79e1d4a9b173d60e5c10e;hpb=7b5ea4fcdf2819e070665ab5610f8b48e3867c10

diff --git a/opcodes/ia64-dis.c b/opcodes/ia64-dis.c
index 146464f..13ee194 100644
--- a/opcodes/ia64-dis.c
+++ b/opcodes/ia64-dis.c
@@ -1,5 +1,6 @@
 /* ia64-dis.c -- Disassemble ia64 instructions
-   Copyright 1998, 1999, 2000, 2002, 2007 Free Software Foundation, Inc.
+   Copyright 1998, 1999, 2000, 2002, 2005, 2007, 2008, 2009
+   Free Software Foundation, Inc.
    Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
 
    This file is part of the GNU opcodes library.
@@ -68,7 +69,7 @@ unit_to_type (ia64_insn opcode, enum ia64_unit unit)
 int
 print_insn_ia64 (bfd_vma memaddr, struct disassemble_info *info)
 {
-  ia64_insn t0, t1, slot[3], template, s_bit, insn;
+  ia64_insn t0, t1, slot[3], template_val, s_bit, insn;
   int slotnum, j, status, need_comma, retval, slot_multiplier;
   const struct ia64_operand *odesc;
   const struct ia64_opcode *idesc;
@@ -100,20 +101,20 @@ print_insn_ia64 (bfd_vma memaddr, struct disassemble_info *info)
   t0 = bfd_getl64 (bundle);
   t1 = bfd_getl64 (bundle + 8);
   s_bit = t0 & 1;
-  template = (t0 >> 1) & 0xf;
+  template_val = (t0 >> 1) & 0xf;
   slot[0] = (t0 >>  5) & 0x1ffffffffffLL;
   slot[1] = ((t0 >> 46) & 0x3ffff) | ((t1 & 0x7fffff) << 18);
   slot[2] = (t1 >> 23) & 0x1ffffffffffLL;
 
-  tname = ia64_templ_desc[template].name;
+  tname = ia64_templ_desc[template_val].name;
   if (slotnum == 0)
     (*info->fprintf_func) (info->stream, "[%s] ", tname);
   else
     (*info->fprintf_func) (info->stream, "      ");
 
-  unit = ia64_templ_desc[template].exec_unit[slotnum];
+  unit = ia64_templ_desc[template_val].exec_unit[slotnum];
 
-  if (template == 2 && slotnum == 1)
+  if (template_val == 2 && slotnum == 1)
     {
       /* skip L slot in MLI template: */
       slotnum = 2;
@@ -182,7 +183,7 @@ print_insn_ia64 (bfd_vma memaddr, struct disassemble_info *info)
 	    }
 	}
 
-	switch (odesc->class)
+	switch (odesc->op_class)
 	  {
 	  case IA64_OPND_CLASS_CST:
 	    (*info->fprintf_func) (info->stream, "%s", odesc->str);
@@ -201,10 +202,19 @@ print_insn_ia64 (bfd_vma memaddr, struct disassemble_info *info)
 		  case 17:	strcpy (regname, "ar.bsp"); break;
 		  case 18:	strcpy (regname, "ar.bspstore"); break;
 		  case 19:	strcpy (regname, "ar.rnat"); break;
+		  case 21:	strcpy (regname, "ar.fcr"); break;
+		  case 24:	strcpy (regname, "ar.eflag"); break;
+		  case 25:	strcpy (regname, "ar.csd"); break;
+		  case 26:	strcpy (regname, "ar.ssd"); break;
+		  case 27:	strcpy (regname, "ar.cflg"); break;
+		  case 28:	strcpy (regname, "ar.fsr"); break;
+		  case 29:	strcpy (regname, "ar.fir"); break;
+		  case 30:	strcpy (regname, "ar.fdr"); break;
 		  case 32:	strcpy (regname, "ar.ccv"); break;
 		  case 36:	strcpy (regname, "ar.unat"); break;
 		  case 40:	strcpy (regname, "ar.fpsr"); break;
 		  case 44:	strcpy (regname, "ar.itc"); break;
+		  case 45:	strcpy (regname, "ar.ruc"); break;
 		  case 64:	strcpy (regname, "ar.pfs"); break;
 		  case 65:	strcpy (regname, "ar.lc"); break;
 		  case 66:	strcpy (regname, "ar.ec"); break;
@@ -214,6 +224,44 @@ print_insn_ia64 (bfd_vma memaddr, struct disassemble_info *info)
 		  }
 		(*info->fprintf_func) (info->stream, "%s", regname);
 	      }
+	    else if (odesc->str[0] == 'c' && odesc->str[1] == 'r')
+	      {
+		switch (value)
+		  {
+		  case 0:       strcpy (regname, "cr.dcr"); break;
+		  case 1:       strcpy (regname, "cr.itm"); break;
+		  case 2:       strcpy (regname, "cr.iva"); break;
+		  case 8:       strcpy (regname, "cr.pta"); break;
+		  case 16:      strcpy (regname, "cr.ipsr"); break;
+		  case 17:      strcpy (regname, "cr.isr"); break;
+		  case 19:      strcpy (regname, "cr.iip"); break;
+		  case 20:      strcpy (regname, "cr.ifa"); break;
+		  case 21:      strcpy (regname, "cr.itir"); break;
+		  case 22:      strcpy (regname, "cr.iipa"); break;
+		  case 23:      strcpy (regname, "cr.ifs"); break;
+		  case 24:      strcpy (regname, "cr.iim"); break;
+		  case 25:      strcpy (regname, "cr.iha"); break;
+		  case 26:      strcpy (regname, "cr.iib0"); break;
+		  case 27:      strcpy (regname, "cr.iib1"); break;
+		  case 64:      strcpy (regname, "cr.lid"); break;
+		  case 65:      strcpy (regname, "cr.ivr"); break;
+		  case 66:      strcpy (regname, "cr.tpr"); break;
+		  case 67:      strcpy (regname, "cr.eoi"); break;
+		  case 68:      strcpy (regname, "cr.irr0"); break;
+		  case 69:      strcpy (regname, "cr.irr1"); break;
+		  case 70:      strcpy (regname, "cr.irr2"); break;
+		  case 71:      strcpy (regname, "cr.irr3"); break;
+		  case 72:      strcpy (regname, "cr.itv"); break;
+		  case 73:      strcpy (regname, "cr.pmv"); break;
+		  case 74:      strcpy (regname, "cr.cmcv"); break;
+		  case 80:      strcpy (regname, "cr.lrr0"); break;
+		  case 81:      strcpy (regname, "cr.lrr1"); break;
+		  default:
+		    sprintf (regname, "cr%u", (unsigned int) value);
+		    break;
+		  }
+		(*info->fprintf_func) (info->stream, "%s", regname);
+	      }
 	    else
 	      (*info->fprintf_func) (info->stream, "%s%d", odesc->str, (int)value);
 	    break;
@@ -256,7 +304,7 @@ print_insn_ia64 (bfd_vma memaddr, struct disassemble_info *info)
 	  need_comma = 0;
 	}
     }
-  if (slotnum + 1 == ia64_templ_desc[template].group_boundary 
+  if (slotnum + 1 == ia64_templ_desc[template_val].group_boundary 
       || ((slotnum == 2) && s_bit))
     (*info->fprintf_func) (info->stream, ";;");