tos/chips/atm1281/HplAtm128UartP.nc

   1 /*
   2  * Copyright (c) 2006 Arch Rock Corporation
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * - Redistributions of source code must retain the above copyright
   9  *   notice, this list of conditions and the following disclaimer.
  10  * - Redistributions in binary form must reproduce the above copyright
  11  *   notice, this list of conditions and the following disclaimer in the
  12  *   documentation and/or other materials provided with the
  13  *   distribution.
  14  * - Neither the name of the Arch Rock Corporation nor the names of
  15  *   its contributors may be used to endorse or promote products derived
  16  *   from this software without specific prior written permission.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  19  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  20  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  21  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
  22  * ARCH ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  23  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  24  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  25  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  26  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  27  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  29  * OF THE POSSIBILITY OF SUCH DAMAGE
  30  */
  31
  32 /**
  33  * @author Alec Woo <awoo@archrock.com>
  34  * @author Jonathan Hui <jhui@archrock.com>
  35  * @version $Revision$ $Date$
  36  */
  37
  38 /*
  39  * Copyright (c) 2004-2005 Crossbow Technology, Inc.  All rights reserved.
  40  *
  41  * Permission to use, copy, modify, and distribute this software and its
  42  * documentation for any purpose, without fee, and without written agreement is
  43  * hereby granted, provided that the above copyright notice, the following
  44  * two paragraphs and the author appear in all copies of this software.
  45  *
  46  * IN NO EVENT SHALL CROSSBOW TECHNOLOGY OR ANY OF ITS LICENSORS BE LIABLE TO
  47  * ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
  48  * DAMAGES ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN
  49  * IF CROSSBOW OR ITS LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
  50  * DAMAGE.
  51  *
  52  * CROSSBOW TECHNOLOGY AND ITS LICENSORS SPECIFICALLY DISCLAIM ALL WARRANTIES,
  53  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
  54  * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS
  55  * ON AN "AS IS" BASIS, AND NEITHER CROSSBOW NOR ANY LICENSOR HAS ANY
  56  * OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR
  57  * MODIFICATIONS.
  58  */
  59
  60 /*
  61  * Copyright (c) 2007, Vanderbilt University
  62  * All rights reserved.
  63  *
  64  * Permission to use, copy, modify, and distribute this software and its
  65  * documentation for any purpose, without fee, and without written agreement is
  66  * hereby granted, provided that the above copyright notice, the following
  67  * two paragraphs and the author appear in all copies of this software.
  68  *
  69  * IN NO EVENT SHALL THE VANDERBILT UNIVERSITY BE LIABLE TO ANY PARTY FOR
  70  * DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT
  71  * OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE VANDERBILT
  72  * UNIVERSITY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  73  *
  74  * THE VANDERBILT UNIVERSITY SPECIFICALLY DISCLAIMS ANY WARRANTIES,
  75  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
  76  * AND FITNESS FOR A PARTICULAR PURPOSE.  THE SOFTWARE PROVIDED HEREUNDER IS
  77  * ON AN "AS IS" BASIS, AND THE VANDERBILT UNIVERSITY HAS NO OBLIGATION TO
  78  * PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
  79  *
  80  */
  81
  82 /**
  83  * Private component of the Atmega1281 serial port HPL.
  84  *
  85  * @author Martin Turon <mturon@xbow.com>
  86  * @author David Gay
  87  * @author Janos Sallai <janos.sallai@vanderbilt.edu>
  88  */
  89
  90 #include <Atm128Uart.h>
  91
  92 module HplAtm128UartP {
  93
  94   provides interface Init as Uart0Init;
  95   provides interface StdControl as Uart0TxControl;
  96   provides interface StdControl as Uart0RxControl;
  97   provides interface HplAtm128Uart as HplUart0;
  98
  99   provides interface Init as Uart1Init;
 100   provides interface StdControl as Uart1TxControl;
 101   provides interface StdControl as Uart1RxControl;
 102   provides interface HplAtm128Uart as HplUart1;
 103
 104   uses interface Atm128Calibrate;
 105   uses interface McuPowerState;
 106 }
 107 implementation {
 108
 109   //=== Uart Init Commands. ====================================
 110   command error_t Uart0Init.init() {
 111     Atm128UartMode_t    mode;
 112     Atm128UartStatus_t  stts;
 113     Atm128UartControl_t ctrl;
 114     uint16_t ubrr0;
 115
 116     ctrl.bits = (struct Atm128_UCSRB_t) {rxcie:0, txcie:0, rxen:0, txen:0};
 117     stts.bits = (struct Atm128_UCSRA_t) {u2x:1};
 118     mode.bits = (struct Atm128_UCSRC_t) {ucsz:ATM128_UART_DATA_SIZE_8_BITS};
 119
 120     ubrr0 = call Atm128Calibrate.baudrateRegister(PLATFORM_BAUDRATE);
 121     UBRR0L = ubrr0;
 122     UBRR0H = ubrr0 >> 8;
 123     UCSR0A = stts.flat;
 124     UCSR0C = mode.flat;
 125     UCSR0B = ctrl.flat;
 126
 127     return SUCCESS;
 128   }
 129
 130   command error_t Uart0TxControl.start() {
 131     SET_BIT(UCSR0B, TXEN0);
 132     call McuPowerState.update();
 133     return SUCCESS;
 134   }
 135
 136   command error_t Uart0TxControl.stop() {
 137     CLR_BIT(UCSR0B, TXEN0);
 138     call McuPowerState.update();
 139     return SUCCESS;
 140   }
 141
 142   command error_t Uart0RxControl.start() {
 143     SET_BIT(UCSR0B, RXEN0);
 144     call McuPowerState.update();
 145     return SUCCESS;
 146   }
 147
 148   command error_t Uart0RxControl.stop() {
 149     CLR_BIT(UCSR0B, RXEN0);
 150     call McuPowerState.update();
 151     return SUCCESS;
 152   }
 153
 154   async command error_t HplUart0.enableTxIntr() {
 155     SET_BIT(UCSR0A, TXC0);
 156     SET_BIT(UCSR0B, TXCIE0);
 157     return SUCCESS;
 158   }
 159
 160   async command error_t HplUart0.disableTxIntr(){
 161     CLR_BIT(UCSR0B, TXCIE0);
 162     return SUCCESS;
 163   }
 164
 165   async command error_t HplUart0.enableRxIntr(){
 166     SET_BIT(UCSR0B, RXCIE0);
 167     return SUCCESS;
 168   }
 169
 170   async command error_t HplUart0.disableRxIntr(){
 171     CLR_BIT(UCSR0B, RXCIE0);
 172     return SUCCESS;
 173   }
 174
 175   async command bool HplUart0.isTxEmpty(){
 176     return READ_BIT(UCSR0A, TXC0);
 177   }
 178
 179   async command bool HplUart0.isRxEmpty(){
 180     return !READ_BIT(UCSR0A, RXC0);
 181   }
 182
 183   async command uint8_t HplUart0.rx(){
 184     return UDR0;
 185   }
 186
 187   async command void HplUart0.tx(uint8_t data) {
 188     atomic{
 189       UDR0 = data;
 190       SET_BIT(UCSR0A, TXC0);
 191     }
 192   }
 193
 194   AVR_ATOMIC_HANDLER(SIG_USART0_RECV) {
 195     if (READ_BIT(UCSR0A, RXC0)) {
 196       signal HplUart0.rxDone(UDR0);
 197     }
 198   }
 199
 200   AVR_NONATOMIC_HANDLER(SIG_USART0_TRANS) {
 201     signal HplUart0.txDone();
 202   }
 203
 204   command error_t Uart1Init.init() {
 205     Atm128UartMode_t    mode;
 206     Atm128UartStatus_t  stts;
 207     Atm128UartControl_t ctrl;
 208     uint16_t ubrr1;
 209
 210     ctrl.bits = (struct Atm128_UCSRB_t) {rxcie:0, txcie:0, rxen:0, txen:0};
 211     stts.bits = (struct Atm128_UCSRA_t) {u2x:1};
 212     mode.bits = (struct Atm128_UCSRC_t) {ucsz:ATM128_UART_DATA_SIZE_8_BITS};
 213
 214     ubrr1 = call Atm128Calibrate.baudrateRegister(PLATFORM_BAUDRATE);
 215     UBRR1L = ubrr1;
 216     UBRR1H = ubrr1 >> 8;
 217     UCSR1A = stts.flat;
 218     UCSR1C = mode.flat;
 219     UCSR1B = ctrl.flat;
 220
 221     return SUCCESS;
 222   }
 223
 224   command error_t Uart1TxControl.start() {
 225     SET_BIT(UCSR1B, TXEN1);
 226     call McuPowerState.update();
 227     return SUCCESS;
 228   }
 229
 230   command error_t Uart1TxControl.stop() {
 231     CLR_BIT(UCSR1B, TXEN1);
 232     call McuPowerState.update();
 233     return SUCCESS;
 234   }
 235
 236   command error_t Uart1RxControl.start() {
 237     SET_BIT(UCSR1B, RXEN1);
 238     call McuPowerState.update();
 239     return SUCCESS;
 240   }
 241
 242   command error_t Uart1RxControl.stop() {
 243     CLR_BIT(UCSR1B, RXEN1);
 244     call McuPowerState.update();
 245     return SUCCESS;
 246   }
 247
 248   async command error_t HplUart1.enableTxIntr() {
 249     SET_BIT(UCSR1A, TXC1);
 250     SET_BIT(UCSR1B, TXCIE1);
 251     return SUCCESS;
 252   }
 253
 254   async command error_t HplUart1.disableTxIntr(){
 255     CLR_BIT(UCSR1B, TXCIE1);
 256     return SUCCESS;
 257   }
 258
 259   async command error_t HplUart1.enableRxIntr(){
 260     SET_BIT(UCSR1B, RXCIE1);
 261     return SUCCESS;
 262   }
 263
 264   async command error_t HplUart1.disableRxIntr(){
 265     CLR_BIT(UCSR1B, RXCIE1);
 266     return SUCCESS;
 267   }
 268
 269   async command bool HplUart1.isTxEmpty() {
 270     return READ_BIT(UCSR1A, TXC1);
 271   }
 272
 273   async command bool HplUart1.isRxEmpty() {
 274     return !READ_BIT(UCSR1A, RXC1);
 275   }
 276
 277   async command uint8_t HplUart1.rx(){
 278     return UDR1;
 279   }
 280
 281   async command void HplUart1.tx(uint8_t data) {
 282     atomic{
 283       UDR1 = data;
 284       SET_BIT(UCSR1A, TXC1);
 285     }
 286   }
 287
 288   AVR_ATOMIC_HANDLER(SIG_USART1_RECV) {
 289     if (READ_BIT(UCSR1A, RXC1))
 290       signal HplUart1.rxDone(UDR1);
 291   }
 292
 293   AVR_NONATOMIC_HANDLER(SIG_USART1_TRANS) {
 294     signal HplUart1.txDone();
 295   }
 296
 297   default async event void HplUart0.txDone() {}
 298   default async event void HplUart0.rxDone(uint8_t data) {}
 299   default async event void HplUart1.txDone() {}
 300   default async event void HplUart1.rxDone(uint8_t data) {}
 301
 302 }