tos/chips/rf230/RF230.h

   1 /*
   2  * Copyright (c) 2007, Vanderbilt University
   3  * All rights reserved.
   4  *
   5  * Permission to use, copy, modify, and distribute this software and its
   6  * documentation for any purpose, without fee, and without written agreement is
   7  * hereby granted, provided that the above copyright notice, the following
   8  * two paragraphs and the author appear in all copies of this software.
   9  *
  10  * IN NO EVENT SHALL THE VANDERBILT UNIVERSITY BE LIABLE TO ANY PARTY FOR
  11  * DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT
  12  * OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE VANDERBILT
  13  * UNIVERSITY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  14  *
  15  * THE VANDERBILT UNIVERSITY SPECIFICALLY DISCLAIMS ANY WARRANTIES,
  16  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
  17  * AND FITNESS FOR A PARTICULAR PURPOSE.  THE SOFTWARE PROVIDED HEREUNDER IS
  18  * ON AN "AS IS" BASIS, AND THE VANDERBILT UNIVERSITY HAS NO OBLIGATION TO
  19  * PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
  20  *
  21  * Author: Miklos Maroti
  22  */
  23
  24 #ifndef __RF230_H__
  25 #define __RF230_H__
  26
  27 enum rf230_registers_enum
  28 {
  29         RF230_TRX_STATUS = 0x01,
  30         RF230_TRX_STATE = 0x02,
  31         RF230_TRX_CTRL_0 = 0x03,
  32         RF230_PHY_TX_PWR = 0x05,
  33         RF230_PHY_RSSI = 0x06,
  34         RF230_PHY_ED_LEVEL = 0x07,
  35         RF230_PHY_CC_CCA = 0x08,
  36         RF230_CCA_THRES = 0x09,
  37         RF230_IRQ_MASK = 0x0E,
  38         RF230_IRQ_STATUS = 0x0F,
  39         RF230_VREG_CTRL = 0x10,
  40         RF230_BATMON = 0x11,
  41         RF230_XOSC_CTRL = 0x12,
  42         RF230_PLL_CF = 0x1A,
  43         RF230_PLL_DCU = 0x1B,
  44         RF230_PART_NUM = 0x1C,
  45         RF230_VERSION_NUM = 0x1D,
  46         RF230_MAN_ID_0 = 0x1E,
  47         RF230_MAN_ID_1 = 0x1F,
  48         RF230_SHORT_ADDR_0 = 0x20,
  49         RF230_SHORT_ADDR_1 = 0x21,
  50         RF230_PAN_ID_0 = 0x22,
  51         RF230_PAN_ID_1 = 0x23,
  52         RF230_IEEE_ADDR_0 = 0x24,
  53         RF230_IEEE_ADDR_1 = 0x25,
  54         RF230_IEEE_ADDR_2 = 0x26,
  55         RF230_IEEE_ADDR_3 = 0x27,
  56         RF230_IEEE_ADDR_4 = 0x28,
  57         RF230_IEEE_ADDR_5 = 0x29,
  58         RF230_IEEE_ADDR_6 = 0x2A,
  59         RF230_IEEE_ADDR_7 = 0x2B,
  60         RF230_XAH_CTRL = 0x2C,
  61         RF230_CSMA_SEED_0 = 0x2D,
  62         RF230_CSMA_SEED_1 = 0x2E,
  63 };
  64
  65 enum rf230_trx_register_enums
  66 {
  67         RF230_CCA_DONE = 1 << 7,
  68         RF230_CCA_STATUS = 1 << 6,
  69         RF230_TRX_STATUS_MASK = 0x1F,
  70         RF230_P_ON = 0,
  71         RF230_BUSY_RX = 1,
  72         RF230_BUSY_TX = 2,
  73         RF230_RX_ON = 6,
  74         RF230_TRX_OFF = 8,
  75         RF230_PLL_ON = 9,
  76         RF230_SLEEP = 15,
  77         RF230_BUSY_RX_AACK = 16,
  78         RF230_BUSR_TX_ARET = 17,
  79         RF230_RX_AACK_ON = 22,
  80         RF230_TX_ARET_ON = 25,
  81         RF230_RX_ON_NOCLK = 28,
  82         RF230_AACK_ON_NOCLK = 29,
  83         RF230_BUSY_RX_AACK_NOCLK = 30,
  84         RF230_STATE_TRANSITION_IN_PROGRESS = 31,
  85         RF230_TRAC_STATUS_MASK = 0xE0,
  86         RF230_TRAC_SUCCESS = 0,
  87         RF230_TRAC_CHANNEL_ACCESS_FAILURE = 3 << 5,
  88         RF230_TRAC_NO_ACK = 5 << 5,
  89         RF230_TRX_CMD_MASK = 0x1F,
  90         RF230_NOP = 0,
  91         RF230_TX_START = 2,
  92         RF230_FORCE_TRX_OFF = 3,
  93 };
  94
  95 enum rf230_phy_register_enums
  96 {
  97         RF230_TX_AUTO_CRC_ON = 1 << 7,
  98         RF230_TX_PWR_MASK = 0x0F,
  99         RF230_TX_PWR_DEFAULT = 0,
 100         RF230_RSSI_MASK = 0x1F,
 101         RF230_CCA_REQUEST = 1 << 7,
 102         RF230_CCA_MODE_0 = 0 << 5,
 103         RF230_CCA_MODE_1 = 1 << 5,
 104         RF230_CCA_MODE_2 = 2 << 5,
 105         RF230_CCA_MODE_3 = 3 << 5,
 106         RF230_CHANNEL_DEFAULT = 11,
 107         RF230_CHANNEL_MASK = 0x1F,
 108         RF230_CCA_CS_THRES_SHIFT = 4,
 109         RF230_CCA_ED_THRES_SHIFT = 0,
 110 };
 111
 112 enum rf230_irq_register_enums
 113 {
 114         RF230_IRQ_BAT_LOW = 1 << 7,
 115         RF230_IRQ_TRX_UR = 1 << 6,
 116         RF230_IRQ_TRX_END = 1 << 3,
 117         RF230_IRQ_RX_START = 1 << 2,
 118         RF230_IRQ_PLL_UNLOCK = 1 << 1,
 119         RF230_IRQ_PLL_LOCK = 1 << 0,
 120 };
 121
 122 enum rf230_control_register_enums
 123 {
 124         RF230_AVREG_EXT = 1 << 7,
 125         RF230_AVDD_OK = 1 << 6,
 126         RF230_DVREG_EXT = 1 << 3,
 127         RF230_DVDD_OK = 1 << 2,
 128         RF230_BATMON_OK = 1 << 5,
 129         RF230_BATMON_VHR = 1 << 4,
 130         RF230_BATMON_VTH_MASK = 0x0F,
 131         RF230_XTAL_MODE_OFF = 0 << 4,
 132         RF230_XTAL_MODE_EXTERNAL = 4 << 4,
 133         RF230_XTAL_MODE_INTERNAL = 15 << 4,
 134 };
 135
 136 enum rf230_pll_register_enums
 137 {
 138         RF230_PLL_CF_START = 1 << 7,
 139         RF230_PLL_DCU_START = 1 << 7,
 140 };
 141
 142 enum rf230_spi_command_enums
 143 {
 144         RF230_CMD_REGISTER_READ = 0x80,
 145         RF230_CMD_REGISTER_WRITE = 0xC0,
 146         RF230_CMD_REGISTER_MASK = 0x3F,
 147         RF230_CMD_FRAME_READ = 0x20,
 148         RF230_CMD_FRAME_WRITE = 0x60,
 149         RF230_CMD_SRAM_READ = 0x00,
 150         RF230_CMD_SRAM_WRITE = 0x40,
 151 };
 152
 153 #endif//__RF230_H__