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* hereby granted, provided that the above copyright notice, the following
* two paragraphs and the author appear in all copies of this software.
* documentation for any purpose, without fee, and without written agreement is
* hereby granted, provided that the above copyright notice, the following
* two paragraphs and the author appear in all copies of this software.
- *
- * IN NO EVENT SHALL CROSSBOW TECHNOLOGY OR ANY OF ITS LICENSORS BE LIABLE TO
- * ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+ *
+ * IN NO EVENT SHALL CROSSBOW TECHNOLOGY OR ANY OF ITS LICENSORS BE LIABLE TO
+ * ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
- * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
- * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS
- * ON AN "AS IS" BASIS, AND NEITHER CROSSBOW NOR ANY LICENSOR HAS ANY
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- * MODIFICATIONS.
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS
+ * ON AN "AS IS" BASIS, AND NEITHER CROSSBOW NOR ANY LICENSOR HAS ANY
+ * OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR
+ * MODIFICATIONS.
* documentation for any purpose, without fee, and without written agreement is
* hereby granted, provided that the above copyright notice, the following
* two paragraphs and the author appear in all copies of this software.
* documentation for any purpose, without fee, and without written agreement is
* hereby granted, provided that the above copyright notice, the following
* two paragraphs and the author appear in all copies of this software.
* IN NO EVENT SHALL THE VANDERBILT UNIVERSITY BE LIABLE TO ANY PARTY FOR
* DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT
* OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE VANDERBILT
* UNIVERSITY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* IN NO EVENT SHALL THE VANDERBILT UNIVERSITY BE LIABLE TO ANY PARTY FOR
* DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT
* OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE VANDERBILT
* UNIVERSITY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* THE VANDERBILT UNIVERSITY SPECIFICALLY DISCLAIMS ANY WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
* AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS
* THE VANDERBILT UNIVERSITY SPECIFICALLY DISCLAIMS ANY WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
* AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS
provides interface HplAtm128Adc;
uses interface McuPowerState;
}
implementation {
//=== Direct read of HW registers. =================================
provides interface HplAtm128Adc;
uses interface McuPowerState;
}
implementation {
//=== Direct read of HW registers. =================================
}
DEFINE_UNION_CAST(Admux2int, Atm128Admux_t, uint8_t);
DEFINE_UNION_CAST(Adcsra2int, Atm128Adcsra_t, uint8_t);
//=== Direct write of HW registers. ================================
}
DEFINE_UNION_CAST(Admux2int, Atm128Admux_t, uint8_t);
DEFINE_UNION_CAST(Adcsra2int, Atm128Adcsra_t, uint8_t);
//=== Direct write of HW registers. ================================
current_val.adif = FALSE;
current_val.adps = scale;
call HplAtm128Adc.setAdcsra(current_val);
current_val.adif = FALSE;
current_val.adps = scale;
call HplAtm128Adc.setAdcsra(current_val);
// Individual bit manipulation. These all clear any pending A/D interrupt.
// It's not clear these are that useful...
async command void HplAtm128Adc.enableAdc() {
// Individual bit manipulation. These all clear any pending A/D interrupt.
// It's not clear these are that useful...
async command void HplAtm128Adc.enableAdc() {
call McuPowerState.update();
}
async command void HplAtm128Adc.enableInterruption() { SET_BIT(ADCSRA, ADIE); }
async command void HplAtm128Adc.disableInterruption() { CLR_BIT(ADCSRA, ADIE); }
call McuPowerState.update();
}
async command void HplAtm128Adc.enableInterruption() { SET_BIT(ADCSRA, ADIE); }
async command void HplAtm128Adc.disableInterruption() { CLR_BIT(ADCSRA, ADIE); }
}
/* A/D interrupt handlers. Signals dataReady event with interrupts enabled */
AVR_ATOMIC_HANDLER(SIG_ADC) {
uint16_t data = call HplAtm128Adc.getValue();
}
/* A/D interrupt handlers. Signals dataReady event with interrupts enabled */
AVR_ATOMIC_HANDLER(SIG_ADC) {
uint16_t data = call HplAtm128Adc.getValue();
__nesc_enable_interrupt();
signal HplAtm128Adc.dataReady(data);
}
default async event void HplAtm128Adc.dataReady(uint16_t done) { }
__nesc_enable_interrupt();
signal HplAtm128Adc.dataReady(data);
}
default async event void HplAtm128Adc.dataReady(uint16_t done) { }