ctl0: UCSYNC | UCMODE_0 | UCMST, /* 3-pin SPI mode 0, LSB first */
ctl1: UCSWRST | UCSSEL_3, /* SPI clock source is SMCLK */
brx: 10, /* SPI clock=SMCLK/10; ~105KHz if SMCLK=1MHz */
ctl0: UCSYNC | UCMODE_0 | UCMST, /* 3-pin SPI mode 0, LSB first */
ctl1: UCSWRST | UCSSEL_3, /* SPI clock source is SMCLK */
brx: 10, /* SPI clock=SMCLK/10; ~105KHz if SMCLK=1MHz */