* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/* Clear interrupts; we'll add them as needed */
call Registers.clrIeRx();
call Registers.clrIeTx();
/* Clear interrupts; we'll add them as needed */
call Registers.clrIeRx();
call Registers.clrIeTx();
/* FIXME: this can cause an arbitrarily long ISR, if m_slen is large.
* But depending on timing, we may always only write 1 byte.
*/
/* FIXME: this can cause an arbitrarily long ISR, if m_slen is large.
* But depending on timing, we may always only write 1 byte.
*/
- while (!call Registers.getIfgTx()); /* in case interleaved UB.send */
- while (m_slen && call Registers.getIfgTx()) {
- call Registers.setTxbuf(*m_sbuf);
- if (--m_slen)
- m_sbuf++;
- }
- if (m_slen == 0) {
- call Registers.clrIeTx();
- m_sobuf = 0;
- signal UartStream.sendDone(m_sobuf, m_solen, SUCCESS);
+ if (m_sobuf) {
+ while (!call Registers.getIfgTx()); /* in case interleaved UB.send */
+ while (m_slen && call Registers.getIfgTx()) {
+ call Registers.setTxbuf(*m_sbuf);
+ if (--m_slen)
+ m_sbuf++;
+ }
+ if (m_slen == 0) {
+ call Registers.clrIeTx();
+ m_sobuf = 0;
+ signal UartStream.sendDone(m_sobuf, m_solen, SUCCESS);
+ }
ctl0: UCMODE_0, /* async, lsb first, 8N1 */
ctl1: UCSWRST | UCSSEL_3, /* clock uart from SMCLK */
brx: UBRX_1MHZ_115200,
ctl0: UCMODE_0, /* async, lsb first, 8N1 */
ctl1: UCSWRST | UCSSEL_3, /* clock uart from SMCLK */
brx: UBRX_1MHZ_115200,