--- /dev/null
+// $Id$\r
+\r
+/* -*- Mode: C; c-basic-indent: 2; indent-tabs-mode: nil -*- */ \r
+/* tab:4\r
+ * IMPORTANT: READ BEFORE DOWNLOADING, COPYING, INSTALLING OR USING. By\r
+ * downloading, copying, installing or using the software you agree to\r
+ * this license. If you do not agree to this license, do not download,\r
+ * install, copy or use the software.\r
+ *\r
+ * Intel Open Source License \r
+ *\r
+ * Copyright (c) 2002 Intel Corporation \r
+ * All rights reserved. \r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are\r
+ * met:\r
+ * \r
+ * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ * Neither the name of the Intel Corporation nor the names of its\r
+ * contributors may be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ * \r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A\r
+ * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL OR ITS\r
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR\r
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * \r
+ * \r
+ */\r
+\r
+/*\r
+ * Constants for CC1000 radio\r
+ *\r
+ * @author Phil Buonadonna\r
+ */\r
+\r
+#ifndef CC1000CONST_H\r
+#define CC1000CONST_H\r
+\r
+/* Constants defined for CC1K */\r
+/* Register addresses */\r
+\r
+enum {\r
+ CC1K_MAIN = 0x00,\r
+ CC1K_FREQ_2A = 0x01,\r
+ CC1K_FREQ_1A = 0x02,\r
+ CC1K_FREQ_0A = 0x03,\r
+ CC1K_FREQ_2B = 0x04,\r
+ CC1K_FREQ_1B = 0x05,\r
+ CC1K_FREQ_0B = 0x06,\r
+ CC1K_FSEP1 = 0x07,\r
+ CC1K_FSEP0 = 0x08,\r
+ CC1K_CURRENT = 0x09,\r
+ CC1K_FRONT_END = 0x0A, //10\r
+ CC1K_PA_POW = 0x0B, //11\r
+ CC1K_PLL = 0x0C, //12\r
+ CC1K_LOCK = 0x0D, //13\r
+ CC1K_CAL = 0x0E, //14\r
+ CC1K_MODEM2 = 0x0F, //15\r
+ CC1K_MODEM1 = 0x10, //16\r
+ CC1K_MODEM0 = 0x11, //17\r
+ CC1K_MATCH = 0x12, //18\r
+ CC1K_FSCTRL = 0x13, //19\r
+ CC1K_FSHAPE7 = 0x14, //20\r
+ CC1K_FSHAPE6 = 0x15, //21\r
+ CC1K_FSHAPE5 = 0x16, //22\r
+ CC1K_FSHAPE4 = 0x17, //23\r
+ CC1K_FSHAPE3 = 0x18, //24\r
+ CC1K_FSHAPE2 = 0x19, //25\r
+ CC1K_FSHAPE1 = 0x1A, //26\r
+ CC1K_FSDELAY = 0x1B, //27\r
+ CC1K_PRESCALER = 0x1C, //28\r
+ CC1K_TEST6 = 0x40, //64\r
+ CC1K_TEST5 = 0x41, //66\r
+ CC1K_TEST4 = 0x42, //67\r
+ CC1K_TEST3 = 0x43, //68\r
+ CC1K_TEST2 = 0x44, //69\r
+ CC1K_TEST1 = 0x45, //70\r
+ CC1K_TEST0 = 0x46, //71\r
+\r
+ // MAIN Register Bit Posititions\r
+ CC1K_RXTX = 7,\r
+ CC1K_F_REG = 6,\r
+ CC1K_RX_PD = 5,\r
+ CC1K_TX_PD = 4,\r
+ CC1K_FS_PD = 3,\r
+ CC1K_CORE_PD = 2,\r
+ CC1K_BIAS_PD = 1,\r
+ CC1K_RESET_N = 0,\r
+\r
+ // CURRENT Register Bit Positions\r
+ CC1K_VCO_CURRENT = 4,\r
+ CC1K_LO_DRIVE = 2,\r
+ CC1K_PA_DRIVE = 0,\r
+\r
+ // FRONT_END Register Bit Positions\r
+ CC1K_BUF_CURRENT = 5,\r
+ CC1K_LNA_CURRENT = 3,\r
+ CC1K_IF_RSSI = 1,\r
+ CC1K_XOSC_BYPASS = 0,\r
+\r
+ // PA_POW Register Bit Positions\r
+ CC1K_PA_HIGHPOWER = 4,\r
+ CC1K_PA_LOWPOWER = 0,\r
+\r
+ // PLL Register Bit Positions\r
+ CC1K_EXT_FILTER = 7,\r
+ CC1K_REFDIV = 3,\r
+ CC1K_ALARM_DISABLE = 2,\r
+ CC1K_ALARM_H = 1,\r
+ CC1K_ALARM_L = 0,\r
+\r
+ // LOCK Register Bit Positions\r
+ CC1K_LOCK_SELECT = 4,\r
+ CC1K_PLL_LOCK_ACCURACY = 3,\r
+ CC1K_PLL_LOCK_LENGTH = 2,\r
+ CC1K_LOCK_INSTANT = 1,\r
+ CC1K_LOCK_CONTINUOUS = 0,\r
+\r
+ // CAL Register Bit Positions\r
+ CC1K_CAL_START = 7,\r
+ CC1K_CAL_DUAL = 6,\r
+ CC1K_CAL_WAIT = 5,\r
+ CC1K_CAL_CURRENT = 4,\r
+ CC1K_CAL_COMPLETE = 3,\r
+ CC1K_CAL_ITERATE = 0,\r
+\r
+ // MODEM2 Register Bit Positions\r
+ CC1K_PEAKDETECT = 7,\r
+ CC1K_PEAK_LEVEL_OFFSET = 0,\r
+\r
+ // MODEM1 Register Bit Positions\r
+ CC1K_MLIMIT = 5,\r
+ CC1K_LOCK_AVG_IN = 4,\r
+ CC1K_LOCK_AVG_MODE = 3,\r
+ CC1K_SETTLING = 1,\r
+ CC1K_MODEM_RESET_N = 0,\r
+\r
+ // MODEM0 Register Bit Positions\r
+ CC1K_BAUDRATE = 4,\r
+ CC1K_DATA_FORMAT = 2,\r
+ CC1K_XOSC_FREQ = 0,\r
+\r
+ // MATCH Register Bit Positions\r
+ CC1K_RX_MATCH = 4,\r
+ CC1K_TX_MATCH = 0,\r
+\r
+ // FSCTLR Register Bit Positions\r
+ CC1K_DITHER1 = 3,\r
+ CC1K_DITHER0 = 2,\r
+ CC1K_SHAPE = 1,\r
+ CC1K_FS_RESET_N = 0,\r
+\r
+ // PRESCALER Register Bit Positions\r
+ CC1K_PRE_SWING = 6,\r
+ CC1K_PRE_CURRENT = 4,\r
+ CC1K_IF_INPUT = 3,\r
+ CC1K_IF_FRONT = 2,\r
+\r
+ // TEST6 Register Bit Positions\r
+ CC1K_LOOPFILTER_TP1 = 7,\r
+ CC1K_LOOPFILTER_TP2 = 6,\r
+ CC1K_CHP_OVERRIDE = 5,\r
+ CC1K_CHP_CO = 0,\r
+\r
+ // TEST5 Register Bit Positions\r
+ CC1K_CHP_DISABLE = 5,\r
+ CC1K_VCO_OVERRIDE = 4,\r
+ CC1K_VCO_AO = 0,\r
+\r
+ // TEST3 Register Bit Positions\r
+ CC1K_BREAK_LOOP = 4,\r
+ CC1K_CAL_DAC_OPEN = 0,\r
+\r
+\r
+ /* \r
+ * CC1K Register Parameters Table\r
+ *\r
+ * This table follows the same format order as the CC1K register \r
+ * set EXCEPT for the last entry in the table which is the \r
+ * CURRENT register value for TX mode.\r
+ * \r
+ * NOTE: To save RAM space, this table resides in program memory (flash). \r
+ * This has two important implications:\r
+ * 1) You can't write to it (duh!)\r
+ * 2) You must read it using the PRG_RDB(addr) macro. IT CANNOT BE ACCESSED AS AN ORDINARY C ARRAY. \r
+ * \r
+ * Add/remove individual entries below to suit your RF tastes.\r
+ * \r
+ */\r
+ CC1K_433_002_MHZ = 0x00,\r
+ CC1K_915_998_MHZ = 0x01,\r
+ CC1K_434_845_MHZ = 0x02,\r
+ CC1K_914_077_MHZ = 0x03,\r
+ CC1K_315_178_MHZ = 0x04,\r
+\r
+ //#define CC1K_SquelchInit 0x02F8 // 0.90V using the bandgap reference\r
+ CC1K_SquelchInit = 0x120,\r
+ CC1K_SquelchTableSize = 9,\r
+ CC1K_MaxRSSISamples = 5,\r
+ CC1K_Settling = 1,\r
+ CC1K_ValidPrecursor = 2,\r
+ CC1K_SquelchIntervalFast = 128,\r
+ CC1K_SquelchIntervalSlow = 2560,\r
+ CC1K_SquelchCount = 30,\r
+ CC1K_SquelchBuffer = 12,\r
+\r
+ CC1K_LPL_PACKET_TIME = 16,\r
+\r
+ CC1K_LPL_CHECK_TIME = 16, /* In tenth's of milliseconds, this should\r
+ be an approximation of the on-time for\r
+ a LPL check rather than the total check\r
+ time. */\r
+ CC1K_LPL_MIN_INTERVAL = 5, /* In milliseconds, the minimum interval\r
+ between low-power-listening checks */\r
+ CC1K_LPL_MAX_INTERVAL = 10000, /* In milliseconds, the maximum interval\r
+ between low-power-listening checks.\r
+ Arbitrary value, but must be at\r
+ most 32767 because of the way\r
+ sleep interval is stored in outgoing\r
+ messages */\r
+ \r
+ CC1000_MIN_BACKOFF = 2,\r
+ CC1000_BACKOFF_PERIOD = 2,\r
+};\r
+\r
+#ifdef CC1K_DEFAULT_FREQ\r
+#define CC1K_DEF_PRESET (CC1K_DEFAULT_FREQ)\r
+#endif\r
+#ifdef CC1K_MANUAL_FREQ\r
+#define CC1K_DEF_FREQ (CC1K_MANUAL_FREQ)\r
+#endif\r
+\r
+#ifndef CC1K_DEF_PRESET\r
+#define CC1K_DEF_PRESET (CC1K_914_077_MHZ)\r
+#endif \r
+\r
+static const_uint8_t CC1K_Params[6][20] = {\r
+ // (0) 433.002 MHz channel, 19.2 Kbps data, Manchester Encoding, High Side LO\r
+ { // MAIN 0x00\r
+ 0x31,\r
+ // FREQ2A,FREQ1A,FREQ0A 0x01-0x03\r
+ 0x58,0x00,0x00, \r
+ // FREQ2B,FREQ1B,FREQ0B 0x04-0x06\r
+ 0x57,0xf6,0x85, //XBOW\r
+ // FSEP1, FSEP0 0x07-0x08\r
+ 0X03,0x55,\r
+ // CURRENT RX MODE VALUE 0x09 also see below\r
+ 4 << CC1K_VCO_CURRENT | 1 << CC1K_LO_DRIVE, \r
+ // FRONT_END 0x0a\r
+ 1 << CC1K_IF_RSSI,\r
+ // PA_POW 0x0b\r
+ 0x0 << CC1K_PA_HIGHPOWER | 0xf << CC1K_PA_LOWPOWER, \r
+ // PLL 0x0c\r
+ 12 << CC1K_REFDIV, \r
+ // LOCK 0x0d\r
+ 0xe << CC1K_LOCK_SELECT,\r
+ // CAL 0x0e\r
+ 1 << CC1K_CAL_WAIT | 6 << CC1K_CAL_ITERATE, \r
+ // MODEM2 0x0f\r
+ 0 << CC1K_PEAKDETECT | 28 << CC1K_PEAK_LEVEL_OFFSET,\r
+ // MODEM1 0x10\r
+ 3 << CC1K_MLIMIT | 1 << CC1K_LOCK_AVG_MODE | CC1K_Settling << CC1K_SETTLING | 1 << CC1K_MODEM_RESET_N, \r
+ // MODEM0 0x11\r
+ 5 << CC1K_BAUDRATE | 1 << CC1K_DATA_FORMAT | 1 << CC1K_XOSC_FREQ,\r
+ // MATCH 0x12\r
+ 0x7 << CC1K_RX_MATCH | 0x0 << CC1K_TX_MATCH,\r
+ // tx current (extra)\r
+ 8 << CC1K_VCO_CURRENT | 1 << CC1K_PA_DRIVE,\r
+ },\r
+\r
+ // 1 915.9988 MHz channel, 19.2 Kbps data, Manchester Encoding, High Side LO\r
+ { // MAIN 0x00 \r
+ 0x31,\r
+ // FREQ2A,FREQ1A,FREQ0A 0x01-0x03\r
+ 0x7c,0x00,0x00, \r
+ // FREQ2B,FREQ1B,FREQ0B 0x04-0x06\r
+ 0x7b,0xf9,0xae, \r
+ // FSEP1, FSEP0 0x07-0x8\r
+ 0x02,0x38,\r
+ // CURRENT RX MODE VALUE 0x09 also see below\r
+ 8 << CC1K_VCO_CURRENT | 3 << CC1K_LO_DRIVE,\r
+ //0x8C, \r
+ // FRONT_END 0x0a\r
+ 1 << CC1K_BUF_CURRENT | 2 << CC1K_LNA_CURRENT | 1 << CC1K_IF_RSSI,\r
+ //0x32,\r
+ // PA_POW 0x0b\r
+ 0x8 << CC1K_PA_HIGHPOWER | 0x0 << CC1K_PA_LOWPOWER, \r
+ //0xff,\r
+ // PLL 0xc\r
+ 8 << CC1K_REFDIV, \r
+ //0x40,\r
+ // LOCK 0xd\r
+ 0x1 << CC1K_LOCK_SELECT,\r
+ //0x10,\r
+ // CAL 0xe\r
+ 1 << CC1K_CAL_WAIT | 6 << CC1K_CAL_ITERATE, \r
+ //0x26,\r
+ // MODEM2 0xf\r
+ 1 << CC1K_PEAKDETECT | 33 << CC1K_PEAK_LEVEL_OFFSET,\r
+ //0xA1,\r
+ // MODEM1 0x10\r
+ 3 << CC1K_MLIMIT | 1 << CC1K_LOCK_AVG_MODE | CC1K_Settling << CC1K_SETTLING | 1 << CC1K_MODEM_RESET_N, \r
+ //0x6f, \r
+ // MODEM0 0x11\r
+ 5 << CC1K_BAUDRATE | 1 << CC1K_DATA_FORMAT | 1 << CC1K_XOSC_FREQ,\r
+ //0x55,\r
+ // MATCH 0x12\r
+ 0x1 << CC1K_RX_MATCH | 0x0 << CC1K_TX_MATCH,\r
+ // tx current (extra)\r
+ 15 << CC1K_VCO_CURRENT | 3 << CC1K_PA_DRIVE,\r
+ },\r
+\r
+ // 2 434.845200 MHz channel, 19.2 Kbps data, Manchester Encoding, High Side LO\r
+ { // MAIN 0x00\r
+ 0x31,\r
+ // FREQ2A,FREQ1A,FREQ0A 0x01-0x03\r
+ 0x51,0x00,0x00, \r
+ // FREQ2B,FREQ1B,FREQ0B 0x04-0x06\r
+ 0x50,0xf7,0x4F, //XBOW\r
+ // FSEP1, FSEP0 0x07-0x08\r
+ 0X03,0x0E,\r
+ // CURRENT RX MODE VALUE 0x09 also see below\r
+ 4 << CC1K_VCO_CURRENT | 1 << CC1K_LO_DRIVE, \r
+ // FRONT_END 0x0a\r
+ 1 << CC1K_IF_RSSI,\r
+ // PA_POW 0x0b\r
+ 0x0 << CC1K_PA_HIGHPOWER | 0xf << CC1K_PA_LOWPOWER, \r
+ // PLL 0x0c\r
+ 11 << CC1K_REFDIV, \r
+ // LOCK 0x0d\r
+ 0xe << CC1K_LOCK_SELECT,\r
+ // CAL 0x0e\r
+ 1 << CC1K_CAL_WAIT | 6 << CC1K_CAL_ITERATE, \r
+ // MODEM2 0x0f\r
+ 1 << CC1K_PEAKDETECT | 33 << CC1K_PEAK_LEVEL_OFFSET,\r
+ // MODEM1 0x10\r
+ 3 << CC1K_MLIMIT | 1 << CC1K_LOCK_AVG_MODE | CC1K_Settling << CC1K_SETTLING | 1 << CC1K_MODEM_RESET_N, \r
+ // MODEM0 0x11\r
+ 5 << CC1K_BAUDRATE | 1 << CC1K_DATA_FORMAT | 1 << CC1K_XOSC_FREQ,\r
+ // MATCH 0x12\r
+ 0x7 << CC1K_RX_MATCH | 0x0 << CC1K_TX_MATCH,\r
+ // tx current (extra)\r
+ 8 << CC1K_VCO_CURRENT | 1 << CC1K_PA_DRIVE,\r
+ },\r
+\r
+ \r
+ // 3 914.077 MHz channel, 19.2 Kbps data, Manchester Encoding, High Side LO\r
+ { // MAIN 0x00 \r
+ 0x31,\r
+ // FREQ2A,FREQ1A,FREQ0A 0x01-0x03\r
+ 0x5c,0xe0,0x00, \r
+ // FREQ2B,FREQ1B,FREQ0B 0x04-0x06\r
+ 0x5c,0xdb,0x42, \r
+ // FSEP1, FSEP0 0x07-0x8\r
+ 0x01,0xAA,\r
+ // CURRENT RX MODE VALUE 0x09 also see below\r
+ 8 << CC1K_VCO_CURRENT | 3 << CC1K_LO_DRIVE,\r
+ //0x8C, \r
+ // FRONT_END 0x0a\r
+ 1 << CC1K_BUF_CURRENT | 2 << CC1K_LNA_CURRENT | 1 << CC1K_IF_RSSI,\r
+ //0x32,\r
+ // PA_POW 0x0b\r
+ 0x8 << CC1K_PA_HIGHPOWER | 0x0 << CC1K_PA_LOWPOWER, \r
+ //0xff,\r
+ // PLL 0xc\r
+ 6 << CC1K_REFDIV, \r
+ //0x40,\r
+ // LOCK 0xd\r
+ 0x1 << CC1K_LOCK_SELECT,\r
+ //0x10,\r
+ // CAL 0xe\r
+ 1 << CC1K_CAL_WAIT | 6 << CC1K_CAL_ITERATE, \r
+ //0x26,\r
+ // MODEM2 0xf\r
+ 1 << CC1K_PEAKDETECT | 33 << CC1K_PEAK_LEVEL_OFFSET,\r
+ //0xA1,\r
+ // MODEM1 0x10\r
+ 3 << CC1K_MLIMIT | 1 << CC1K_LOCK_AVG_MODE | CC1K_Settling << CC1K_SETTLING | 1 << CC1K_MODEM_RESET_N, \r
+ //0x6f, \r
+ // MODEM0 0x11\r
+ 5 << CC1K_BAUDRATE | 1 << CC1K_DATA_FORMAT | 1 << CC1K_XOSC_FREQ,\r
+ //0x55,\r
+ // MATCH 0x12\r
+ 0x1 << CC1K_RX_MATCH | 0x0 << CC1K_TX_MATCH,\r
+ // tx current (extra)\r
+ 15 << CC1K_VCO_CURRENT | 3 << CC1K_PA_DRIVE,\r
+ },\r
+\r
+ // 4 315.178985 MHz channel, 38.4 Kbps data, Manchester Encoding, High Side LO\r
+ { // MAIN 0x00\r
+ 0x31,\r
+ // FREQ2A,FREQ1A,FREQ0A 0x01-0x03\r
+ 0x45,0x60,0x00, \r
+ // FREQ2B,FREQ1B,FREQ0B 0x04-0x06\r
+ 0x45,0x55,0xBB,\r
+ // FSEP1, FSEP0 0x07-0x08\r
+ 0X03,0x9C,\r
+ // CURRENT RX MODE VALUE 0x09 also see below\r
+ 8 << CC1K_VCO_CURRENT | 0 << CC1K_LO_DRIVE, \r
+ // FRONT_END 0x0a\r
+ 1 << CC1K_IF_RSSI,\r
+ // PA_POW 0x0b\r
+ 0x0 << CC1K_PA_HIGHPOWER | 0xf << CC1K_PA_LOWPOWER, \r
+ // PLL 0x0c\r
+ 13 << CC1K_REFDIV, \r
+ // LOCK 0x0d\r
+ 0xe << CC1K_LOCK_SELECT,\r
+ // CAL 0x0e\r
+ 1 << CC1K_CAL_WAIT | 6 << CC1K_CAL_ITERATE, \r
+ // MODEM2 0x0f\r
+ 1 << CC1K_PEAKDETECT | 33 << CC1K_PEAK_LEVEL_OFFSET,\r
+ // MODEM1 0x10\r
+ 3 << CC1K_MLIMIT | 1 << CC1K_LOCK_AVG_MODE | CC1K_Settling << CC1K_SETTLING | 1 << CC1K_MODEM_RESET_N, \r
+ // MODEM0 0x11\r
+ 5 << CC1K_BAUDRATE | 1 << CC1K_DATA_FORMAT | 0 << CC1K_XOSC_FREQ,\r
+ // MATCH 0x12\r
+ 0x7 << CC1K_RX_MATCH | 0x0 << CC1K_TX_MATCH,\r
+ // tx current (extra)\r
+ 8 << CC1K_VCO_CURRENT | 1 << CC1K_PA_DRIVE,\r
+ },\r
+\r
+ // 5 Spare\r
+ { // MAIN 0x00\r
+ 0x31,\r
+ // FREQ2A,FREQ1A,FREQ0A 0x01-0x03\r
+ 0x58,0x00,0x00, \r
+ // FREQ2B,FREQ1B,FREQ0B 0x04-0x06\r
+ 0x57,0xf6,0x85, //XBOW\r
+ // FSEP1, FSEP0 0x07-0x08\r
+ 0X03,0x55,\r
+ // CURRENT RX MODE VALUE 0x09 also see below\r
+ 8 << CC1K_VCO_CURRENT | 4 << CC1K_LO_DRIVE, \r
+ // FRONT_END 0x0a\r
+ 1 << CC1K_IF_RSSI,\r
+ // PA_POW 0x0b\r
+ 0x0 << CC1K_PA_HIGHPOWER | 0xf << CC1K_PA_LOWPOWER, \r
+ // PLL 0x0c\r
+ 12 << CC1K_REFDIV, \r
+ // LOCK 0x0d\r
+ 0xe << CC1K_LOCK_SELECT,\r
+ // CAL 0x0e\r
+ 1 << CC1K_CAL_WAIT | 6 << CC1K_CAL_ITERATE, \r
+ // MODEM2 0x0f\r
+ 1 << CC1K_PEAKDETECT | 33 << CC1K_PEAK_LEVEL_OFFSET,\r
+ // MODEM1 0x10\r
+ 3 << CC1K_MLIMIT | 1 << CC1K_LOCK_AVG_MODE | CC1K_Settling << CC1K_SETTLING | 1 << CC1K_MODEM_RESET_N, // MODEM0 0x11\r
+ 5 << CC1K_BAUDRATE | 1 << CC1K_DATA_FORMAT | 1 << CC1K_XOSC_FREQ,\r
+ // MATCH 0x12\r
+ 0x7 << CC1K_RX_MATCH | 0x0 << CC1K_TX_MATCH,\r
+ // tx current (extra)\r
+ 8 << CC1K_VCO_CURRENT | 1 << CC1K_PA_DRIVE,\r
+ },\r
+};\r
+\r
+#define UQ_CC1000_RSSI "CC1000RssiP.Rssi"\r
+\r
+#endif /* CC1000CONST_H */\r
projects / tinyos-2.x.git / blobdiff